阅读说明：本技术 使用自适应节点平衡的电源转换器设备和方法 (Power converter apparatus and method using adaptive node balancing ) 是由 乔治·威廉·奥顿 于 2018-03-23 设计创作，主要内容包括：本发明提供了一种设备,该设备包括第一绕组和第二绕组,该第一绕组和该第二绕组位于芯上并具有共同耦接到逆变器电路的第一节点的第一抽头。该设备还包括开关电路,该开关电路被配置为选择性地将第一绕组的第二抽头耦接到逆变器电路的第二节点,并且选择性地将第二绕组的第二抽头耦接到逆变器电路的第三节点。该开关电路可以被配置为提供相对于第一节点在第二节点和第三节点中的相应节点处的第一电压和第二电压的期望平衡。本发明还描述了相关方法。(An apparatus is provided that includes a first winding and a second winding on a core and having a first tap commonly coupled to a first node of an inverter circuit. The apparatus also includes a switching circuit configured to selectively couple a second tap of the first winding to a second node of the inverter circuit and to selectively couple a second tap of the second winding to a third node of the inverter circuit. The switching circuit may be configured to provide a desired balance of the first and second voltages at respective ones of the second and third nodes relative to the first node. Related methods are also described.)

1. An apparatus, comprising:

a first winding and a second winding on a core and having a first tap commonly coupled to a first node of an inverter circuit; and

a switching circuit configured to selectively couple a second tap of the first winding to a second node of the inverter circuit and to selectively couple a second tap of the second winding to a third node of the inverter circuit.

2. The apparatus of claim 1, wherein the switching circuit is configured to provide a desired balance of first and second voltages at respective ones of the second and third nodes relative to the first node.

3. The apparatus of claim 1, wherein the first winding and the second winding have a turns ratio of about 1: 1.

4. The apparatus of claim 1, wherein the switching circuit comprises:

a first switch configured to couple the second tap of the first winding to the second node;

a second switch configured to couple the second tap of the second winding to the third node; and

a control circuit configured to control the first switch and the second switch.

5. The apparatus of claim 4, wherein the control circuit is configured to operate the first and second switches at substantially the same respective first and second duty cycles.

6. The apparatus of claim 5, wherein the first duty cycle and the second duty cycle are each less than or equal to about 50%.

7. The apparatus of claim 4, wherein the first and second duty cycles allow flux in the core to return to substantially zero during periods when the first and second switches are open.

8. The apparatus of claim 4, wherein the first and second switches comprise respective first and second transistors.

9. The apparatus of claim 4, wherein the core comprises a first core, and wherein the apparatus further comprises:

a third winding and a fourth winding on a second core and having a first tap commonly coupled to the first node;

a third switch configured to selectively couple a second tap of the third winding to the second node; and

a fourth switch configured to selectively couple a second tap of the fourth winding to the third node,

wherein the control circuit is further configured to control the third switch and the fourth switch.

10. The apparatus of claim 9, wherein the control circuit is configured to operate the third and fourth switches at respective third and fourth duty cycles that are complementary to the first and second duty cycles.

11. The apparatus of claim 9, wherein the inverter circuit comprises a multi-level inverter circuit.

12. The apparatus of claim 1, wherein the first node comprises a neutral line of an output of the inverter circuit.

13. An apparatus, comprising:

a DC link including a first DC bus and a second DC bus;

a balancer circuit coupled to the first DC bus and the second DC bus and comprising:

a first winding and a second winding on a core and having a first tap commonly coupled to a neutral;

first and second switches configured to selectively couple a second tap of a respective one of the first and second windings to a respective one of the first and second DC buses; and

a control circuit configured to control the first and second switches to balance a voltage between the first and second DC buses and the neutral line.

14. The apparatus of claim 13, wherein the control circuit is configured to operate each of the first switch and the second switch at a duty cycle of less than or equal to about 50%.

15. The apparatus of claim 14:

wherein the core comprises a first core;

wherein the apparatus further comprises:

a third winding and a fourth winding on a second core and having a first tap commonly coupled to the neutral; and

third and fourth switches configured to selectively couple second taps of the third and fourth windings to second taps of respective ones of the third and fourth windings; and is

Wherein the control circuit is further configured to control the third and fourth switches to balance the voltage between the first and second DC buses and the neutral line.

16. A method of operating an inverter, the method comprising:

providing a first winding and a second winding, the first winding and the second winding being located on a core and having a first tap commonly coupled to a first node of the inverter; and

selectively coupling a second tap of the first winding to a second node of the inverter and selectively coupling a second tap of the second winding to a third node of the inverter to balance a first voltage and a second voltage at the second node and the third node relative to the first node.

17. The method of claim 16, wherein the first winding and the second winding have a turns ratio of about 1: 1.

18. The method of claim 16, wherein selectively coupling a second tap of the first winding to a second node of the inverter and selectively coupling a second tap of the second winding to a third node of the inverter to balance first and second voltages at the second and third nodes relative to the first node comprises: operating a first switch at a first duty cycle to couple the second tap of the first winding to the second node and operating a second switch at a second duty cycle to couple the second tap of the second winding to the third node, the second duty cycle being substantially the same as the first duty cycle.

19. The method of claim 18, wherein the first duty cycle and the second duty cycle are each less than or equal to about 50%.

20. The method of claim 16, wherein the first node comprises a neutral line.

Background

The subject matter of the present disclosure relates to power converter devices, and more particularly, to power converter devices having a DC bus.

Power converter devices, such as Uninterruptible Power Supply (UPS) systems and grid-tie inverters, typically include an inverter that receives power from a DC link. The inverter may produce a single-phase or three-phase output referenced to the neutral line, and the DC link may include first and second buses having respective positive and negative voltages relative to the neutral line.

Unbalanced loads can cause DC bus imbalance problems in three-phase inverter systems. In particular, loading one phase of the inverter output substantially more than the other phases may cause the voltages on the positive and negative DC buses of the DC link to be unbalanced relative to the voltage on the neutral line of the inverter. Such problems may be solved by using a "balancer" circuit that intermittently couples the DC bus to the neutral line, such as described in U.S. patent No. 6,483,730 to Johnson, jr. However, such conventional balancer circuits may generate undesirable ripple currents even when the load is unbalanced.

Disclosure of Invention

Some embodiments of the inventive subject matter provide an apparatus that includes a first winding and a second winding on a core and having a first tap commonly coupled to a first node of an inverter circuit. The apparatus also includes a switching circuit configured to selectively couple a second tap of the first winding to a second node of the inverter circuit and to selectively couple a second tap of the second winding to a third node of the inverter circuit. The switching circuit may be configured to provide a desired balance of the first and second voltages at respective ones of the second and third nodes relative to the first node. In some embodiments, the first node may be a neutral line, and the second and third nodes may be first and second DC buses. In further embodiments, the first, second, and third nodes may be nodes corresponding to various output levels of the multi-level inverter.

The switching circuit may include: a first switch (e.g., a first transistor) configured to couple a second tap of the first winding to a second node; a second switch (e.g., a second transistor) configured to couple a second tap of the second winding to a third node; and a control circuit configured to control the first switch and the second switch. The control circuit may be configured to operate the first and second switches at substantially the same respective first and second duty cycles. The first and second duty cycles may each be less than or equal to about 50% and may be configured to allow flux return in the core to be substantially zero during periods when the first and second switches are open.

In further embodiments, the apparatus may further include a third winding and a fourth winding on the second core and having a first tap commonly coupled to the first node. The third switch may be configured to selectively couple a second tap of the third winding to the second node, and the fourth switch may be configured to selectively couple a second tap of the fourth winding to the third node. The control circuit may be further configured to control the third switch and the fourth switch. In some embodiments, the control circuit may be configured to operate the third and fourth switches at respective third and fourth duty cycles that are complementary to the first and second duty cycles.

Further embodiments of the inventive subject matter provide an apparatus that includes a DC link including first and second DC buses and a balancer circuit coupled to the first and second DC buses. The balancer circuit includes: a first winding and a second winding on the core and having a first tap commonly coupled to the neutral; first and second switches configured to selectively couple second taps of respective ones of the first and second windings to respective ones of the first and second DC buses; and a control circuit configured to control the first and second switches to balance the voltage between the first and second DC buses and the neutral line. The apparatus may further comprise: a third winding and a fourth winding on the second core and having a first tap commonly coupled to the neutral; and third and fourth switches configured to selectively couple second taps of the third and fourth windings to second taps of respective ones of the third and fourth windings. The control circuit may be further configured to control the third and fourth switches to balance the voltage between the first and second DC buses and the neutral line.

Still other embodiments provide a method of operating an inverter, the method comprising: providing a first winding and a second winding, the first and second windings being located on the core and having a first tap commonly coupled to a first node of the inverter; and selectively coupling a second tap of the first winding to a second node of the inverter and selectively coupling a second tap of the second winding to a third node of the inverter to balance the first voltage and the second voltage at the second node and the third node relative to the first node.

Drawings

Fig. 1 is a schematic diagram illustrating a balancer circuit according to some embodiments.

Fig. 2 is a waveform diagram illustrating operation of the balancer circuit of fig. 1 according to some embodiments.

Fig. 3 is a schematic diagram illustrating an exemplary application of a balancer circuit according to some embodiments.

Fig. 4 is a schematic diagram illustrating an interleaved balancer circuit according to further embodiments.

Fig. 5 is a waveform diagram illustrating an operation of the balancer circuit of fig. 4.

Fig. 6 is a schematic diagram illustrating a 3-level inverter circuit application of the balancer circuit of fig. 4, according to some embodiments.

Fig. 7 is a schematic diagram illustrating a 5-level inverter circuit application of a balancer circuit according to further embodiments.

Detailed Description

Specific exemplary embodiments of the present subject matter will now be described with reference to the accompanying drawings. The inventive subject matter may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive subject matter to those skilled in the art. In the drawings, like numbering represents like items. It will be understood that when an item is referred to as being "connected" or "coupled" to another item, it can be directly connected or directly coupled to the other item or intervening items may be present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless expressly specified otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, items, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, items, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a balancer circuit 100 according to some embodiments of the present subject matter. The balancer circuit 100 includes a switching circuit configured to selectively couple first taps of the first and second windings L1, L2 of the transformer 110 to respective ones of the first and second DC busses 105a, 105 b. Windings L1, L2 are disposed on a common core 112, and the windings L1, L2 have a second tap commonly coupled to the neutral line N. More specifically, the switching circuit includes a first switch S1 that connects a first tap of the first winding L1 to the first DC bus 105a, and a second switch S2 that connects a first tap of the second winding L2 to the second DC bus 105 b. A first diode D1 connects the first tap of the second winding L2 to the first DC bus 105a, and a second diode D2 connects the first tap of the first winding L1 to the second DC bus 105 b.

The windings L1, L2 preferably have a turns ratio of about 1:1, and the balancer circuit 100 balances the voltages V +, V-on the first and second DC busses 105a, 105b with respect to the neutral line N using this unit turns ratio. In some embodiments, the control circuit 120 controls the switches S1, S2 such that the switches S1, S2 operate at substantially the same duty cycle. Specifically, when the first switch S1 and the second switch S2 are conductive, a 1:1 turn ratio drives the magnitudes of the voltages V +, V-toward equilibrium. The first switch S1 and the second switch S2 then turn off to initiate discharge of the first winding L1 and the second winding L2 via the first diode D1 and the second diode D2 and allow the flux in the core 112 to drop to zero before the first switch S1 and the second switch S2 turn on again. In some embodiments, the first switch S1 and the second switch S2 may operate at a duty cycle of approximately 50%, as shown in fig. 2. In some embodiments, the duty cycle may be less than 50% as shown in fig. 2, but a reduced duty cycle may result in less than desirable performance (e.g., increased ripple current).

It should be appreciated that the balancer circuit 100 may be implemented using any of a number of different types of components. For example, in some embodiments, the first switch S1 and the second switch S2 may be implemented using transistors, such as Insulated Gate Bipolar Transistors (IGBTs) or power MOSFETs, or other types of semiconductor switches. The first switch S1 and the second switch S2 may be bi-directional, for example, such that if IGBTs are used for the first switch S1 and the second switch S2, then the respective anti-parallel diodes may be used with the IGBTs to provide bi-directionality (the MOSFETs may have intrinsic body diodes, which may eliminate the need for separate anti-parallel diodes). Control circuit 120 may be implemented using any of a variety of different analog circuit components and/or digital circuit components. For example, the control circuit 120 may be implemented using a data processing device (such as a microcontroller) and peripheral circuits configured to drive the first switch S1 and the second switch S2. In some embodiments, the switches S1, S2 may be controlled using analog circuitry and/or discrete digital circuitry that provide similar functionality.

Fig. 3 illustrates an exemplary application of the balancer circuit 100 according to further embodiments. In particular, fig. 3 shows a power converter arrangement that may be used, for example, in an uninterruptible power supply. The first and second DC buses 105a, 105b receive power from a rectifier circuit 130, which may be coupled to an AC power source (such as a utility power source and/or a motor/generator set). The first and second DC busses 105a, 105b may also be coupled to a DC power source (such as a battery, fuel cell, and/or photovoltaic power source). The first and second DC buses 105a, 105b are coupled to an inverter circuit 140, which may be coupled to a load. For example, inverter circuit 140 may be a three-phase inverter circuit for supplying power to a power distribution system in a data center or other environment. Along the lines discussed above, if the inverter circuit 140 produces an AC output of 50/60Hz, the balancer circuit 100 may operate the first switch S1 and the second switch S2 at a duty cycle of about 50% to equalize the magnitudes of the voltages V +, V-on the first DC bus 105a and the second DC bus 105b, for example, at a substantially higher frequency (e.g., 10kHz) to compensate for the unbalanced loading of the inverter circuit 140.

According to further embodiments, improved performance may be achieved by using multiple balancer circuits operating in an at least partially staggered manner. Referring to fig. 4, a balancer system may include first and second balancer circuits 400a and 400b coupled to first and second DC buses 405a and 405 b. The first balancer circuit 400 includes the first transformer 410a, the first and second switches S1 and S2, and the first and second diodes D1 and D2 arranged as discussed above with reference to fig. 1. The second balancer circuit 400b includes a second transformer 410b, third and fourth switches S3 and S4, and third and fourth diodes D3 and D4, which are similarly arranged. The control circuit 420 operates the first pair of switches S1, S2 and the second pair of switches S3, S4 in an interleaved manner. For example, as shown in fig. 5, the switches S1, S2 of the first balancer circuit 400a may operate in unison at a first 50% duty cycle, and the switches S3, S4 of the second balancer circuit 400b may operate in unison at a second 50% duty cycle that is complementary to (180 ° offset from) the first duty cycle. This arrangement may provide reduced ripple current since at least one of the first balancer circuit 400a and the second balancer circuit 400b is active at any given time. Such an arrangement may be particularly advantageous when used with a multi-level inverter circuit, such as the three-level inverter circuit 600 shown in fig. 6. However, it should be understood that such an arrangement may also be advantageously used with a two-level inverter circuit.

In further embodiments, a combination of balancer circuits along the above lines may be used with higher order multi-level inverter circuits to balance the voltages at the various nodes of the inverter circuits. For example, as shown in fig. 7, the first balancer circuit 700a may be used to balance the voltages V1, V2 across the first pair of bus capacitors C1, C2 associated with the upper portion of the 5-level inverter circuit 710, i.e., to equalize the magnitudes of the voltage V + on the first DC bus 705a and the voltage at the neutral line N with respect to the middle first node N1 of the inverter circuit 710. The second balancer circuit 700b may similarly be used to balance the voltages V3, V4 across the second pair of bus capacitors C3, C4 associated with the lower portion of the 5-level inverter circuit 710, i.e., to equalize the voltage at the neutral line N and the voltage V-on the second DC bus 705b with respect to the magnitude of the intermediate second node N2 of the inverter circuit 710. The third balancer circuit 700c may be used to balance the voltages V +, V-on the first and second DC bus lines 705a, 705b with respect to the neutral line N. The first balancer circuit 700a, the second balancer circuit 700b, and the third balancer circuit 700c may have any configuration described above with reference to fig. 1 to 6. For example, each of the first balancer circuit 700a, the second balancer circuit 700b, and the third balancer circuit 700c may have a single configuration as shown in fig. 1 or a double configuration as shown in fig. 5.

In the drawings and specification, there have been disclosed exemplary embodiments of the inventive subject matter. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the inventive subject matter being defined by the following claims.