阅读说明：本技术 一种tdm背板总线测试方法、测试装置及存储介质 (TDM backplane bus test method, test device and storage medium ) 是由 孟庆晓 谭冰 郭军勇 于 2019-08-23 设计创作，主要内容包括：本发明公开了一种TDM背板总线测试方法、测试装置及存储介质,所述TDM背板总线测试方法包括：当主控板、媒体板以及用户线路单板启动时,控制所述媒体板启动多个误比特率测试通道；将每个所述误比特率测试通道的时隙进行标记,并选取预设时隙作为所述用户线路单板中每个槽位的数据传输时隙；将每个所述误比特率测试通道的时隙与所述用户线路单板的时隙进行联网,并通过多个所述误比特率测试通道测试TDM背板总线的通断状态。本发明通过在媒体板上设置多条并行的误比特率测试通道,并通过多个误比特率测试通道同时对TDM背板总线进行测试,以提高对TDM背板总线的测试效率。(The invention discloses a TDM backboard bus testing method, a testing device and a storage medium, wherein the TDM backboard bus testing method comprises the following steps: when the main control board, the media board and the user line single board are started, controlling the media board to start a plurality of bit error rate test channels; marking the time slot of each bit error rate test channel, and selecting a preset time slot as the data transmission time slot of each slot position in the user line single board; and networking the time slot of each bit error rate test channel and the time slot of the user line single board, and testing the on-off state of the TDM backboard bus through a plurality of bit error rate test channels. The invention sets a plurality of parallel bit error rate test channels on the media board and tests the TDM backboard bus through the plurality of bit error rate test channels simultaneously so as to improve the test efficiency of the TDM backboard bus.)

1. A TDM backplane bus test method is characterized by comprising the following steps:

when the main control board, the media board and the user line single board are started, controlling the media board to start a plurality of bit error rate test channels;

marking the time slot of each bit error rate test channel, and selecting a preset time slot as the data transmission time slot of each slot position in the user line single board;

and networking the time slot of each bit error rate test channel and the time slot of the user line single board, and testing the on-off state of the TDM backboard bus through a plurality of bit error rate test channels.

2. The TDM backplane bus testing method according to claim 1, wherein when the main control board, the media board and the user line single board are started, before controlling the media board to start the plurality of bit error rate testing channels, the method comprises the following steps:

detecting whether the power-on states of the main control board, the media board and the user line single board are in a normal state;

and when the power-on states of the main control board, the media board and the user line single board are in normal states, starting the main control board, the media board and the user line single board.

3. The TDM backplane bus testing method according to claim 2, wherein the controlling the media board to start a plurality of bit error rate testing channels when the main control board, the media board and the user line single board are started comprises the following steps:

when the main control board, the media board and the user line single board are started, sending a control instruction to the media board through the main control board;

and the media board receives the control instruction and controls the digital signal processing module to start a plurality of bit error rate test channels.

4. The TDM backplane bus testing method according to claim 3, wherein marking the time slot of each bit error rate test channel, and selecting a preset time slot as a data transmission time slot of each slot in the subscriber line board specifically comprises the following steps:

acquiring a time slot corresponding to each bit error rate test channel, and marking the time slot corresponding to each bit error rate test channel according to a preset sequence;

and acquiring the slot position information of each slot position in the subscriber line single board, and selecting a preset time slot as a data transmission time slot of each slot position in the subscriber line single board.

5. The TDM backplane bus testing method according to claim 4, wherein networking the time slot of each bit error rate testing channel with the time slot of the subscriber line board, and testing the on-off state of the TDM backplane bus through the plurality of bit error rate testing channels specifically comprises the steps of:

networking the time slot of each bit error rate test channel with the time slot of the user line single board;

selecting a test mode in an editable logic device in the subscriber line single board;

and testing the on-off state of the TDM backboard bus through a plurality of bit error rate test channels.

6. The TDM backplane bus testing method according to claim 5, wherein the step of testing the on-off state of the TDM backplane bus through the plurality of bit error rate testing channels specifically comprises the steps of:

controlling the digital signal processing module to send random test data to the subscriber line single board;

the user line single board receives the random test data and returns the random test data to the digital signal processing module according to the test mode;

and the digital signal processing module detects whether the random test data is changed or not and judges the on-off state of the TDM backboard bus.

7. The TDM backplane bus testing method of claim 6, wherein the random test data is sent to the main control board through the bit error rate test channel, and is sent to the subscriber line single board through the main control board.

8. The TDM backplane bus testing method according to claim 6, wherein the step of networking the time slot of each bit error rate testing channel with the time slot of the subscriber line board and testing the on-off state of the TDM backplane bus through the plurality of bit error rate testing channels comprises the following steps:

and uploading the judgment result of the digital signal processing module to the main control board, and displaying the on-off state of the TDM backboard bus on a display screen of the main control board.

9. A TDM backboard bus test device is characterized by comprising a main control board, a media board and a user line single board; the media board and the user line single board are respectively electrically connected with the main control board; the media board is internally provided with a digital signal processing module, and the digital signal processing module is used for starting a bit error rate test channel so as to test the on-off state of the TDM backboard bus; the user line single board is provided with an editable logic device, and the editable logic device is used for selecting a TDM backboard bus and selecting a test mode during testing;

the main control board is provided with a time slot exchange chip, a processor and a memory connected with the processor; the time slot exchanging chip is used for networking the time slot of each bit error rate testing channel and the time slot of the user line single board; the memory stores a TDM backplane bus test program, and the TDM backplane bus test program is used for implementing the TDM backplane bus test method according to any one of claims 1 to 8 when executed by the processor.

10. A storage medium storing a TDM backplane bus test program, wherein the TDM backplane bus test program is used for implementing the TDM backplane bus test method according to any one of claims 1 to 8 when the TDM backplane bus test program is executed by a processor.

Technical Field

The invention relates to the field of backboard test equipment application, in particular to a TDM backboard bus test method, a test device and a storage medium.

Background

A TDM (time division multiplexing mode) backplane bus is a common bus design mode for VoIP (voice over internet protocol) products, and generally, multi-slot equipment transmits time slot exchanged data through the TDM bus; when the time slot switching chip is installed, the chip is placed on a main control board and then is connected with each service slot position through a back board TDM bus; because some process problems in production cannot ensure that the connection between each service board and the TDM bus of the main control board is normal, when the TDM backplane bus is produced, it is required to test whether the TDM bus is working normally, but the TDM backplane bus is too many, and the efficiency of a general test mode is too low.

Accordingly, the prior art is yet to be improved and developed.

Disclosure of Invention

The invention provides a TDM backplane bus testing method, a testing device and a storage medium, aiming at the defects of the prior art, and aims to improve the testing efficiency of the TDM backplane bus by arranging a plurality of parallel bit error rate testing channels on a media board and simultaneously testing the TDM backplane bus by the plurality of bit error rate testing channels.

The technical scheme adopted by the invention for solving the technical problem is as follows:

the invention provides a TDM backboard bus testing method, wherein the TDM backboard bus testing method comprises the following steps:

when the main control board, the media board and the user line single board are started, controlling the media board to start a plurality of bit error rate test channels;

marking the time slot of each bit error rate test channel, and selecting a preset time slot as the data transmission time slot of each slot position in the user line single board;

and networking the time slot of each bit error rate test channel and the time slot of the user line single board, and testing the on-off state of the TDM backboard bus through a plurality of bit error rate test channels.

Further, when the main control board, the media board and the user line single board are started, the following steps are included before the media board is controlled to start the multiple bit error rate test channels:

detecting whether the power-on states of the main control board, the media board and the user line single board are in a normal state;

and when the power-on states of the main control board, the media board and the user line single board are in normal states, starting the main control board, the media board and the user line single board.

Further, when the main control board, the media board and the user line single board are started, controlling the media board to start the multiple bit error rate test channels specifically includes the following steps:

when the main control board, the media board and the user line single board are started, sending a control instruction to the media board through the main control board;

and the media board receives the control instruction and controls the digital signal processing module to start a plurality of bit error rate test channels.

Further, marking the time slot of each bit error rate test channel, and selecting a preset time slot as a data transmission time slot of each slot position in the subscriber line board specifically includes the following steps:

acquiring a time slot corresponding to each bit error rate test channel, and marking the time slot corresponding to each bit error rate test channel according to a preset sequence;

and acquiring the slot position information of each slot position in the subscriber line single board, and selecting a preset time slot as a data transmission time slot of each slot position in the subscriber line single board.

Further, networking the time slot of each bit error rate test channel with the time slot of the subscriber line board, and testing the on-off state of the TDM backplane bus through the plurality of bit error rate test channels specifically includes the following steps:

networking the time slot of each bit error rate test channel with the time slot of the user line single board;

selecting a test mode in an editable logic device in the subscriber line single board;

and testing the on-off state of the TDM backboard bus through a plurality of bit error rate test channels.

Further, the step of testing the on-off state of the TDM backplane bus by using the multiple bit error rate test channels specifically includes the following steps:

controlling the digital signal processing module to send random test data to the subscriber line single board;

the user line single board receives the random test data and returns the random test data to the digital signal processing module according to the test mode;

and the digital signal processing module detects whether the random test data is changed or not and judges the on-off state of the TDM backboard bus.

Further, the random test data is sent to the main control board through the bit error rate test channel, and is sent to the user line board through the main control board.

Further, the step of networking the time slot of each bit error rate test channel with the time slot of the subscriber line board, and testing the on-off state of the TDM backplane bus through the plurality of bit error rate test channels includes the following steps:

and uploading the judgment result of the digital signal processing module to the main control board, and displaying the on-off state of the TDM backboard bus on a display screen of the main control board.

The invention also provides a TDM backboard bus testing device, which comprises a main control board, a media board and a user line single board; the media board and the user line single board are respectively electrically connected with the main control board; the media board is internally provided with a digital signal processing module, and the digital signal processing module is used for starting a bit error rate test channel so as to test the on-off state of the TDM backboard bus; the user line single board is provided with an editable logic device, and the editable logic device is used for selecting a TDM backboard bus and selecting a test mode during testing;

the main control board is provided with a time slot exchange chip, a processor and a memory connected with the processor; the time slot exchanging chip is used for networking the time slot of each bit error rate testing channel and the time slot of the user line single board; the memory stores a TDM backplane bus test program, and the TDM backplane bus test program is used for realizing the TDM backplane bus test method when being executed by the processor.

The invention also provides a storage medium, wherein the storage medium stores a TDM backplane bus test program, and the TDM backplane bus test program is used for realizing the TDM backplane bus test method when being executed by a processor.

The invention adopts the technical scheme and has the following effects:

the invention sets a plurality of bit error rate test channels on the media board, respectively tests a plurality of TDM backboard buses by using the plurality of bit error rate test channels, and tests in a loopback test mode during testing, so that the on-off state of the plurality of TDM backboard buses can be quickly tested, thereby improving the test efficiency of the TDM backboard buses.

Drawings

FIG. 1 is a flow chart of a preferred embodiment of the TDM backplane bus test method of the present invention.

Fig. 2 is a schematic diagram of TDM backplane bus testing of the present invention.

Fig. 3 is a test schematic diagram of a loopback test mode of the present invention.

FIG. 4 is a functional schematic of the test apparatus of the present invention.

In the figure: 100. a main control board; 200. a media board; 300. a subscriber line single board; 110. a processor; 120. a memory; 210. a digital signal processing module; 310. the logic can be edited.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.