阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 梅本康成 大部功 井手野馨 小屋茂树 于 2019-06-14 设计创作，主要内容包括：本发明提供能够增大过渡电压而将SOA扩大的半导体装置。配置于基板之上的集电极层、基极层、以及发射极层构成双极晶体管。发射极电极与发射极层进行欧姆接触。发射极层具有在俯视观察时在一个方向上较长的形状。发射极层跟发射极电极进行欧姆接触的欧姆接触界面与发射极层间的在发射极层的长边方向上的尺寸差大于发射极层与欧姆接触界面间的在发射极层的宽度方向上的尺寸差。(The invention provides a semiconductor device capable of increasing a transition voltage and expanding an SOA. The collector layer, the base layer, and the emitter layer disposed on the substrate constitute a bipolar transistor. The emitter electrode makes ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in a plan view. The size difference between the ohmic contact interface of the emitter layer and the emitter electrode in ohmic contact with each other in the long side direction of the emitter layer is larger than the size difference between the emitter layer and the ohmic contact interface in the width direction of the emitter layer.)

1. A semiconductor device, comprising:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor; and

an emitter electrode in ohmic contact with the emitter layer,

the emitter layer has a shape that is long in one direction when viewed from above,

the size difference between the ohmic contact interface and the emitter layer in the long side direction of the emitter layer is larger than the size difference between the emitter layer and the ohmic contact interface in the width direction of the emitter layer, wherein the ohmic contact interface is the ohmic contact interface where the emitter layer and the emitter electrode make ohmic contact.

2. The semiconductor device according to claim 1,

the difference in dimension in the long-side direction of the emitter layer between the emitter layer and the ohmic contact interface is 10 times or more the difference in dimension in the width direction of the emitter layer between the emitter layer and the ohmic contact interface.

3. The semiconductor device according to claim 2,

at both ends of the emitter layer in the long-side direction, a distance in the long-side direction of the emitter layer from the end of the emitter layer in the long-side direction to the ohmic contact interface is 5 times or more a difference in dimension between the emitter layer and the ohmic contact interface in the width direction of the emitter layer.

4. The semiconductor device according to any one of claims 1 to 3,

at least one end of the emitter layer in the longitudinal direction has a distance of 3 [ mu ] m or more in the longitudinal direction from the end of the emitter layer in the longitudinal direction to the ohmic contact interface.

5. A semiconductor device, comprising:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in an insulating film,

the emitter layer has a shape that is long in one direction when viewed from above,

the size difference between the emitter layer and the contact hole in the long side direction of the emitter layer is larger than the size difference between the emitter layer and the contact hole in the width direction of the emitter layer.

6. The semiconductor device according to claim 5,

the difference in dimension between the emitter layer and the contact hole in the long-side direction of the emitter layer is 10 times or more the difference in dimension between the emitter layer and the contact hole in the width direction of the emitter layer.

7. The semiconductor device according to claim 6,

at both ends of the emitter layer in the long-side direction, a distance in the long-side direction of the emitter layer from the end of the emitter layer in the long-side direction to the contact hole is 5 times or more a difference in size between the emitter layer and the contact hole in the width direction of the emitter layer.

8. The semiconductor device according to any one of claims 5 to 7,

at least one end portion of the emitter layer in the longitudinal direction has a distance of 4 [ mu ] m or more in the longitudinal direction from the end portion of the emitter layer in the longitudinal direction to the contact hole.

9. A semiconductor device, comprising:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor; and

an emitter electrode in ohmic contact with the emitter layer,

the emitter layer has a shape that is long in one direction in a plan view, and an ohmic contact interface where the emitter layer and the emitter electrode make ohmic contact has a planar shape in which at least 1 vertex of a rectangle is chamfered.

10. The semiconductor device according to claim 9,

a distance in the longitudinal direction of the emitter layer from an end in the longitudinal direction of the emitter layer to a farthest position of the chamfered portion of the ohmic contact interface is 3 μm or more.

11. A semiconductor device, comprising:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in an insulating film,

the emitter layer has a shape that is long in one direction in a plan view, and the contact hole has a planar shape in which at least 1 vertex of a rectangle is chamfered.

12. The semiconductor device according to claim 11,

a distance in the longitudinal direction of the emitter layer from an end in the longitudinal direction of the emitter layer to a farthest position of a chamfered portion of the contact hole is 4 μm or more.

13. A semiconductor device, comprising:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in an insulating film,

the emitter layer has a shape that is long in one direction,

an emitter access resistance at least one end portion of the emitter layer is 5 times or more as large as the emitter access resistance at a central portion of the emitter layer, wherein the emitter access resistance is an electrical resistance from a junction interface between the emitter layer and the base layer to the emitter electrode.

14. The semiconductor device according to claim 13,

the emitter access resistance is formed by the emitter layer.

Technical Field

The present invention relates to a semiconductor device.

Background

As an active element constituting a power amplifier module of a mobile terminal, a Heterojunction Bipolar Transistor (HBT) is mainly used (patent document 1). The desired characteristics required for the HBT include various items such as high efficiency, high gain, high output, and high withstand voltage. In envelope tracking systems of recent interest, HBTs operating at high collector voltages are required. In order to realize high-voltage operation of the HBT, it is necessary to expand a Safe Operating Area (SOA).

Patent document 1: japanese patent laid-open publication No. 2005-101402

In the graph showing the collector current-collector voltage characteristics (Ic-Vce characteristics), when the collector voltage of the HBT is increased, the boundary line (SOA line) between the inside of the SOA and the outside of the SOA gradually decreases. According to the evaluation experiments by the inventors of the present application, it was found that at a certain collector voltage, a phenomenon in which the SOA line discontinuously decreases occurred. The collector voltage at which the SOA line discontinuously decreases is referred to as a transition voltage (transition voltage).

If the operating voltage is set to be approximately the same as or higher than the transition voltage, there is a high risk that the actual operating range deviates from the range of the SOA when a load variation occurs during the operation of the HBT. If the operating range deviates from the range of the SOA, the HBT may be damaged. In order to operate at a high collector voltage without damaging the HBT even if load fluctuations occur, it is desirable to increase the transient voltage and expand the SOA.

Disclosure of Invention

The invention provides a semiconductor device capable of increasing a transition voltage and expanding an SOA.

According to an aspect of the present invention, there is provided a semiconductor device including:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor; and

an emitter electrode in ohmic contact with the emitter layer,

the emitter layer has a shape that is long in one direction in a plan view,

a dimension difference between an ohmic contact interface, which is an ohmic contact interface where the emitter layer and the emitter electrode make ohmic contact, and the emitter layer in a longitudinal direction of the emitter layer is larger than a dimension difference between the emitter layer and the ohmic contact interface in a width direction of the emitter layer.

According to another aspect of the present invention, there is provided a semiconductor device including:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in the insulating film,

the emitter layer has a shape that is long in one direction in a plan view,

the difference in dimension in the longitudinal direction of the emitter layer between the emitter layer and the contact hole is larger than the difference in dimension in the width direction of the emitter layer between the emitter layer and the contact hole.

According to still another aspect of the present invention, there is provided a semiconductor device including:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor; and

an emitter electrode in ohmic contact with the emitter layer,

the emitter layer has a shape elongated in one direction in a plan view, and an ohmic contact interface at which the emitter layer and the emitter electrode make ohmic contact has a planar shape in which at least 1 vertex of a rectangle is chamfered.

According to still another aspect of the present invention, there is provided a semiconductor device including:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in the insulating film,

the emitter layer has a shape elongated in one direction in a plan view, and the contact hole has a planar shape in which at least 1 vertex of a rectangle is chamfered.

According to still another aspect of the present invention, there is provided a semiconductor device including:

a collector layer, a base layer, and an emitter layer disposed on the substrate to form a bipolar transistor;

an emitter electrode in ohmic contact with the emitter layer; and

an emitter wiring connected to the emitter electrode through a contact hole provided in the insulating film,

the emitter layer has a shape that is long in one direction,

an emitter contact resistance at least one end of the emitter layer is 5 times or more greater than the emitter contact resistance at a central portion of the emitter layer, wherein the emitter contact resistance is an electrical resistance from a junction interface between the emitter layer and the base layer to the emitter electrode.

If the arrangement of the emitter electrode, the shape of the emitter electrode, the arrangement of the contact hole for the emitter, or the shape of the contact hole for the emitter is formed as described above, the transient voltage can be increased to expand the SOA.

Drawings

Fig. 1 is a plan view of an HBT as a reference example to be subjected to an evaluation experiment.

Fig. 2 is a graph showing the measurement results of the SOA line of the HBT.

Fig. 3 is a graph showing the actual measurement result of the collector current-base voltage characteristic (Ic-Vb characteristic).

Fig. 4 is a plan view of the semiconductor device of embodiment 1.

Fig. 5 is a cross-sectional view of the one-dot chain line 5-5 of fig. 4.

Fig. 6 is a cross-sectional view of the one-dot chain line 6-6 of fig. 4.

Fig. 7 is a plan view of the vicinity of the emitter layer of the semiconductor device of embodiment 1, and a graph showing an example of temperature distribution in the long side direction of the emitter layer in operation.

Fig. 8A is a plan view of an emitter layer, an ohmic contact interface, and a base electrode of an HBT manufactured for evaluation of the transition voltage Vt, and fig. 8B is a graph showing a measurement result of the transition voltage Vt.

Fig. 9 is a graph showing the measurement results of the SOA line of the sample corresponding to the HBT of example 1 (fig. 4) and the sample corresponding to the HBT of the reference example (fig. 1).

Fig. 10A, 10B, and 10C are plan views showing positional relationships among the emitter layer, the emitter electrode, the ohmic contact interface, the contact hole, and the emitter wiring.

Fig. 11 is a graph showing the measurement results of the transition voltage Vt of the sample, and the positional relationship of the emitter layer, the emitter wiring, and the ohmic contact interface of the sample has the relationship shown in fig. 10B and 10C.

Fig. 12 is a plan view of a semiconductor device according to a modification of embodiment 1.

Fig. 13 is a cross-sectional view of a semiconductor device according to another modification of embodiment 1.

Fig. 14A is a plan view of an emitter layer, an emitter electrode, and an emitter wiring of the semiconductor device of embodiment 2, and fig. 14B is a schematic sectional view of one-dot chain line 14B-14B of fig. 14A.

Fig. 15A is a plan view of an emitter layer, a contact hole, and a base electrode of the HBT manufactured for evaluation of the transition voltage Vt, and fig. 15B is a graph showing a measurement result of the transition voltage Vt.

Fig. 16 is a plan view of the emitter layer, the emitter electrode, the contact hole, and the emitter wiring of the semiconductor device of embodiment 3.

Fig. 17 is a top view of the semiconductor device of example 4.

Fig. 18 is a top view of the semiconductor device of embodiment 5.

Fig. 19 is a top view of the semiconductor device of embodiment 6.

Fig. 20 is a top view of the semiconductor device of embodiment 7.

Fig. 21 is a top view of the semiconductor device of embodiment 8.

Fig. 22 is a top view of the semiconductor device of embodiment 9.

Fig. 23A, 23B, and 23C are plan views of the emitter layer, the emitter electrode, the contact hole, and the ohmic contact interface of the semiconductor device according to embodiment 10 and its modified example.

Fig. 24 is a top view of the semiconductor device of embodiment 11.

Fig. 25 is a top view of the semiconductor device of embodiment 12.

Description of reference numerals:

an emitter layer; an emitter layer in the narrow sense; a cap layer; a contact layer; an emitter electrode; a contact hole; emitter wiring; an ohmic contact interface; a central region of the emitter layer; an end region of the emitter layer; bevel edge; a subcollector layer; a collector layer; a collector electrode; 43.. contact holes; a collector wiring; a base layer; a base electrode; a base electrode main portion; a base electrode pad portion; 53.. contact holes; a base wiring; a substrate; 61.. an insulating film; a unit transistor; 71.. emitter common wiring (ground wiring); a via hole; high frequency input wiring; 76.. MIM structured capacitors; 77... sheet resistance; 78..

Detailed Description

Before describing the embodiment, a factor that hinders the SOA expansion in a general HBT is described based on an evaluation experiment performed by the inventors of the present application with reference to the drawings of fig. 1 to 3.

Fig. 1 is a plan view of an HBT as a reference example to be subjected to an evaluation experiment. A sub-electrode layer 40 made of a conductive semiconductor is provided on a surface layer portion of the substrate. Above the sub-collector layer 40, a collector layer 41 and a base layer 51 are arranged. The collector layer 41 is aligned with the base layer 51 in a plan view, and is disposed inside the subcollector layer 40. The emitter layer 31 is disposed on the base layer 51. The emitter layer 31 is disposed inside the base layer 51 in a plan view. The collector layer 41, the base layer 51, and the emitter layer 31 constitute a bipolar transistor, such as an HBT.

The emitter layer 31 has a planar shape that is long in one direction (lateral direction in fig. 1) in a plan view. The planar shape of the emitter layer 31 is rectangular, for example. An emitter electrode 32 is disposed on the emitter layer 31. The emitter electrode 32 is formed of metal and makes ohmic contact with the emitter layer 31. The interface where the emitter electrode 32 makes ohmic contact with the emitter layer 31 is referred to as an "ohmic contact interface". The ohmic contact interface 35 is aligned with the emitter electrode 32 when viewed in plan. The edge of the ohmic contact interface 35 is disposed slightly inward of the edge of the emitter layer 31 and at a substantially constant interval from the edge of the emitter layer 31.

A base electrode 52 is disposed on the base layer 51, and the base electrode 52 and the base layer 51 are in ohmic contact. In fig. 1, the base electrode 52 is hatched. The base electrode 52 includes 2 base electrode main portions 52A, a base electrode pad portion 52B. The 2 base electrode main portions 52A are respectively arranged on both sides in the width direction of the emitter layer 31 in a plan view, and extend in the longitudinal direction of the emitter layer 31. The base electrode pad portion 52B connects 2 base electrode main portions 52A to each other outside one end portion (left end in fig. 1) in the longitudinal direction of the emitter layer 31. The base electrode 52 composed of the base electrode main portion 52A and the base electrode pad portion 52B surrounds the emitter layer 31 in a U-shape.

Collector electrodes 42 are disposed inside subcollector layer 40 and on both sides of collector layer 41. The collector electrodes 42 each have a planar shape that is long in a direction parallel to the longitudinal direction of the emitter layer 31. The collector electrode 42 is connected to the collector layer 41 via the sub-collector layer 40.

An insulating film is disposed on emitter electrode 32, collector electrode 42, and base electrode 52. Emitter wiring 34, collector wiring 44, and base wiring 54 are disposed on the insulating film, and are overlapped with emitter electrode 32, collector electrode 42, and base electrode pad portion 52B, respectively, in a plan view. Emitter wiring 34 is connected to emitter electrode 32 through contact hole 33 provided in the insulating film. The collector wiring 44 is connected to the collector electrode 42 through a contact hole 43 provided in the insulating film. The base wiring 54 is connected to the base electrode pad portion 52B through the contact hole 53 provided in the insulating film.

The emitter contact hole 33 is disposed inside the emitter electrode 32 in a plan view, and has a planar shape that is long in the longitudinal direction of the emitter layer 31. The collector contact hole 43 is disposed inside the collector electrode 42 in a plan view, and has a planar shape that is long in the longitudinal direction of the collector electrode 42. The base contact hole 53 is disposed at a crossing position where an extension line extending the emitter layer 31 in the longitudinal direction crosses the base electrode pad portion 52B.

Emitter wiring 34 is led out from the position where contact hole 33 is arranged in a direction parallel to the longitudinal direction of emitter layer 31. Base wiring 54 is led out in a direction opposite to the direction in which emitter wiring 34 is led out from the position where contact hole 53 is arranged. There may be a case where a layer 2 wiring is also arranged on emitter wiring 34, collector wiring 44, and base wiring 54.

In a plan view, emitter layer 31, emitter electrode 32, and contact hole 33 are arranged symmetrically in both the longitudinal direction and the width direction. In addition, the distance between the edge of the emitter layer 31 and the edge of the emitter electrode 32 is substantially constant regardless of the longitudinal direction or the width direction. The interval between the edge of the emitter layer 31 and the edge of the contact hole 33 is substantially constant regardless of the longitudinal direction or the width direction. Here, "substantially" constant means that the variation in size is within a range of process variation, for example, the width of the variation is 0.5 μm or less.

In general, in order to ensure a large area for current to flow in the emitter layer 31, the area of the emitter electrode 32 is designed to be as large as possible. For example, the interval between the outer periphery of the emitter layer 31 and the outer periphery of the emitter electrode 32 is designed to be 1 μm or less.

When a monolithic microwave integrated circuit device (MMIC) incorporating a power amplifier is configured, a plurality of HBTs shown in fig. 1 are arranged on 1 semiconductor substrate. The plurality of HBTs are electrically connected directly via the emitter wiring 34, the collector wiring 44, the base wiring 54, and the layer 2 wiring thereon, or indirectly via an element such as a resistor. Thus, a power amplifier having a power stage and a driver stage is constructed.

Fig. 2 is a graph showing the measurement results of the SOA line of the HBT. The horizontal axis represents collector voltage Vce in units "V" and the vertical axis represents collector voltage Vce in units "mA/cm²"denotes the collector current density Jc. The circle symbols and the triangle symbols in the graph represent SOA lines based on actual measurements of samples of different emitter sizes, respectively. The circle symbols and the solid lines in the graph of fig. 2 indicate the actual measurement results of the sample having emitter electrode 32 with a width of 3 μm and a length of 40 μm, and the triangle symbols and the broken lines indicate the actual measurement results of the sample having emitter electrode 32 with a width of 3 μm and a length of 20 μm. The region on the lower voltage side than the SOA line corresponds to the SOA.

It can be seen that if the collector voltage Vce increases from 6V to 6.5V, the SOA line discontinuously sharply decreases. The collector voltage Vce when the SOA line discontinuously decreases corresponds to the transition voltage Vt.

In the reference example shown in fig. 1 and 2, the number of emitter electrodes 32 is 1 and the number of base electrode main portions 52A is 2, but even in an HBT in which the number of emitter electrodes 32 and the number of base electrode main portions 52A are combined in another manner, it is confirmed that the discontinuity of the SOA line is reduced. For example, in HBTs in which both the emitter electrode 32 and the base electrode main portion 52A are 1, in HBTs in which the emitter electrode 32 is 2 and the base electrode main portion 52A is 3, and in HBTs in which the emitter electrode 32 is 3 and the base electrode main portion 52A is 4, the discontinuity of the SOA line is also confirmed to be reduced.

Fig. 3 is a graph showing the actual measurement result of the collector current-base voltage characteristic (Ic-Vb characteristic). The horizontal axis represents the base voltage Vb in arbitrary units, and the vertical axis represents the collector current Ic in arbitrary units. In the measurement, the base voltage Vb and the collector current Ic are measured while sweeping the base current Ib with the current source. The measurement was performed at a plurality of voltages of collector voltage Vce — V1, V2, V3, V4, and V5. The voltage V1-V5 has a magnitude relationship of V1 < V2 < V3 < V4 < V5.

In a range where collector current Ic is small, collector current Ic monotonically increases with an increase in base voltage Vb, and the inclination of collector current Ic with respect to base voltage Vb gradually becomes large. Further, when the collector current Ic becomes large, the slope of the incoming collector current Ic with respect to the base voltage Vb becomes an infinite sharp return point SB. When collector current Ic is increased beyond abrupt return point SB, the slope of collector current Ic with respect to base voltage Vb becomes negative, and base voltage Vb decreases as collector current Ic increases.

When collector voltage Vce is V4 and V5, kink K occurs in which collector current Ic discontinuously decreases after collector current Ic passes through sharp return point SB. When the collector voltage Vce is V1, V2, V3 lower than V4, V5, kink K does not occur. The minimum collector voltage Vce at which kink K occurs corresponds to the transition voltage Vt (fig. 2). Here, the kink K is a characteristic region in which the base voltage Vb tends to decrease and the collector current Ic tends to increase in the Ic-Vb characteristic, and the base voltage Vb temporarily increases or the collector current Ic temporarily decreases (see fig. 3).

Next, the reason why the kink K occurs in the region beyond the sharp return point SB of the collector current-base voltage characteristic will be described.

It is assumed that the kink K occurs due to thermal or electrical asymmetry that the HBT has. Inside emitter layer 31 (fig. 1), emitter electrode 32 and contact hole 33 are arranged symmetrically. However, the collector electrode 42, the base electrode 52, various wirings, and the like, which are asymmetrically arranged with respect to the emitter layer 31, are arranged around the emitter layer 31. In addition, when the HBTs constituting the power stage and the power amplifier of the driver stage, and the arrangement of the lead-out wiring, circuit elements, via holes, and the like around the HBTs are viewed in overhead, there is thermal and electrical asymmetry factor with respect to the 1 emitter layer 31 concerned.

When the collector current increases beyond the snap-back point SB, the region in which the emitter current Ie mainly flows is displaced in the longitudinal direction of the emitter layer 31 (fig. 1) due to these asymmetry factors. It can be considered that the kink K (fig. 3) occurs due to the displacement of the region where the emitter current Ie mainly flows. In the embodiment described below, the position of the region where the emitter current Ie mainly flows is less susceptible to the influence of the asymmetry factor of the periphery of the emitter layer 31.