阅读说明：本技术 一种逻辑电路及可穿戴电子设备 (Logic circuit and wearable electronic equipment ) 是由 杨家奇 郭俊涛 黄正乙 于 2018-06-04 设计创作，主要内容包括：一种逻辑电路及可穿戴电子设备,所述逻辑电路包括多个功能模块,所述逻辑电路对于不包含关键路径的功能模块,其电源端接收第一电源信号；对于包含关键路径的功能模块,其电源端接收第二电源信号；其中,所述第一电源信号的电压值小于所述第二电源信号的电压值。通过本发明提供的技术方案,可以尽可能降低逻辑电路的电源电压,减小逻辑电路的功率消耗。(A logic circuit and wearable electronic equipment, the logic circuit includes a plurality of functional modules, the logic circuit for not including the functional module of the critical path, its power supply end receives the first power signal; for the functional module comprising the critical path, a power supply end of the functional module receives a second power supply signal; wherein a voltage value of the first power supply signal is less than a voltage value of the second power supply signal. By the technical scheme provided by the invention, the power supply voltage of the logic circuit can be reduced as much as possible, and the power consumption of the logic circuit is reduced.)

1. A logic circuit comprising a plurality of functional blocks, characterized in that,

for a functional module which does not comprise a critical path, a power supply end of the functional module receives a first power supply signal;

for the functional module comprising the critical path, a power supply end of the functional module receives a second power supply signal;

wherein a voltage value of the first power supply signal is less than a voltage value of the second power supply signal.

2. The logic circuit of claim 1, wherein each functional block comprises an input stage flip-flop, an output stage flip-flop, and a combinational circuit connected between the input stage flip-flop and the output stage flip-flop,

for a non-critical path module, a clock input end of an input stage trigger receives a first clock signal, and the non-critical path module is a functional module which does not comprise a critical path;

for a critical path module, a clock input end of an input stage trigger receives a second clock signal, and the critical path module is a functional module comprising a critical path;

wherein a phase of the second clock signal is earlier than a phase of the first clock signal.

3. The logic circuit of claim 2, wherein the critical path module is divided into a plurality of different delay levels, and the critical paths in the functional modules of different delay levels have different delays, and wherein the clock inputs of the input stage flip-flops of the functional modules of different delay levels receive the second clock signals of different phases.

4. The logic circuit of claim 3, wherein the larger the critical path delay of the functional module for different delay levels, the earlier the phase of the second clock signal received at the clock input of the input stage flip-flop of the functional module.

5. The logic circuit of claim 2, wherein the flip-flop is a D flip-flop.

6. A logic circuit according to any one of claims 2 to 5, wherein the combinatorial circuit is a circuit formed by combining one or more logic gates.

7. The logic circuit according to any one of claims 2 to 5, wherein a voltage difference between the first power supply signal and the second power supply signal is less than a threshold voltage, the threshold voltage being a threshold voltage of a transistor in the combinational circuit.

8. The logic circuit of claim 1, wherein the voltage value of the second power signal is equal to a lowest voltage in a preset design specification, and the voltage value of the first power signal is smaller than the lowest voltage in the preset design specification.

9. A wearable electronic device, characterized in that it comprises a logic circuit according to any one of claims 1 to 8.

Technical Field

The invention relates to the technical field of electronics, in particular to a logic circuit and wearable electronic equipment.

Background

In recent years, with the rapid development of the technology of the Internet of Things (IOT for short)And by extension, IOT products are more and more abundant in types. Typical IOT products include smart home devices and internet-of-things smart wearable devices (also referred to as wearable electronic devices). As IOT technology evolves, low power designs have become increasingly important. For a digital system logic circuit, the power consumption formula is P ═ CV²Wherein P represents consumed power, C represents load capacitance of the digital system, V represents power supply voltage, and f represents system operating frequency. According to the power consumption formula, the reduction of the power consumption can be started from three factors of capacitance, voltage and frequency, wherein the consumed power is in direct proportion to the square of the power supply voltage, and the power supply voltage has the largest influence on the power consumption of the digital system logic circuit. Moreover, the load capacitance and operating frequency are generally uncontrollable and constant values for the designer. Therefore, reducing the power supply voltage is a key to improving the power consumption of digital systems.

However, as the power supply voltage is continuously reduced, the delay of the logic circuit is continuously increased, which may cause the logic circuit including the Critical Path to fail to operate at the system operating frequency, that is, the power supply voltage may not be continuously reduced to ensure that the logic circuit meets the delay requirement. In the prior art, a document "Reducing Power, Leakage, and area of Standard-Cell ASICs Using Threshold Logic Flip-Flops" proposes to use an analog circuit to replace a part of a digital circuit, for example, to use the analog circuit to replace a conventional digital Logic decision circuit, and to combine with a back-end D Flip-Flop (DFlip-Flop, DFF for short) to form an analog-digital hybrid circuit, so as to achieve the effect of Reducing Power consumption.

However, if the analog-digital hybrid circuit is not used, the power consumption design of the logic circuit of the existing digital system is still to be strengthened.

Disclosure of Invention

The technical problem solved by the invention is how to reduce the power supply voltage of the logic circuit as much as possible so as to reduce the power consumption of the logic circuit.

In order to solve the above technical problem, an embodiment of the present invention provides a logic circuit, including a plurality of functional modules, where for a functional module that does not include a critical path, a power supply end of the logic circuit receives a first power supply signal; for the functional module comprising the critical path, a power supply end of the functional module receives a second power supply signal; wherein a voltage value of the first power supply signal is less than a voltage value of the second power supply signal.

Optionally, each functional module includes an input stage flip-flop, an output stage flip-flop, and a combinational circuit connected between the input stage flip-flop and the output stage flip-flop, wherein, for a non-critical path module, a clock input terminal of the input stage flip-flop receives a first clock signal, and the non-critical path module is a functional module that does not include a critical path; for a critical path module, a clock input end of an input stage trigger receives a second clock signal, and the critical path module is a functional module comprising a critical path; wherein a phase of the second clock signal is earlier than a phase of the first clock signal.

Optionally, the critical path module is divided into a plurality of different delay levels, and the critical paths in the functional modules with different delay levels have different delays, where for the functional modules with different delay levels, the clock input terminals of the input stage flip-flops receive second clock signals with different phases.

Optionally, for functional modules with different delay levels, the larger the delay of the critical path is, the earlier the phase of the second clock signal received by the clock input terminal of the input stage flip-flop of the functional module is.

Optionally, the flip-flop is a D flip-flop.

Optionally, the combination circuit is a circuit formed by combining one or more logic gates.

Optionally, a voltage difference between the first power signal and the second power signal is smaller than a threshold voltage, where the threshold voltage is a threshold voltage of a transistor in the combinational circuit.

Optionally, a voltage value of the second power signal is equal to a lowest voltage in a preset design specification, and a voltage value of the first power signal is smaller than the lowest voltage in the preset design specification.

To solve the above technical problem, an embodiment of the present invention provides a wearable electronic device, including the above logic circuit.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the embodiment of the invention provides a logic circuit, which comprises a plurality of functional modules, wherein for the functional modules which do not comprise a critical path, a power supply end of the logic circuit receives a first power supply signal; for the functional module comprising the critical path, a power supply end of the functional module receives a second power supply signal; wherein a voltage value of the first power supply signal is less than a voltage value of the second power supply signal. Compared with the existing logic circuit, the logic circuit provided by the embodiment of the invention can respectively provide different power supply voltages for the functional module not comprising the critical path and the functional module comprising the critical path, and compared with the critical path module and the power supply voltage of the non-critical path module, the power supply voltage of the first power supply signal with a lower power supply voltage value can be adopted, so that the power consumption of the logic circuit is reduced as much as possible on the premise of ensuring the normal operation of the functions of the functional modules.

Further, each functional module comprises an input stage trigger, an output stage trigger and a combination circuit connected between the input stage trigger and the output stage trigger, wherein for a non-critical path module, a clock input end of the input stage trigger receives a first clock signal, and the non-critical path module is a functional module without a critical path; for a critical path module, a clock input end of an input stage trigger receives a second clock signal, and the critical path module is a functional module comprising a critical path; wherein a phase of the second clock signal is earlier than a phase of the first clock signal. The critical path module and the non-critical path module adopt clock signals with different phases, so that the critical path module can start to work in advance and can tolerate delay to a greater extent, thereby working based on lower power supply voltage, further reducing voltage and saving power consumption.

Further, a voltage difference between the first power signal and the second power signal is smaller than a threshold voltage, the threshold voltage is a threshold voltage of a transistor in the combinational circuit, and high-low level conversion can be completed inside the trigger without adopting a voltage converter.

Drawings

Fig. 1 is a schematic block diagram of a conventional logic circuit;

FIG. 2 is a schematic block diagram of a logic circuit according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of a further logic circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a delay waveform of a logic circuit according to an embodiment of the present invention;

FIG. 5A is a schematic block diagram of another conventional logic circuit;

FIG. 5B is a schematic block diagram of another logic circuit of an embodiment of the present invention;

fig. 6 is a power consumption comparison diagram of the logic circuit shown in fig. 5A and 5B.

Detailed Description

As mentioned in the background, in order to ensure that the critical path of the logic circuit meets the delay requirement, it is difficult to continue to decrease the power supply voltage based on the lowest voltage of the critical path.

The inventor of the present application has found that a logic circuit generally includes several functional blocks (e.g., functional block a, functional block B, functional block C, functional block D, functional block E, functional blocks F, … … shown in the left diagram of fig. 1), each of which generally includes an input stage DFF, a combinational circuit formed by logic gates, and an output stage DFF (e.g., shown in the right diagram of fig. 1), and a single clock signal is used as an input clock signal and a single power signal is used as an input signal of a power supply voltage. In order to take account of the time delay requirement of the critical path, the logic circuit has difficulty in continuously reducing the voltage on the basis of the lowest voltage of the critical path.

The embodiment of the invention provides a logic circuit, which comprises a plurality of functional modules, wherein for the functional modules which do not comprise a critical path, a power supply end of the logic circuit receives a first power supply signal; for the functional module comprising the critical path, a power supply end of the functional module receives a second power supply signal; wherein a voltage value of the first power supply signal is less than a voltage value of the second power supply signal. Compared with the existing logic circuit, the logic circuit provided by the embodiment of the invention can respectively provide different power supply voltages for the functional module not comprising the critical path and the functional module comprising the critical path, and compared with the critical path module, the non-critical path module can adopt the power supply voltage of the first power supply signal with lower power supply voltage value, so that the power consumption is lower, and the power consumption of the logic circuit is reduced as much as possible on the premise of ensuring the normal operation of the functions of the functional modules.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic block diagram of a logic circuit according to an embodiment of the present invention. Referring to fig. 2, the logic circuit 200 may include a plurality of functional blocks. Some of the functional modules are functional modules including a critical path, such as functional module D; some of the functional modules are functional modules that do not include a critical path, such as functional module a, functional module B, functional module C, functional module E, and functional modules F and … …. In a typical logic circuit, the ratio of functional blocks that do not include a critical path to functional blocks that include a critical path is 4: 1. The logic circuit 200 has two or more supply voltages, unlike a conventional single supply voltage. For each functional module, two power supplies can supply power, that is, two paths of power supply signals are received. However, in order to reduce power consumption, if the power supply with lower voltage can meet the voltage requirement of circuit operation, the functional module can be powered by receiving the power supply signal with lower voltage.

Specifically, for a functional module (other functional module except functional module D) that does not include a critical path, its power supply terminal receives a first power supply signal; for the functional module containing the critical path (functional module D), its power supply terminal receives the second power supply signal. Wherein the voltage VDD1 of the first power signal is less than the voltage VDD2 of the second power signal, i.e., voltage VDD1< voltage VDD 2. The logic circuit 200 receives two paths of power signals, and can adopt a voltage VDD1 with a lower voltage value to supply power to functional modules without a critical path; the functional module including the critical path is powered by the voltage VDD2 with a higher voltage value. Functional modules that do not include critical paths may break through the delay requirements of the critical paths, thereby achieving lower power consumption.

As a preferred embodiment, in conjunction with fig. 2 and 3, one functional block 30 in the logic circuit 200 may include an input stage flip-flop 301, an output stage flip-flop 302, and a combining circuit 303 connected between the input stage flip-flop and the output stage flip-flop. The voltage VDD2 provides a power supply voltage for the combinational circuit 303 and its input part (the second half of the input stage flip-flop 301) and output part (the first half of the output stage flip-flop 302), and the voltage VDD1 provides a power supply voltage for the rest parts, i.e., the first half of the input stage flip-flop 301 and the second half of the output stage flip-flop 302.

The input stage flip-flop 301 and the output stage flip-flop 302 may be D flip-flops, or may be other appropriate types of flip-flops. The combination circuit 303 may be a circuit formed by combining one or more logic gates. The combinational circuit 303 is typically composed of logic gates such as and gates, or gates, not gates, exclusive or gates, nand gates, and nor gates, which are referred to as passgates, and may constitute any other gates.

In the combinational circuit 303, all logic gates have a propagation delay time. The critical path is the longest path from signal input to output in the combinatorial circuit, and the delay of this path determines the shortest period that the digital system can reach and also determines the highest frequency that the digital system can reach.

Referring to fig. 3, as a non-limiting example, for a non-critical path module, i.e. a functional module not including a critical path, the clock input terminal of the input stage flip-flop 301 may receive a first clock signal CLK1, and the first clock signal CLK1 may be a clock signal determined according to a predetermined design specification. For a critical path module, i.e. a functional module comprising a critical path, the clock input of the input stage flip-flop 301 may receive a second clock signal (not shown). Thereafter, the clock input terminal of the output stage flip-flop 302 may receive an inverted clock signal of the first clock signal CLK1 to achieve signal synchronization.