阅读说明：本技术 基于随机计算与余数系统相结合的fir滤波系统 (FIR filtering system based on combination of random calculation and remainder system ) 是由 卢有亮 赵成 滕云龙 王浩 张桓源 元硕成 卢鹏宇 罗建平 于 2019-09-25 设计创作，主要内容包括：本发明公开一种基于随机计算与余数系统相结合的FIR滤波系统,该FIR滤波系统包括余数系统前向转换单元、随机计算前向转换单元、运算单元、随机计算后向转换单元及余数系统后向转换单元。本发明将输入的二进制数通过前向转换单元转换为余数表示,并再通过随机计算前向转换单元将对应通道的数据转换成概率域比特流,然后将原本的乘法和加法操作使用与门和随机计算后向转换单元替换,最后将最终的结果通过余数系统后向转换单元转换回二进制输出,在大量减少构造传统的滤波器所需要的资源的同时减少了因随机计算所增加的时延。(The invention discloses an FIR filtering system based on the combination of random calculation and a remainder system. The invention converts the input binary number into remainder representation through a forward conversion unit, converts the data of the corresponding channel into probability domain bit stream through a random calculation forward conversion unit, then replaces the original multiplication and addition operations by an AND gate and a random calculation backward conversion unit, and finally converts the final result back to binary output through a remainder system backward conversion unit, thereby greatly reducing the resources required by constructing the traditional filter and simultaneously reducing the time delay increased by random calculation.)

1. An FIR filtering system based on random computation combined with a residue number system, comprising:

a remainder system forward conversion unit, a random calculation forward conversion unit, an arithmetic unit, a random calculation backward conversion unit and a remainder system backward conversion unit;

the remainder system forward conversion unit is used for generating a remainder base { m }according to the generated remainder base₁，m₂，m₃，...，m_i，...，m_LConverting the input binary number X to obtain a conversion result { X }₁，x₂，x₃，...，x_i，...，x_L}；

The random calculation forward conversion unit is used for converting the conversion result { x ] of the remainder system forward conversion unit₁，x₂，x₃，...，x_i，...，x_LCarrying out secondary conversion to obtain a secondary conversion result { s }₁，s₂，s₃，...，s_i，...，s_LIn which s is_iIs formed by x_iConverting the obtained probability domain bit stream;

the operation unit is used for calling AND gate operation under each channel;

the random calculation backward conversion unit is used for converting the corresponding channel random calculation result into a remainder system and simultaneously performing accumulation and modulus operation;

and the remainder system backward conversion unit is used for converting the number under the remainder system into a binary representation to obtain a filtering result.

2. The FIR filtering system based on random computation combined with the remainder system as claimed in claim 1, wherein the remainder system forward conversion unit generates the remainder base as follows:

and constructing a finite impulse response filter system, and selecting the residue number base according to the digit number of the output data of the filter system to ensure that the digit number of the output data is in the dynamic range of the residue number base.

3. The FIR filtering system based on random computation combined with remainder system as claimed in claim 2, wherein when the output data is 32 bits, the remainder base is {2 }¹¹-1，2¹¹，2¹¹+1}。

4. The FIR filtering system based on random computation combined with remainder system as claimed in claim 3, wherein when the output data is 32 bits, the length of the corresponding random computation bit stream is {2047, 2048, 2049}, and the remainder is converted into a random computation bit stream of the corresponding length.

5. The FIR filtering system based on the combination of random computation and remainder system as claimed in claim 4, wherein said random computation forward conversion unit performs a second conversion specifically as follows:

conversion result { x for the remainder system forward conversion unit₁，x₂，x₃，...，x_i，...，x_LData x in (c) }_iPerforming secondary conversion to obtain a secondary conversion result { s₁，s₂，s₃，...，s_i，...，s_LAnd (c) in the secondary conversion result, the data is binary number X and passes through the residue base m_iTo obtain x_iThen by x_iConversion into a probability domain bitstream s_i。

6. The FIR filtering system based on the combination of random calculation and remainder system as claimed in claim 5, wherein said operation unit uses AND gate and said random calculation backward conversion unit to perform multiplication and addition operation under each channel to obtain operation result.

7. The FIR filtering system based on the combination of random calculation and remainder system as claimed in claim 6, wherein said remainder system backward conversion unit converts the operation result into binary output, and preferentially converts the operation result after the second conversion to obtain the filtering result.

Technical Field

The invention belongs to the technical field of digital signal processing, and particularly relates to an FIR filtering system based on combination of random calculation and a remainder system.

Background

A Finite Impulse Response (FIR) filter is one of the most commonly used and important filters in digital signal processing systems because it can be designed to have an arbitrary amplitude-frequency characteristic while ensuring an accurate and strict linear phase characteristic, and its unit sampling Response is Finite and is a stable system. In practical use, the main goal of the FIR digital filter is not only to obtain filter coefficients satisfying performance criteria, but also to reduce hardware resources and energy consumption as much as possible.

The Remainder Number System (RNS) is an unweighted operation, and each modular operation has natural independence and parallelism, and no carry exists between the modular operations. In the residue number system, a large integer X passes through a set of pairwise coprime residue numbers m₁,m₂,m₃…m_LIs divided into a set of small integers of independent parallel operation x₁,X₂,x₃…x_LIn addition and multiplication operations, no carry propagation exists among all parallel modules, so that the time delay of a key path is reduced, and the method is widely applied and researched in digital signal processing with a large number of multiplication and addition operations.

Stochastic Computing (SC) is a weightless, low-cost, noise-immune approximation Computing method in which a number is converted into a probability domain bit stream for computation, and if the generated probability domain bit stream is a centrally distributed sequence and a uniformly distributed sequence, then an accurate multiply-add result can be obtained by a simple and or gate. The random calculation can greatly reduce resource consumption, but also brings huge delay and reduces the operation speed. The random operation is combined with a remainder System (SC-RNS), the parallelism of the remainder System and the low overhead of the random computation are combined, the resource consumption is greatly reduced, and the delay increased by the random computation is reduced.

Disclosure of Invention

The invention aims to provide an FIR filter system based on random computation and remainder system combination (SC-RNS) so as to reduce the resources required for constructing the traditional filter and simultaneously reduce the time delay increased by the random computation.

In order to achieve the above object, the present invention provides an FIR filtering system based on random computation and remainder system combination, comprising:

a remainder system forward conversion unit, a random calculation forward conversion unit, an arithmetic unit, a random calculation backward conversion unit and a remainder system backward conversion unit;

the remainder system forward conversion unit is used for generating a remainder base { m }according to the generated remainder base₁,m₂,m₃,…,m_i,…,m_LConverting the input binary number X to obtain a conversion result { X }₁,x₂,x₃,…,x_i,…,x_L}；

The random calculation forward conversion unit is used for converting the conversion result { x ] of the remainder system forward conversion unit₁,x₂,x₃,…,x_i,…,x_LCarrying out secondary conversion to obtain a secondary conversion result { s }₁,s₂,s₃,…,s_i,…,s_LIn which s is_iIs formed by x_iConverting the obtained probability domain bit stream;

the operation unit is used for calling AND gate operation under each channel;

the random calculation backward conversion unit is used for converting the corresponding channel random calculation result into a remainder system and simultaneously performing accumulation and modulus operation;

and the remainder system backward conversion unit is used for converting the number under the remainder system into a binary representation to obtain a filtering result.

Further, the residue system forward conversion unit generates a residue base specifically as follows:

and constructing a finite impulse response filter system, and selecting the residue number base according to the digit number of the output data of the filter system to ensure that the digit number of the output data is in the dynamic range of the residue number base.

Further, when the output data is 32 bits, the residue basis is {2 }¹¹-1,2¹¹,2¹¹+1}。

Further, when the output data is 32 bits, the length of the corresponding random computation bit stream is {2047, 2048, 2049}, and the remainder is converted into a random computation bit stream of the corresponding length.

Further, the performing of the second conversion by the random calculation forward conversion unit specifically includes:

conversion result { x for the remainder system forward conversion unit₁,x₂,x₃,…,x_i,…,x_LData x in (c) }_iPerforming secondary conversion to obtain a secondary conversion result { s₁,s₂,s₃,…,s_i,…,s_LAnd (c) in the secondary conversion result, the data is binary number X and passes through the residue base m_iTo obtain x_iThen by x_iConversion into a probability domain bitstream s_i。

Furthermore, the arithmetic unit uses an AND gate and the random calculation under each channel and then carries out multiplication and addition operation on the conversion unit to obtain an operation result.

Furthermore, the residue number system backward conversion unit converts the operation result into binary output, and preferentially converts the operation result after the secondary conversion to obtain a filtering result.

The invention has the beneficial effects that: the invention converts the input binary number into remainder representation through a forward conversion unit, converts the number represented by the remainder into bit stream representation of random calculation again, replaces the original multiplication and addition operations by using a simple AND gate, and finally converts the final result back into binary output through a backward conversion unit, thereby greatly reducing the resources required by constructing the traditional filter and simultaneously reducing the increased time delay.

Drawings

FIG. 1 is a block diagram of an FIR filtering system based on random calculation combined with a remainder system according to the present invention;

in the figure: 110-a forward conversion unit; 120-a secondary conversion unit; 130-an arithmetic unit; 140-probability calculation backward conversion unit, 150-remainder system backward conversion unit;

fig. 2 is a diagram of a forward conversion unit for converting a binary number X into a remainder domain and then into a probability domain bit stream according to the present invention.

FIG. 3 is a diagram of a random calculation backward conversion unit according to the present invention;

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The main solution of the embodiment of the invention is as follows:

as shown in fig. 1, an FIR filtering system based on random computation combined with a remainder system includes:

a remainder system (RNS) forward conversion unit 110, a random computation (SC) forward conversion unit 120, an operation unit 130, a random computation (SC) backward conversion unit 140, and a remainder system (RNS) backward conversion unit 150;

the input of the present invention is a binary number X, which is processed by the remainder system forward conversion unit 110.

Remainder base m in remainder system forward conversion unit 110₁,m₂,m₃,…,m_i,…,m_LConverting binary number X into remainder X₁,x₂,x₃,…,x_i,…,x_LDenotes that the video stream is converted into a corresponding bit stream after passing through the random-computation forward conversion unit 120.

The residue system forward conversion unit generates a residue base specifically as follows:

and constructing a required FIR filter by using FDATOOL of MATLAB to generate a corresponding Verilog code, and selecting a residue basis according to the digit of output data of the filter in the code to ensure that the product of the residue basis is larger than the value of the maximum bit width, namely the digit of the output data is in the dynamic range of the residue basis.

In the preferred embodiment of this embodiment, a FIR filter with 32 bits of output data is used, and the residue basis is {2 }¹¹-1,2¹¹,2¹¹+1, which can represent a dynamic range of The corresponding randomly calculated bit stream is of length {2047, 2048, 2049}, and the remainder is converted into a randomly calculated bit stream of corresponding length. The binary number X after residue base conversion is { X₁,x₂,x₃,x₄,x₅}。

The random calculation forward conversion unit 120 converts the system forward conversion unit's conversion result { x) according to the remainder₁,x₂,x₃,…,x_i,…,x_LIth item data x in_iPerforming secondary conversion to obtain a secondary conversion result { s₁,s₂,s₃,…,s_i,…,s_LAnd f, wherein the ith item of data in the secondary conversion result is a remainder base m of binary number X passing through the ith channel_iTo obtain x_iThen by x_iConversion into a probability domain bitstream s_iAs shown in fig. 2.

The operation unit 130 obtains the result of the multiplication operation by using and gates in the respective channels.

In the preferred embodiment of this embodiment, the operation unit 130 performs multiplication and addition operations on each channel by using the and gate and the post-conversion unit 140 for random calculation, so as to obtain an operation result.

The random calculation backward conversion unit 140 converts the corresponding channel random calculation result to a remainder system, and performs the accumulation and modulo operations at the same time, as shown in fig. 3.

The remainder system back-conversion unit 150 converts the numbers under the remainder system to a binary representation, resulting in the final result of the operation.

In a preferred embodiment of this embodiment, the residue number system backward conversion unit converts the operation result into a binary output, and preferentially converts the operation result after the second conversion to obtain a filtering result.

The invention uses accumulators and comparators to implement a forward conversion of random calculations, modulo-2¹¹-1 and die 2¹¹Because the bit width of the adder and the multiplier is 11 bits, 11-bit counters are adopted. And a die 2¹¹The bit width of +1 is 12 bits, so modulo 2¹²The conversion to +1 uses a 12-bit counter for random calculation. Multiplication operation is realized by the operation unit 130 through an AND gate under each residue channel, and addition operation, namely corresponding filtering operation, is realized by the backward conversion unit through random calculation.

The invention converts the bit stream generated at last by random computation into a remainder system, and then converts the final result back to a binary system to obtain the final filtering result, namely, the random computation backward conversion unit 140 converts the random computation result into a representation under the remainder system, and the backward conversion unit 150 converts the number under the remainder system into a binary representation to obtain the filtering result.

In summary, the invention first uses the Matlab fdato ool tool box to design the required FIR filter and generate the corresponding Verilog code, and selects the residue number base according to the number of bits of the output data in the generated code, so that the output number is in the dynamic range of the residue number base; then according to the selected residue basis, determining the length of the bit stream randomly calculated by each channel; then, according to the codes, the construction of other units is completed, including a remainder system forward conversion unit 110, a random calculation forward conversion unit 120, a random calculation backward conversion unit 140 and a remainder system backward conversion unit 150; the binary number X enters the FIR filtering system constructed by the present invention, is converted into remainder representation by the remainder system forward conversion unit 110, the remainder representation is converted into a bit stream by the random computation forward conversion unit 120, then the original multiplication and addition operations are replaced by the and gate and random computation backward conversion unit 140, and finally the final result is converted back to binary output by the remainder system backward conversion unit 150 to obtain the filtering result.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.