阅读说明：本技术 触发器电路 (Flip-flop circuit ) 是由 徐薪承 曹太和 林柏青 于 2018-06-19 设计创作，主要内容包括：一种触发器电路,包含:一输入端、一输出端、一控制电路以及一逻辑电路。该控制电路耦接至该输入端以及该输出端。该控制电路自该输入端接收一输入电压并自该输出端接收一输出电压,且该控制电路至少根据该输入电压以及该输出电压来产生多个参考电压。该逻辑电路耦接至该控制电路以及该输出端。当该输入电压从一第一电压值转换为一第二电压值时,该控制电路通过该多个参考电压来控制该逻辑电路以将该输出电压从该第二电压值转换为该第一电压值。(A flip-flop circuit includes an input terminal, an output terminal, a control circuit, and a logic circuit. The control circuit is coupled to the input terminal and the output terminal. The control circuit receives an input voltage from the input terminal and an output voltage from the output terminal, and the control circuit generates a plurality of reference voltages at least according to the input voltage and the output voltage. The logic circuit is coupled to the control circuit and the output terminal. When the input voltage is converted from a first voltage value to a second voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from the second voltage value to the first voltage value.)

1. A flip-flop circuit, comprising:

an input terminal and an output terminal;

a control circuit coupled to the input terminal and the output terminal, wherein the control circuit receives an input voltage from the input terminal and an output voltage from the output terminal, and the control circuit generates a plurality of reference voltages according to the input voltage and the output voltage;

and the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from a second voltage value to the first voltage value when the input voltage is converted from the first voltage value to the second voltage value.

2. The flip-flop circuit of claim 1, wherein the voltage values of the plurality of reference voltages are an arithmetic series, the first voltage value is one of a maximum voltage and a minimum voltage of the plurality of reference voltages, and the second voltage value is the other of the maximum voltage and the minimum voltage of the plurality of reference voltages.

3. The flip-flop circuit of claim 2, wherein the logic circuit comprises a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

4. The flip-flop circuit of claim 3, wherein the control circuit transmits a specific reference voltage to a gate terminal and a source terminal of a specific one of the plurality of MOSFETs when a variation of the input voltage is smaller than a predetermined threshold.

5. The flip-flop circuit of claim 4, wherein the control circuit stops transmitting the specific reference voltage to the source terminal of the specific MOSFET when the change of the input voltage is greater than or equal to the predetermined threshold.

6. The flip-flop circuit of claim 1, wherein the control circuit comprises:

a comparator for comparing the input voltage with a specific reference voltage and outputting the higher of the input voltage and the specific reference voltage as one of the plurality of reference voltages.

7. The flip-flop circuit of claim 1, wherein the control circuit comprises:

a comparator for comparing the output voltage with a specific reference voltage and outputting the higher of the output voltage and the specific reference voltage as one of the plurality of reference voltages.

8. The flip-flop circuit of claim 1, wherein the control circuit comprises:

a comparator for comparing the input voltage with a specific reference voltage and outputting the lower of the input voltage and the specific reference voltage as one of the reference voltages.

9. The flip-flop circuit of claim 1, wherein the control circuit comprises:

and the comparator is used for comparing the output voltage with a specific reference voltage and outputting the lower one of the output voltage and the specific reference voltage as one of the reference voltages.

10. The flip-flop circuit of claim 3, wherein the control circuit comprises:

and the switching circuit is used for judging whether to output a specific reference voltage to a source terminal of a specific metal oxide semiconductor field effect transistor in the plurality of metal oxide semiconductor field effect transistors or not according to the output voltage.

Technical Field

The present invention relates to an electronic circuit, and more particularly, to a flip-flop circuit with protection measures.

Background

With the rapid development of Complementary Metal-Oxide-Semiconductor (CMOS) technology, the size of transistors is continuously reduced to reduce the chip area, thereby increasing the operating speed and saving power consumption. However, as transistor dimensions continue to shrink, so does the gate oxide and transistor channel, and the maximum allowable cross-voltage across any transistor electrode (gate, drain, source, and base). If the voltage difference between any two terminals of a transistor is greater than the nominal voltage, the transistor will be damaged. The voltage rating of the advanced CMOS process is getting lower and lower, so the conventional CMOS Schmitt trigger (Schmitt trigger) circuit faces the problem that the power supply voltage is higher than the voltage rating, which causes the transistor to be damaged.

Disclosure of Invention

It is an object of the present invention to provide a flip-flop circuit to solve the above problems.

According to an embodiment of the present invention, a flip-flop circuit includes an input terminal, an output terminal, a control circuit, and a logic circuit. The control circuit is coupled to the input terminal and the output terminal. The control circuit receives an input voltage from the input terminal and an output voltage from the output terminal, and the control circuit generates a plurality of reference voltages at least according to the input voltage and the output voltage. The logic circuit is coupled to the control circuit and the output terminal. When the input voltage is converted from a first voltage value to a second voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from the second voltage value to the first voltage value.

Drawings

FIG. 1 is a schematic diagram of a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a logic circuit according to an embodiment of the invention.

Fig. 3 is an operational diagram of a logic circuit according to a first embodiment of the invention.

FIG. 4 is a diagram illustrating the operation of a logic circuit according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a control circuit according to an embodiment of the invention.

Fig. 6 is a schematic diagram of a comparison circuit in the control circuit according to an embodiment of the invention.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, hardware manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct and indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram of a flip-flop circuit 10 according to an embodiment of the present invention, as shown IN fig. 1, the flip-flop circuit 10 includes an input terminal IN, an output terminal OUT, a control circuit 110 and a logic circuit 120, wherein the control circuit 110 receives an input voltage V from the input terminal IN_inAnd receives an output voltage V from an output terminal OUT_outAnd according to the input voltage V_inAnd an output voltage V_outThe reference voltages VSS, VDD × 2 … VDD × n are generated, wherein VSS may be a ground voltage, in other words, VSS may be the lowest potential point in the flip-flop circuit 10, and VDD is the highest voltage, also called the rated voltage, that can be used in the semiconductor process used to manufacture the flip-flop circuit 10. n may be a positive integer greater than 2, and the value of n depends on practical applications, i.e., the invention is not limited to the value of n, the reference voltage VDD × n represents a reference voltage n times the reference voltage VDD, and the reference voltage VDD × n may be a reference voltage output to the logic circuit 120 through the control circuit 110 via an external input.

IN the present invention, when the input voltage V is on the input terminal IN_inWhen the reference voltage VSS is converted to the reference voltage VDD × n, the flip-flop circuit 10 enables the output voltage V at the output terminal OUT to be the output voltage V through the control circuit 110 and the logic circuit 120_outConverting the reference voltage VDD n into a reference voltage VSS; similarly, when the input voltage V is on the input terminal IN_inWhen the reference voltage VDD × n is converted to the reference voltage VSS, the flip-flop circuit 10 enables the output voltage V on the OUT terminal to be outputted through the control circuit 110 and the logic circuit 120_outThe voltage is converted from the reference voltage VSS to the reference voltage VDD × n, and the detailed conversion process will be described in the following paragraphs.

Fig. 2 is a schematic diagram of a logic circuit 120 according to an embodiment of the invention, as shown in fig. 2, the logic circuit 120 is formed by stacking (cascade) P-type metal oxide semiconductor field effect transistors (abbreviated as transistors in the following paragraphs) MP1, MP2 … MPn and MP (N +1), and N-type transistors MN1, MN2 … MNn and MN (N +1), where N is the same as N of the reference voltage VDD N in fig. 1, and all represent a positive integer, such as 3, 4, 5, and so on. The P-type transistor and the N-type transistor in the logic circuit 120 respectively receive the reference voltage from the control circuit 110 through the gate terminal to control the on/off state of the transistors, and a source terminal of the transistor MP (N +1) is coupled to the reference voltage VDD × N and a source terminal of the transistor MN (N +1) is coupled to the reference voltage VSS. In addition, the control circuit 110 transmits the reference voltage to a source terminal of the transistor MPn and a source terminal of the transistor MNn according to the output voltage V_outDetermines the reference voltage values received by the source terminal of transistor MPn and the source terminal of transistor MNn, thereby controlling the switching states of transistor MPn and transistor MNn and thus completing the output voltage V_outThe conversion of (1).

Fig. 3 is an operation diagram of the logic circuit 120 according to a first embodiment of the present invention, in which N is 2, in other words, the logic circuit 120 includes P-type transistors MP1, MP2 and MP3 and N-type transistors MN1, MN2 and MN3, which are stacked on each other as shown in fig. 3. This embodiment describes when the input voltage V is_inWhen the voltage is converted from the reference voltage VSS to VDD × 2, the logic circuit 120 operates. In the initial state (step 1 marked with number 1 in fig. 3), when the input voltage V is applied_inWhen the reference voltage is VSS, the output voltage is V_outThe reference voltage VDD 2 should be in the last transition state, and the gate terminals of the P-type transistors MP1-MP3 are all from the bottomThe control circuit 110 receives a reference voltage VDD, and the gate terminals of the N-type transistors MN1-MN3 receive the reference voltages VDD × 2, VDD and VSS from the control circuit 110, respectively; then, the voltage V is inputted_inThe control circuit 110 transmits the reference voltage VDD to the gate terminals of the N-type transistors MN1-MN3 (step 2 marked with numeral 2 in FIG. 3) starting from the reference voltage VSS, and those skilled in the art should readily understand that when the input voltage of the flip-flop circuit increases from a low level to a high level, the output voltage must be switched after the input voltage exceeds the high threshold voltage, so that the input voltage V is increased_inWhen the reference voltage VSS increases but does not reach the threshold voltage, the control circuit 110 additionally transmits the reference voltage VDD to the source terminal of the N-type transistor MN2 (step 3 in fig. 3, labeled as numeral 3), so that the gate terminal and the source terminal of the N-type transistor MN2 are both turned off by receiving the reference voltage VDD. Then, when the voltage V is inputted_inAfter the high threshold voltage is exceeded, the control circuit 110 stops transmitting the reference voltage VDD to the source terminal of the N-type transistor MN2, the N-type transistor MN2 is turned on, the N-type transistors MN1-MN3 are all turned on, and transmits the reference voltage VSS to the output terminal OUT, so that the output voltage V is output_outFrom the reference voltage VDD × 2 to the reference voltage VSS (step 4 is marked with numeral 4 in fig. 3). Then, the control circuit 110 starts with the reference voltage VSS and transmits the reference voltages to the P-type transistors MP1-MP3 at intervals of the reference voltage VDD, specifically, the gate of the P-type transistor MP1 receives the reference voltage VSS, the gate of the P-type transistor MP2 receives the reference voltage VDD, and the gate of the P-type transistor MP3 receives the reference voltage VDD 2, so that the gate voltage is in an arithmetic series { VSS, VDD 2}, and the gate of the P-type transistor MP3 is in an off state because the gate voltage is VDD 2, and the rest of the P-type transistors generate the voltage reduction function because the gate voltage is a decreasing voltage at intervals of VDD. Thus, the output voltage V_outThe voltage across any transistor in the logic circuit 120 will not exceed the rated voltage, thereby greatly reducing the possibility of transistor damage.

FIG. 4 is a diagram illustrating the operation of the logic circuit 120 according to a second embodiment of the present invention, wherein n is 2 in this embodimentIn other words, the logic circuit 120 includes P-type transistors MP1, MP2, and MP3 and N-type transistors MN1, MN2, and MN3, which are stacked on each other as shown in fig. 4. This embodiment describes when the input voltage V is_inWhen the voltage is converted from the reference voltage VDD × 2 to VSS, the logic circuit 120 operates. In the initial state (marked with number 1 as step 1 in fig. 4), when the input voltage V is applied_inWhen the reference voltage is VDD 2, the output voltage is V_outThe reference voltage VSS should be the last switching state, in which the gate terminals of the N-type transistors MN1-MN3 all receive the reference voltage VDD from the control circuit 110, and the gate terminals of the P-type transistors MP1-MP3 receive the reference voltages VSS, VDD and VDD × 2 from the control circuit 110, respectively; then, the voltage V is inputted_inWhen the reference voltage VDD is decreased from VDD × 2, the control circuit 110 transmits the reference voltage VDD to the gate terminals of the P-type transistors MP1-MP3 (step 2 marked with numeral 2 in fig. 4), as described in the embodiment of fig. 3, the input voltage of the flip-flop circuit is decreased from high to low, and the output voltage must be switched after the low threshold voltage, so that the input voltage V is changed_inWhen the reference voltage VDD × 2 starts to decrease but does not reach the low threshold voltage, the control circuit 110 additionally transmits the reference voltage VDD to the source terminal of the P-type transistor MP2 (step 3 marked with numeral 3 in fig. 4), so that the gate terminal and the source terminal of the P-type transistor MP2 are both turned off by receiving the reference voltage VDD. Then, when the voltage V is inputted_inAfter the threshold voltage is too low, the control circuit 110 stops transmitting the reference voltage VDD to the source terminal of the P-type transistor MP2, and the P-type transistor MP2 is turned on, at this time, the P-type transistors MP1-MP3 are all turned on, and transmits the reference voltage VDD 2 to the output terminal OUT, so that the output voltage V is output_outFrom the reference voltage VSS, the reference voltage VDD × 2 is converted (the 4 th step is marked with the numeral 4 in fig. 4). Then, the control circuit 110 starts with a reference voltage VDD × 2 and transmits the reference voltages to the N-type transistors MN1-MN3 at intervals of the reference voltage VDD, specifically, the gate of the N-type transistor MN1 receives the reference voltage VDD × 2, the gate of the N-type transistor MN2 receives the reference voltage VDD, and the gate of the N-type transistor MN3 receives the reference voltage VSS, such that the gate voltages exhibit an arithmetic progression { VSS, VDD }, and the N-type transistor MN3 exhibits an off-state due to the gate voltage thereof being VSSThe other N-type transistors generate a step-down function because the gate voltage is a decreasing voltage at intervals of VDD. Thus, the output voltage V_outThe successful conversion to the reference voltage VDD x 2 is achieved without the voltage across any of the transistors in the logic circuit 120 exceeding the rated voltage, thereby greatly reducing the possibility of transistor damage.

It should be noted that, in the embodiments of fig. 3 and fig. 4, n is 2 for example, but this is not a limitation of the present invention, when the reference voltage VDD × n is larger due to the higher value of n (e.g. n is 3, 4, 5 …), the number of transistors stacked in the logic circuit 120 is also increased, so that the voltage across any transistor in the logic circuit 120 can still be maintained not to exceed the rated voltage, thereby protecting the circuit. In addition, the present invention is not limited to the implementation of the control circuit 110, in an embodiment, the control circuit 110 may be implemented in a hardware manner, for example, the control circuit 110 may be a processor, but in other embodiments, the control circuit 110 may be implemented in software, firmware, etc., as long as the control circuit 110 can generate the reference voltages VSS, VDD … VDD (n-1), VDD n to the logic circuit 120, which all fall within the scope of the present invention.

Fig. 5 is a schematic diagram of the control circuit 110 according to an embodiment of the invention, as shown in fig. 5, the control circuit 110 includes the comparison circuits 510, 520, 530 and 540 and the switch circuits 550 and 560, in fig. 5, the switch circuits 550 and 560 and the comparison circuits 510, 520, 530 and 540 are separated for simplicity and convenience of reading, but in this embodiment, the switch circuits 550 and 560 and the comparison circuits 510, 520, 530 and 540 are all implemented in the same circuit. In the present embodiment, the switch circuits 550 and 560 are respectively implemented by a P-type transistor SW1 and an N-type transistor SW 2. However, in other embodiments, the comparison circuits 510, 520, 530, and 540 and the switch circuits 550 and 560 may be implemented independently, and are not limited to being implemented in the same circuit. In detail, the comparison circuit 510 is used for comparing the input voltage V_inAnd a reference voltage VDD, and outputs the higher of the two to the gate terminal of the P-type transistor MP 3; the comparison circuit 520 compares the output voltage V_outAnd a reference voltage VDD, and outputThe lower of the two to the gate terminal of the P-type transistor MP 1; the comparison circuit 530 is used for comparing the output voltage V_outAnd a reference voltage VDD, and outputs the higher of the two to the gate terminal of an N-type transistor MN 1; the comparison circuit 540 is used for comparing the input voltage V_inAnd a reference voltage VDD, and outputs the lower of the two to a gate terminal of an N-type transistor MN 3; the control circuit 110 couples the reference voltage VDD to the gate terminals of the P-type transistor MP2 and the N-type transistor MN 2. In addition, the switch circuits 550 and 560 are based on the output voltage V_outThe voltage values of the transistors SW1 and SW2 are turned on, and if turned on, the reference voltage VDD is transmitted to the source terminals of the P-type transistor MP2 and the N-type transistor MN2, respectively.

Referring to both FIG. 3 and FIG. 5, when in the initial state, the input voltage V is applied_inFor reference voltage VSS, output voltage V_outVDD is VDD 2, the gate terminals of the P-type transistors MP1-MP3 all receive the reference voltage VDD from the control circuit 110 according to the characteristics of the comparison circuit 510 and 520, and the gate terminals of the N-type transistors MN1-MN3 receive the reference voltages VDD 2, VDD and VSS from the control circuit 110 respectively according to the characteristics of the comparison circuit 530 and 540. The switching circuit 560 outputs a voltage V_outTurned on for VDD × 2 to transmit the reference voltage VDD to the source terminal of the N-type transistor MN2, and turned off since the gate terminal and the source terminal of the N-type transistor MN2 are both the reference voltage VDD. With input voltage V_inAfter the reference voltage VSS rises to the reference voltage VDD × 2, the gate terminals of the P-type transistors MP2-MP3 respectively receive the reference voltages VDD and VDD × 2 from the control circuit 110, and the N-type transistor MN3 receives the reference voltage VDD from the control circuit 110. And then the output voltage V_outGradually decreases, eventually resulting in the switch circuit 560 being turned off, and the N-type transistors MN1-MN3 are thus turned on in full numbers, thereby outputting the voltage V_outThe conversion is performed to the reference voltage VSS, and the gate terminals of the N-type transistors MN1 and MN2 receive the reference voltage VDD and the gate terminal of the P-type transistor MP1 receives the reference voltage VSS, thereby implementing the embodiment of FIG. 3.

Referring to both FIG. 4 and FIG. 5, when in the initial state, the input voltage V is set_inThe reference voltage VDD 2 is output voltage V_outIs VSS, becauseThe gate terminals of the P-type transistors MP1-MP3 respectively receive the reference voltages VSS, VDD and VDD 2 from the control circuit 110 according to the characteristics of the comparison circuits 510-520, and the gate terminals of the N-type transistors MN1-MN3 all receive the reference voltage VDD from the control circuit 110 according to the characteristics of the comparison circuits 530-540. The switch circuit 550 outputs a voltage V_outTurned on for VSS to transmit the reference voltage VDD to the source terminal of the P-type transistor MP2, since the gate terminal and the source terminal of the P-type transistor MP2 are both turned off for the reference voltage VDD. With input voltage V_inAfter the voltage from VDD × 2 drops to VSS, the gate terminals of the P-type transistors MP2-MP3 all receive the voltage VDD from the control circuit 110 and the N-type transistor MN3 receives the voltage VSS from the control circuit 110. And then the output voltage V_outGradually rises, eventually causing the switch circuit 550 to be turned off, and the P-type transistors MP1-MP3 are fully turned on, thereby outputting the voltage V_outThe voltage is converted to the reference voltage VDD × 2 to complete the conversion, and the gate terminals of the N-type transistors MN1 and MN2 receive the reference voltages VDD × 2 and VDD, respectively, and the gate terminal of the P-type transistor MP1 receives the reference voltage VDD, thereby implementing the embodiment of fig. 4.

FIG. 6 is a schematic diagram of the comparison circuit 510-540 in the control circuit 110 according to an embodiment of the invention, as shown in FIG. 6, the comparison circuit 510-540 is implemented by two transistors, in detail, the comparison circuit 510 includes a P-type transistor MPX and an MPY, wherein the gate of the P-type transistor MPX is coupled to the reference voltage VDD, and the gate of the P-type transistor MPY is coupled to the input voltage V_inAnd the source terminals of the P-type transistors MPX and MPY are coupled to the gate terminal of the P-type transistor MP3, thereby outputting the input voltage V_inThe higher voltage of the reference voltage VDD to the gate terminal of the P-type transistor MP 3; the comparison circuit 520 comprises N-type transistors MNX and MNY, wherein the gate of the N-type transistor MNX is coupled to the reference voltage VDD, and the gate of the N-type transistor MNY is coupled to the output voltage V_outAnd the source terminals of the N-type transistors MPX and MPY are coupled to the gate terminal of the P-type transistor MP1, thereby outputting the output voltage V_outThe lower voltage of the reference voltage VDD to the gate terminal of the P-type transistor MP 1; the comparison circuit 530 includes P-type transistors MPI and MPJ, wherein the P-type transistor MPIA gate coupled to a reference voltage VDD, and a gate of the P-type transistor MPJ coupled to an output voltage V_outAnd the source terminals of the P-type transistors MPI and MPJ are coupled to the gate terminal of the N-type transistor MN1, thereby outputting an output voltage V_outThe higher of the reference voltage VDD to the gate terminal of the N-type transistor MN 1; the comparison circuit 540 comprises N-type transistors MNI and MNJ, wherein the gate of the N-type transistor MNI is coupled to the reference voltage VDD, and the gate of the N-type transistor MNJ is coupled to the input voltage V_inAnd the source terminals of the N-type transistors MNI and MNJ are coupled to the gate terminal of the N-type transistor MN3, thereby outputting the input voltage V_inThe lower voltage of the reference voltage VDD to the gate terminal of the N-type transistor MN 3.

In the present invention, the control circuit 110 transmits different reference voltages to the transistors stacked in the logic circuit 120, so that after the output voltage is converted, the two terminals of any one of the transistors in the logic circuit 120 will not exceed the rated voltage, thereby greatly reducing the risk of the transistor damage.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Description of the symbols

10 flip-flop circuit

110 control circuit

120 logic circuit

IN input terminal

OUT output terminal

V_inInput voltage

V_outOutput voltage

VSS, VDD 2 … VDD n reference voltages

MP1-MP3, MPn, MP (n +1), MPX, MPY, MPI, MPJ, SW 1P type transistor

MN1-MN3, MNn, MN (N +1), MNX, MNY, MNI, MNJ, SW 2N type transistor

510-540 comparison circuit

550-560 switching circuit