阅读说明：本技术 一种应用于抑制ldo输出电压过冲的方法及电路 (Method and circuit for suppressing output voltage overshoot of LDO (low dropout regulator) ) 是由 陈志坚 王雨晨 陈鸿 李斌 郑彦祺 周绍林 于 2019-10-11 设计创作，主要内容包括：本发明公开了一种应用于抑制LDO输出电压过冲的方法,涉及半导体集成电路的技术领域,解决了对需采用较大的电容用于对LDO输出电压过冲的抑制的技术问题。该方法是通过电压采集模块实时采集LDO的输出电压,并将所述输出电压转换成可随输出电压线性变化反馈信号；输出电压控制模块基于所述反馈信号生成用于表征输出电压变化的控制信号,所述控制信号对LDO的控制端进行调节,使LDO的输出电压包含有过冲电压时,对所述过冲电压进行抑制。本发明还同开了一种应用于抑制LDO输出电压过冲的电路。本发明可对LDO输出电压过冲现象进行有效的抑制,且LDO整体无需采用很大的电容,节省了芯片面积,同时抑制电压过冲的LDO整体功耗也较小,十分节能。(The invention discloses a method for inhibiting output voltage overshoot of an LDO (low dropout regulator), relates to the technical field of semiconductor integrated circuits, and solves the technical problem that a larger capacitor is required to be adopted for inhibiting the output voltage overshoot of the LDO. The method comprises the steps that the output voltage of the LDO is collected in real time through a voltage collecting module, and the output voltage is converted into a feedback signal which can change linearly along with the output voltage; the output voltage control module generates a control signal for representing output voltage change based on the feedback signal, and the control signal regulates a control end of the LDO so as to inhibit the overshoot voltage when the output voltage of the LDO contains the overshoot voltage. The invention also discloses a circuit for inhibiting the overshoot of the output voltage of the LDO. The invention can effectively inhibit the overshoot phenomenon of the output voltage of the LDO, and the LDO does not need to adopt a large capacitor, thereby saving the area of a chip.)

1. A method for restraining output voltage overshoot of an LDO (low dropout regulator) is characterized in that the output voltage of the LDO is collected in real time through a voltage collection module, and the output voltage is converted into a feedback signal which can change linearly along with the output voltage; the output voltage control module generates a control signal for representing output voltage change based on the feedback signal, and the control signal regulates a control end of the LDO so as to inhibit the overshoot voltage when the output voltage comprises the overshoot voltage.

2. The method for suppressing the output voltage overshoot of the LDO according to claim 1, wherein the control signal regulates a control terminal of the LDO, and particularly the control signal regulates a power tube (M8) of the LDO, comprising:

the power tube (M8) drops the input voltage according to the reference voltage to obtain the output voltage, when the output voltage comprises the overshoot voltage, the control signal pulls down the grid potential of the power tube (M8) to reduce the drain voltage of the power tube (M8) and restrain the overshoot voltage.

3. The method of claim 1, wherein the output voltage control module is enabled to be in a stable operation state by biasing the input terminal (Vbp), so that the output voltage control module responds to the feedback signal in real time.

4. The circuit applied to suppress the overshoot of the output voltage of the LDO comprises the LDO, the LDO comprises a power tube (M8), the drain of the power tube (M8) is a power output end (Vout), the circuit is characterized by further comprising a voltage acquisition module and an output voltage control module, the input end of the voltage acquisition module is connected with the drain of the power tube (M8), the feedback end of the voltage acquisition module is connected with the control end of the output voltage control module, and the output end of the output voltage control module is connected with the gate of the power tube (M8).

5. The circuit for suppressing the overshoot of the LDO output voltage according to claim 4, wherein the input voltage control module comprises a first control unit, a second control unit, and a bias input terminal (Vbp), the control terminal of the first control unit is connected to the bias input terminal (Vbp), the output terminal of the first control unit is connected to the control terminal of the second control unit, the control terminal of the second control unit is further connected to the feedback terminal of the voltage acquisition module, and the output terminal of the second control unit is connected to the gate of the power transistor (M8).

6. The circuit for suppressing LDO output voltage overshoot according to claim 5, wherein said first control unit comprises a first transistor (M1); the second control unit comprises a second transistor (M2); the source of the first transistor (M1) is connected with the source of the second transistor (M2), the gate of the first transistor (M1) is connected with the bias input end (Vbp), the drain of the first transistor (M1) is connected with the gate of the second transistor (M2), and the drain of the second transistor (M2) is connected with the gate of the power tube (M8).

7. The circuit for suppressing the overshoot of the LDO output voltage according to claim 5, wherein the voltage acquisition module comprises a voltage detection unit and a current source unit, an input terminal of the current detection unit is connected to the drain of the power transistor (M8), an output terminal of the current detection unit is connected to an input terminal of the current source unit, and an output terminal of the current source unit is connected to the control terminal of the second control unit.

8. The circuit for suppressing the overshoot of the LDO output voltage according to claim 7, wherein the voltage detection unit comprises a third transistor (M3), a fourth transistor (M4), and a fifth transistor (M5); the current source unit includes a sixth transistor (M6) and a seventh transistor (M7); the gate and the drain of the third transistor (M3) are both connected to the drain of a power transistor (M8), the gate and the drain of the fourth transistor (M4) are both connected to the source of the third transistor (M3), the gate and the drain of the fifth transistor (M5) are both connected to the source of the fourth transistor (M4), the gate and the drain of the sixth transistor (M6) are both connected to the source of the fifth transistor (M5), the gate of the sixth transistor (M6) is also connected to the gate of a seventh transistor (M7), the drain of the seventh transistor (M7) is connected to the control terminal of the second control unit, and the source of the sixth transistor (M6) and the source of the seventh transistor (M7) are both grounded.

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a method and a circuit for suppressing output voltage overshoot of an LDO (low dropout regulator).

Background

Since an integrated chip contains many modules, and the operating voltages required by the modules may be different from each other, we usually use a power management chip to implement the functions of voltage conversion, power distribution, detection, etc. The LDO, which is called a Low Drop-out Voltage Regulator (Low Drop-out Voltage Regulator), is an indispensable part of a power management chip, and can maintain a specified output Voltage in a wide range of load current and input Voltage, and the difference between the input Voltage and the output Voltage can be small. In addition, the LDO has the characteristics of low self power consumption, low noise, small quiescent current, low cost and the like, so that the LDO is widely applied.

However, due to the structural problem, during the power-on process, the output voltage of the LDO will generate an instantaneous overshoot, which will affect the life of the LDO itself and the module supplying power. If the output transient voltage of the LDO is too high, a series of problems such as breakdown of the subsequent module may occur, and therefore, it is necessary and desirable to suppress the output voltage overshoot of the LDO. Most of the existing LDOs adopt larger on-chip capacitors and even off-chip capacitors to suppress output voltage overshoot, so that the problem of larger area is brought, and the design requirements of high integration degree and small volume of an integrated circuit are not met.

Disclosure of Invention

The invention aims to solve the technical problem of the prior art, and aims to provide a method for suppressing the overshoot of the output voltage of an LDO (low dropout regulator), which can effectively suppress the overshoot of the output voltage of the LDO.

The invention also aims to provide a circuit for applying and inhibiting the overshoot of the output voltage of the LDO, which can effectively inhibit the overshoot of the output voltage of the LDO.

In order to achieve the first purpose, the invention provides a method for inhibiting the overshoot of the output voltage of an LDO (low dropout regulator). the output voltage of the LDO is collected in real time through a voltage collection module, and is converted into a feedback signal which can change linearly along with the output voltage; the output voltage control module generates a control signal for representing output voltage change based on the feedback signal, and the control signal regulates a control end of the LDO so as to inhibit the overshoot voltage when the output voltage of the LDO contains the overshoot voltage.

In a further improvement, the control signal adjusts a control terminal of the LDO, and specifically, the control signal adjusts a power transistor of the LDO, including:

the power tube drops the input voltage according to the reference voltage to obtain the output voltage, and when the output voltage comprises the overshoot voltage, the control signal pulls down the grid potential of the power tube to reduce the drain voltage of the power tube and suppress the overshoot voltage.

Furthermore, the output voltage control module is in a stable working state through a bias input end, so that the output voltage control module responds to the feedback signal in real time.

In order to achieve the second purpose, the invention provides a circuit for suppressing the overshoot of the output voltage of the LDO, which comprises the LDO, the LDO comprises a power tube, the drain of the power tube is a power output end, the LDO further comprises a voltage acquisition module and an output voltage control module, the input end of the voltage acquisition module is connected with the drain of the power tube, the feedback end of the voltage acquisition module is connected with the control end of the output voltage control module, and the output end of the output voltage control module is connected with the gate of the power tube.

The input voltage control module comprises a first control unit, a second control unit and a bias input end, the control end of the first control unit is connected with the bias input end, the output end of the first control unit is connected with the control end of the second control unit, the control end of the second control unit is further connected with the feedback end of the voltage acquisition module, and the output end of the second control unit is connected with the grid electrode of the power tube.

Further, the first control unit includes a first transistor, the second control unit includes a second transistor, a source of the first transistor is connected to a source of the second transistor, a gate of the first transistor is connected to the bias input terminal, a drain of the first transistor is connected to a gate of the second transistor, and a drain of the second transistor is connected to a gate of the power transistor.

Furthermore, the voltage acquisition module comprises a voltage detection unit and a current source unit, the input end of the current detection unit is connected with the drain electrode of the power tube, the output end of the current detection unit is connected with the input end of the current source unit, and the output end of the current source unit is connected with the control end of the second control unit.

Further, the voltage detection unit includes a third transistor, a fourth transistor, and a fifth transistor; the current source unit includes a sixth transistor and a seventh transistor; the grid electrode and the drain electrode of the third transistor are both connected with the drain electrode of the power tube, the grid electrode and the drain electrode of the fourth transistor are both connected with the source electrode of the third transistor, the grid electrode and the drain electrode of the fifth transistor are both connected with the source electrode of the fourth transistor, the grid electrode and the drain electrode of the sixth transistor are both connected with the source electrode of the fifth transistor, the grid electrode of the sixth transistor is further connected with the grid electrode of the seventh transistor, the drain electrode of the seventh transistor is connected with the control end of the second control unit, and the source electrode of the sixth transistor and the source electrode of the seventh transistor are both grounded.

Advantageous effects

The invention has the advantages that: through adding a voltage acquisition module that is used for gathering output voltage at the output of LDO, voltage acquisition module feeds back the voltage signal who gathers to output voltage control module, is suppressed the output overshoot voltage of LDO by output voltage control module to realized the suppression to LDO output voltage overshoot phenomenon, avoided other circuits of LDO lug connection, its overshoot voltage causes the easy problem of damaging of electronic component of other circuits easily. In addition, only transistors are adopted in the voltage acquisition module and the output voltage control module, so that the LDO is ensured not to adopt a large capacitor, and the use area of a chip is greatly reduced; and the transistor is adopted as the load of the voltage acquisition module, so that the whole power consumption of the LDO capable of inhibiting the voltage overshoot is smaller, and the energy is saved.

Drawings

FIG. 1 is a block diagram of the LDO of the present invention;

FIG. 2 is a schematic structural diagram of an LDO according to the present invention;

FIG. 3 is a circuit diagram of the LDO;

FIG. 4 is a circuit diagram of the LDO of the present invention;

FIG. 5 is a fast power-up waveform of the LDO;

FIG. 6 is a slow power-up waveform of the LDO;

FIG. 7 is a fast power-up waveform of the LDO of the present invention as a whole;

fig. 8 is a slow power-up waveform diagram of the LDO of the present invention as a whole.

Wherein: m1-a first transistor, M2-a second transistor, M3-a third transistor, M4-a fourth transistor, M5-a fifth transistor, M6-a sixth transistor, M7-a seventh transistor, M8-a power tube, U1-a differential operational amplifier, C1-a first capacitor, R1-a first resistor, R2-a second resistor, a VCC-power supply terminal, a VREF-reference voltage input terminal, a Vbp-bias input terminal and a Vout-power output terminal.

Detailed Description

The invention is further described below with reference to examples, but not to be construed as being limited thereto, and any number of modifications which can be made by anyone within the scope of the claims are also within the scope of the claims.

Referring to fig. 1-2, in the method for suppressing the overshoot of the output voltage of the LDO according to the present invention, the output voltage of the LDO is collected in real time by the voltage collection module, and the output voltage is converted into a feedback signal that can change linearly with the output voltage; the output voltage control module generates a control signal for representing the change of the output voltage based on the feedback signal, and the control signal regulates the control end of the LDO so as to inhibit the overshoot voltage when the output voltage of the LDO contains the overshoot voltage, thereby realizing the inhibition of the overshoot phenomenon of the output voltage of the LDO. Specifically, control signal adjusts the control end of LDO, specifically control signal adjusts power tube M8 of LDO, includes: the power tube M8 drops the input voltage according to the reference voltage to obtain the output voltage, and when the output voltage includes the overshoot voltage, the control signal pulls down the gate potential of the power tube M8 to lower the drain voltage of the power tube M8 and suppress the overshoot voltage. The output voltage control module is in a stable working state through the bias input end Vbp, so that the output voltage control module responds to the feedback signal in real time, the purpose of accurately, real-timely and nondestructively feeding back the overshoot voltage to the output voltage control module is achieved, the output voltage control module regulates the drain voltage of the power tube M8 in real time, and the overshoot voltage is suppressed in real time.

When the output voltage of the LDO contains the overshoot voltage, the current of the feedback signal output by the voltage acquisition module increases linearly with the overshoot voltage in the output voltage, and the linearly increased feedback signal pulls down the voltage at the input end of the output voltage control module, and correspondingly, the voltage at the output end of the output voltage control module, that is, the voltage of the control signal, also decreases, so as to pull down the gate voltage of the power tube M8, increase the source-gate voltage of the power tube M8, cause the current at the source-drain electrode of the power tube to increase, finally cause the drain voltage of the power tube M8 to decrease, and realize suppression of the overshoot voltage of the output voltage of the LDO. Wherein, the power tube M8 is a P-type field effect tube.

The utility model provides a be applied to circuit of restraining LDO output voltage overshoot, including LDO, LDO includes power tube M8, and the drain electrode of power tube M8 is power output end Vout, still includes voltage acquisition module and output voltage control module, and the input of voltage acquisition module is connected with the drain electrode of power tube M8, and the feedback end of voltage acquisition module is connected with the control end of output voltage control module, and the output of output voltage control module is connected with the grid of power tube M8. Referring to fig. 3, the LDO further includes a differential operational amplifier U1, a first capacitor C1, a first resistor R1, and a second resistor R2, wherein a reference voltage input terminal VREF is input to an inverting input terminal of the differential operational amplifier U1, an output terminal of the differential operational amplifier U1 is connected to a gate of a power transistor M8, the gate of the power transistor M8 is connected to a drain thereof through the first capacitor C1, the drain of the power transistor M8 is further grounded through the first resistor R1 and the second resistor R2, and a source of the power transistor M8 is connected to a power supply terminal VCC. The non-inverting input terminal of the differential operational amplifier U1 is connected to the connection terminal of the first resistor R1 and the second resistor R2.

The differential operational amplifier U1, the first capacitor C1, the first resistor R1, the second resistor R2 and the power transistor M8 form a conventional LDO architecture. According to the virtual short and virtual break characteristics of the differential operational amplifier U1, the differential operational amplifier U1 ensures that the feedback voltage between the first resistor R1 and the second resistor R2 is equal to the output reference voltage. The first capacitor C1, acting as a miller capacitor, compensates for the phase margin of the LDO loop and improves the stability of the loop, and its magnitude is usually determined by the differential operational amplifier U1. The magnitude and proportional relationship between the first resistor R1 and the second resistor R2 determine the current passing through the branch and the output voltage of the power output terminal Vout, and the formula is as follows:

wherein the content of the first and second substances,

and

are currents through the first resistor R1 and the second resistor R2, which are known to have equal relationships due to the virtual cutoff characteristics of the differential operational amplifier U1.

In this embodiment, the input voltage control module includes a first control unit, a second control unit, and a bias input terminal Vbp. The bias input end Vbp is used for providing a stable input voltage, and the first control unit is locked, so that the working area of the first control unit cannot be changed, and the impedance of the first control unit is prevented from being greatly fluctuated. The control end of the first control unit is connected with the bias input end Vbp, the output end of the first control unit is connected with the control end of the second control unit, the control end of the second control unit is further connected with the feedback end of the voltage acquisition module, and the output end of the second control unit is connected with the grid electrode of the power tube M8. The voltage acquisition module comprises a voltage detection unit and a current source unit, and the input end of the current detection unit is connected with the drain electrode of the power tube M8. The output end of the current detection unit is connected with the input end of the current source unit, and the output end of the current source unit is connected with the control end of the second control unit.

Referring to fig. 4, the first control unit includes a first transistor M1, the second control unit includes a second transistor M2, and a source of the first transistor M1 is connected to a source of the second transistor M2 and is also connected to a power supply terminal VCC. The gate of the first transistor M1 is connected to the bias input Vbp, the drain of the first transistor M1 is connected to the gate of the second transistor M2, and the drain of the second transistor M2 is connected to the gate of the power transistor M8. The voltage detection unit includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5; the current source unit includes a sixth transistor M6 and a seventh transistor M7. The gate and the drain of the third transistor M3 are both connected to the drain of the power transistor M8, the gate and the drain of the fourth transistor M4 are both connected to the source of the third transistor M3, the gate and the drain of the fifth transistor M5 are both connected to the source of the fourth transistor M4, the gate and the drain of the sixth transistor M6 are both connected to the source of the fifth transistor M5, the gate of the sixth transistor M6 is also connected to the gate of the seventh transistor M7, and the drain of the seventh transistor M7 is connected to the control terminal of the second control unit. That is, the drain of the seventh transistor M7 is connected to the gate of the second transistor M2. The source of the sixth transistor M6 and the source of the seventh transistor M7 are both grounded.

The first transistor M1 and the second transistor M2 are P-type field effect transistors; the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are N-type field effect transistors.

It is difficult to fabricate resistors with precisely controlled resistance values or resistors with reasonable physical dimensions under many CMOS process conditions. Therefore, in the voltage acquisition module, a third crystal is adoptedThe tube M3, the fourth transistor M4 and the fifth transistor M5 are used as loads of the voltage acquisition module. Because the grid electrode and the drain electrode of the transistor are in short circuit, the potentials of the grid electrode and the drain electrode are always the same, the transistor is always in a state of a saturation region after being electrified, and the impedance of the transistor isWherein g is_mIs transconductance. The transconductance of the transistor is related to parameters such as the threshold voltage of the transistor and the width-to-length ratio of the transistor, and in practical application, the impedance of the transistor in this connection mode can be adjusted by adjusting the width-to-length ratio of the transistor.

When the transient output voltage of the power output terminal Vout is too large, the gate-to-drain voltage of the third transistor M3 becomes large, thereby causing the drain and source currents of the third transistor M3 to increase. Since the gates and the drains of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are connected, drain and source currents through the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are increased. Since the sixth transistor M6 and the seventh transistor M7 constitute a current source unit, the current of the branch of the seventh transistor M7 and the first transistor M1 becomes large. And the gate of the first transistor M1 is biased by the bias input terminal Vbp, so that the current at the drain of the first transistor M1 does not change, and the impedance thereof does not fluctuate greatly, which results in a reduction in the gate voltage of the second transistor M2. Since the source of the second transistor M2 is connected to the power supply terminal VCC, the source and gate voltages thereof increase, which results in an increase in the source and drain currents of the second transistor M2, and a decrease in the drain voltage thereof, and a decrease in the gate voltage of the power transistor M8. When the gate voltage of the power transistor M8 is reduced, the source and drain currents passing through the power transistor M8 are also increased, so that the output voltage of the power output terminal Vout is reduced, the purpose of a negative feedback loop is achieved, and the overshoot voltage of the output voltage is suppressed.

In the power-on process, due to the effect of the bias voltage of the bias input terminal Vbp on the output voltage control module, when the power supply voltage of the power supply terminal VCC is smaller than the set bias voltage, the first transistor M1 is turned off, the drain voltage thereof is zero, so that the gate voltage of the second transistor M2 is also zero, the gate voltage of the power transistor M8 is pulled up to the input voltage of the power supply terminal VCC, and the power transistor M8 is turned off. That is, for the power-up process, in the state of VCC < Vbp + Vth, the output voltage of the power output terminal Vout is zero. Where Vth is the turn-on voltage of the first transistor M1. For the whole LDO, the power-on process starts to respond only after VCC > Vbp + Vth, i.e. the output voltage of the power output terminal Vout is greater than zero.

When the supply voltage of the LDO is 25V and the output voltage of the power output terminal Vout is 10V, the 50us fast power-up process is as shown in fig. 5 and the 2ms slow power-up process is as shown in fig. 6. The voltage of the reference voltage input terminal VREF is 1.18V, the first resistor R1 is 747.5K, and the second resistor R2 is 100K.

From fig. 5 and 6, it can be seen that the fast power-up and slow power-up processes of the LDO are performed, and if the circuit module for suppressing the output voltage overshoot is not added, the transient output voltage overshoot of the LDO is very large and is substantially as fast as the supply voltage of the power supply terminal VCC. If the LDO is directly connected to other circuits, such an overshoot voltage may cause some electronic components to break down, causing damage to other circuits.

For the whole LDO with the added output voltage control module and voltage acquisition circuit module, when the supply voltage is 25V and the output voltage of the power output terminal Vout is 10V, the 50us fast power-up process is as shown in fig. 7 and the 2ms slow power-up process is as shown in fig. 8. The voltage of the reference voltage input terminal VREF is 1.18V, the first resistor R1 is 747.5K, the second resistor R2 is 100K, and the bias voltage of the bias input terminal Vbp is 24.14V.

As can be seen from fig. 7 and 8, in both the fast power-on mode and the slow power-on mode, the output voltage of the power output terminal Vout does not exceed 10.14V at the highest, and is only 0.1V greater than the expected output voltage, so that the overshoot voltage of the output voltage is greatly suppressed. The LDO does not adopt a large capacitor as a whole, so that the use area of a chip is greatly reduced; in addition, the output voltage control module for suppressing the overshoot voltage and the voltage acquisition circuit module are both field effect transistors, so that the whole power consumption of the LDO capable of suppressing the voltage overshoot is low. Through the test, under the condition that the power supply voltage of the power supply terminal VCC is 25V, the whole power consumption is 500 nA. In addition, the power consumption can be adjusted by adjusting the width-to-length ratios of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 to increase or decrease the impedances thereof.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various changes and modifications without departing from the structure of the invention, which will not affect the effect of the invention and the practicability of the patent.