阅读说明：本技术 半导体器件和方法
(Semiconductor device and method
) 是由 余振华
余国宠
余俊辉 于 2018-12-17 设计创作，主要内容包括：在实施例中,一种器件包括：第一器件,包括：具有第一连接件的集成电路器件；第一光敏粘合层,位于集成电路器件上；以及第一导电层,位于第一连接件上,第一光敏粘合层围绕第一导电层；第二器件,包括：具有第二连接件的内插器；第二光敏粘合层,位于内插器上,第二光敏粘合层物理连接至第一光敏粘合层；以及第二导电层,位于第二连接件上,第二光敏粘合层围绕第二导电层；以及导电连接件,接合第一导电层和第二导电层,通过气隙围绕导电连接件。本发明实施例涉及半导体器件和方法。(In an embodiment, a device comprises: a first device comprising: an integrated circuit device having a first connection; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device comprising: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer being physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector joining the first conductive layer and the second conductive layer, surrounding the conductive connector through an air gap. Embodiments of the invention relate to semiconductor devices and methods.)
1. A semiconductor device, comprising:
a first device comprising:
an integrated circuit device having a first connection;
a first photosensitive adhesive layer on the integrated circuit device; and
a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer;
a second device comprising:
an interposer having a second connector;
a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and
a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and
a conductive connector joining the first and second conductive layers, the conductive connector being surrounded by an air gap.
2. The semiconductor device according to claim 1, wherein a first width of the first conductive layer is smaller than a second width of the second conductive layer.
3. The semiconductor device of claim 2, wherein the conductive connection has a first portion adjacent to a first integrated circuit device and a second portion adjacent to a second integrated circuit device, the first portion having a first width and the second portion having a second width greater than the first width.
4. The semiconductor device of claim 3, wherein the air gap separates the second portion of the conductive connection from the first photosensitive adhesive layer.
5. The semiconductor device according to claim 1, wherein a seed layer is not formed between the first connection and the first conductive layer or between the first conductive layer and the conductive connection.
6. The semiconductor device of claim 1, further comprising:
a first seed layer formed between the first connection and the first conductive layer, wherein no seed layer is formed between the first conductive layer and the conductive connection.
7. A method of forming a semiconductor device, comprising:
forming a first opening in a first photosensitive adhesive layer adjacent a first side of a first integrated circuit device;
plating a first reflowable layer in the first opening;
forming a second opening in a second photosensitive adhesive layer adjacent to a first side of a second integrated circuit device;
plating a second reflowable layer in the second opening;
laminating the first photosensitive adhesive layer and the second photosensitive adhesive layer together to physically connect the first integrated circuit device and the second integrated circuit device; and
reflowing the first and second reflowable layers to form a conductive connection electrically connecting the first and second integrated circuit devices.
8. The method of claim 7, further comprising:
sealing the first integrated circuit device with a molding compound adjacent to a first side of the second integrated circuit device;
dividing the first integrated circuit device;
forming a redistribution structure adjacent a second side of the second integrated circuit device; and
forming conductive balls on the redistribution structure.
9. The method of claim 8, further comprising:
bonding the second integrated circuit device to a package substrate using the conductive balls.
10. A method of forming a semiconductor device, comprising:
encapsulating a plurality of first integrated circuit devices with a first molding compound;
forming a first photosensitive adhesive layer over the first integrated circuit device;
patterning a first opening in the first photosensitive adhesive layer;
plating a first conductive layer in the first opening;
plating a first reflowable layer on the first conductive layer, the combined thickness of the first conductive layer and the first reflowable layer being less than the first thickness of the first photosensitive adhesive layer, the first conductive layer and the first reflowable layer being electrically connected to the first integrated circuit device;
pressing a second integrated circuit device to the first photosensitive adhesive layer to physically connect the first integrated circuit device and the second integrated circuit device; and
reflowing the first reflowable layer to form a conductive connection electrically connecting the first integrated circuit device and the second integrated circuit device.
Technical Field
Embodiments of the invention relate to semiconductor devices and methods.
Background
With the development of Integrated Circuits (ICs), the semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the ever-decreasing size of the smallest components, which allows more components to be integrated into a given area.
These integration improvements are two-dimensional (2D) in nature because the area occupied by the integrated components is substantially on the surface of the semiconductor wafer. The increase in density and corresponding decrease in area of integrated circuits often exceeds the ability to bond integrated circuit chips directly to a substrate. Interposers have been used to reassign ball contact areas from the chip to a larger area of the interposer. Furthermore, interposers have allowed three-dimensional (3D) packages including multiple chips. Other packages have also been developed to incorporate various aspects of 3D.
Disclosure of Invention
According to some embodiments of the present invention, there is provided a semiconductor device including: a first device comprising: an integrated circuit device having a first connection; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device comprising: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector joining the first conductive layer and the second conductive layer, surrounding the conductive connector through an air gap.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor device, including: forming a first opening in a first photosensitive adhesive layer adjacent a first side of a first integrated circuit device; plating a first reflowable layer in the first opening; forming a second opening in a second photosensitive adhesive layer adjacent to a first side of a second integrated circuit device; plating a second reflowable layer in the second opening; laminating the first photosensitive adhesive layer and the second photosensitive adhesive layer together to physically connect the first integrated circuit device and the second integrated circuit device; and reflowing the first and second reflowable layers to form a conductive connection electrically connecting the first and second integrated circuit devices.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor device, including: encapsulating a plurality of first integrated circuit devices with a first molding compound; forming a first photosensitive adhesive layer over the first integrated circuit device; patterning a first opening in the first photosensitive adhesive layer; plating a first conductive layer in the first opening; plating a first reflowable layer on the first conductive layer, the combined thickness of the first conductive layer and the first reflowable layer being less than the first thickness of the first photosensitive adhesive layer, the first conductive layer and the first reflowable layer being electrically connected to the first integrated circuit device; pressing a second integrated circuit device to the first photosensitive adhesive layer to physically connect the first integrated circuit device and the second integrated circuit device; and reflowing the first reflowable layer to form a conductive connection electrically connecting the first integrated circuit device and the second integrated circuit device.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-2B are various diagrams of intermediate steps during processing of an integrated circuit device, according to some embodiments.
Fig. 3A-4B are various diagrams of intermediate steps during processing of a wafer, according to some embodiments.
Fig. 5A-18 are various diagrams of intermediate steps during a process of forming a device package, according to some embodiments.
Fig. 19 is a diagram of a device package according to some embodiments.
Fig. 20 illustrates a device package according to some other embodiments.
Fig. 21 illustrates a device package according to other embodiments.
Fig. 22-33 are various diagrams of intermediate steps during a process for forming a device package, according to some embodiments.
Fig. 34 illustrates a device package according to some other embodiments.
Fig. 35 illustrates a device package according to still other embodiments.
Fig. 36 illustrates a device package according to still other embodiments.
Fig. 37-46 are various diagrams of intermediate steps during a process for forming a device package, according to some embodiments.
Fig. 47-57 are various diagrams of intermediate steps during a process for forming a device package, according to some embodiments.
Fig. 58A-58F illustrate a process for forming a conductive connection according to another embodiment.
Fig. 59A to 59K illustrate a process for forming a conductive connection according to another embodiment.
Fig. 60A-60F illustrate a process for forming a conductive connection according to another embodiment.
Fig. 61A and 61B are various views of a device package according to some other embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
According to some embodiments, an electrically conductive connection is formed. A photosensitive adhesive film is formed on the die and wafer. Openings are formed in the photosensitive adhesive film to expose the die and wafer connections. A conductive layer and a reflowable layer are plated in the opening. It is noted that the combined thickness of the conductive layer and the reflowable layer in each opening is less than the thickness of the photosensitive adhesive film. The die and the wafer are physically connected to each other by the photosensitive adhesive film, and then the die and the wafer are electrically connected to each other by reflowing the reflowable layer to form a conductive connector. Because the open bottom is filled with reflowable material, an air gap is formed around the resulting conductive connection. The formation of the air gap may provide a cushion around the conductive connections, avoiding the risk of short circuits forming when the spacing between adjacent conductive connections is reduced.
Fig. 1A-2B are various diagrams of intermediate steps during processing of an integrated circuit device 50, according to some embodiments. Fig. 1A to 2B are cross-sectional views in which a diagram ending with an "a" mark shows an overall view, and a diagram ending with a "B" mark shows a region R from the respective "a" view1Detailed description of the drawings.
The integrated circuit device 50 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE) die), etc., or a combination thereof. The integrated circuit devices 50 may be formed in a wafer, wherein the wafer may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit devices 50. Integrated circuit device 50 includes a substrate 52 and a connector 54.
The substrate 52 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 52 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. The substrate 52 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, and the like, may be formed in and/or on the active surface (e.g., the upward facing surface) of the substrate 52.
An interconnect structure having a dielectric layer and corresponding metallization pattern is formed on the active surface of the substrate 52. The dielectric layer may be an inter-metal dielectric (IMD) layer. For example, low-K dielectric materials, such as undoped silicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO, and the like, may be formed from low-K dielectric materials by any suitable method known in the art, such as spin-on coating, Chemical Vapor Deposition (CVD), plasma-enhanced CVD (pecvd), high-density plasma chemical vapor deposition (HDP-CVD), and the likexCySpin-on glass, spin-on polymer, silicon carbon material, compound thereof, and composite thereofCombinations of (e) and the like) form the IMD layer. The metallization patterns in the dielectric layer may route electrical signals between devices, for example, by using vias and/or traces, and may also include various electronic devices such as capacitors, resistors, inductors, and the like. The various devices and metallization patterns may be interconnected to implement one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, and the like. Additionally, connections 54, such as conductive pillars or contact pads, are formed in and/or on the interconnect structure to provide external electrical connections to the circuit and device. Those of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes. Other circuits may be used as appropriate for a given application.
In fig. 1A and 1B, a photosensitive adhesive film 56 is formed on the active surface of the substrate 52. The photosensitive adhesive film 56 may be formed of, for example, benzocyclobutene (BCB), epoxy film (SU-8), ShinEtsu SINRTMAn organic photopolymer layer (PSPL) of polyimide or the like, and may be formed by spin coating or the like. The photosensitive adhesive film 56 may also be referred to as an adhesive layer. After formation, photosensitive adhesive film 56 may be exposed for patterning. The pattern of photosensitive adhesive film 56 corresponds to connector 54. The patterning forms a pattern of openings 58 through photosensitive adhesive film 56, exposing portions of connectors 54. Width W of each opening 581May be less than the width of the connector 54, such as width W1From about 1 μm to about 40 μm. Width W1Or may be greater than or equal to the width of the connector 54. After forming and patterning the photosensitive adhesive film 56, it is cured, for example, by an annealing process, which may be performed in an oven at a temperature of less than about 200 ℃. The formed photosensitive adhesive film 56 has a thickness T of from about 1 μm to about 10 μm1. The depth of the opening 58 is equal to the thickness T1。
In fig. 2A and 2B, a conductive layer 60 is formed in the opening 58 located on the connection member 54. The conductive layer 60 is formed of a conductive material such as nickel, copper, gold, or the like, or a combination thereof, and is formed by a plating process such as electroless plating using the connection member 54 instead of a seed layer. A reflowable layer 62 is then formed over the conductive layer 60 in the opening 58. Reflowable layer 62 is formed of a reflowable material such as solder, tin, or the like, or a combination thereof, and is formed by a plating process using conductive layer 60 in place of a seed layer.
The conductive layer 60 and the reflowable layer 62 have a combined thickness T of from about 1 μm to about 10 μm2. Thickness T2Less than thickness T1. According to the width W1The thickness of the reflowable layer 62 is calculated so that enough reflowable material is formed for a subsequently formed conductive connection. In this way, the top surface of the photosensitive adhesive film 56 extends above the top surface of the reflowable layer 62. Form a gap G1Wherein, the gap G1Is equal to the thickness T1And T2The difference between them.
Fig. 3A-4B are various diagrams of intermediate steps during processing of a wafer 70, according to some embodiments. Fig. 3A to 4B are sectional views in which a diagram ending with an "a" mark shows an overall view, and a diagram ending with a "B" mark shows a detailed view of a region R2 from the corresponding "a" view.
The wafer 70 includes a plurality of device regions 100A and 100B in which integrated circuit devices 50 are to be attached to form a plurality of devices. The devices formed in the wafer 70 may be interposers, integrated circuit dies, etc. Wafer 70 includes substrate 72, through-holes 74, and connectors 76.
The substrate 72 may be a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 72 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. The substrate 72 may be doped or undoped. In embodiments in which the interposer is formed in the wafer 70, the substrate 72 typically does not include active devices located therein, but the interposer may include passive devices formed in and/or on a front side (e.g., an upwardly facing surface) of the substrate 72. In embodiments in which integrated circuit dies are formed in wafer 70, devices such as transistors, capacitors, resistors, diodes, etc., may be formed in and/or on the front side of substrate 72.
The through-hole 74 is formed to extend from the front surface of the substrate 72 into the substrate 72. When the substrate 72 is a silicon substrate, the through-vias 74 are sometimes also referred to as through-substrate vias or through-silicon vias (TSVs). The through-holes 74 may be formed by forming grooves in the substrate 72, for example, by etching, milling, laser techniques, combinations thereof, and the like. A thin dielectric material may be formed in the recess, such as by using an oxidation technique. A thin barrier layer 74a may be conformally deposited over the frontside of substrate 72 and within the opening, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, and the like. Barrier layer 74a may be formed of an oxide, nitride, or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and the like. A conductive material 74b may be deposited over the barrier layer 74a and in the opening. The conductive material 74b may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive material 74b are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material 74b and barrier layer 74a are removed from the front side of substrate 72 by, for example, CMP. The through vias 74 collectively include a barrier layer 74a and a conductive material 74b, wherein the barrier layer 74a is located between the conductive material 74b and the substrate 72.
Interconnect structures are formed over the front side of substrate 72 and are used to electrically connect integrated circuit devices (if any) and/or through vias 74 together and/or to external devices. The interconnect structure may include a dielectric layer and a corresponding metallization pattern located in the dielectric layer. The metallization pattern may include vias and/or traces to interconnect any devices and/or through vias 74 together and/or to external devices. The dielectric layer may be made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, such as PSG, BPSG, FSG, SiOxCyLow K dielectric materials such as spin-on glass, spin-on polymers, silicon carbon materials, compounds thereof, composites thereof, combinations thereof, and the like. The dielectric layer may be deposited by any suitable method known in the art, such as spin-on coating, CVD, PECVD, HDP-CVD, and the like. For example, by makingMetallization patterns may be formed in each dielectric layer by depositing and patterning a photoresist material on the dielectric layer using photolithographic techniques to expose portions of the dielectric layer that will become the metallization patterns. An etching process, such as an anisotropic dry etching process, may be used to create recesses and/or openings in the dielectric layer corresponding to the exposed portions of the dielectric layer. The recesses and/or openings may be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier layer may be formed of one or more layers of TaN, Ta, TiN, Ti, CoW, etc., deposited by ALD, etc., and the conductive material may be formed of copper, aluminum, tungsten, silver, combinations thereof, etc., and may be deposited by CVD, PVD, etc. Any excess diffusion barrier and/or conductive material on the dielectric layer may be removed, such as by using CMP. Additionally, a connector 76, such as a conductive post or contact pad, is formed in and/or on the interconnect structure to provide external electrical connection to the through via 74 and the metallization pattern of the interconnect structure.
In fig. 3A and 3B, a photosensitive adhesive film 78 is formed on the front surface of the substrate 72. Photosensitive adhesive film 78 may be formed of a material similar to that of photosensitive adhesive film 56, and may be formed by a method similar to that used to form photosensitive adhesive film 56. After formation, the photosensitive adhesive film 78 may be exposed for patterning. The pattern of photosensitive adhesive film 78 corresponds to connector 76. The patterning forms a pattern of openings 80 through photosensitive adhesive film 78, exposing portions of connectors 76. Width W of each opening 802May be less than the width of the connector 76, such as width W2From about 1 μm to about 40 μm. Width W2Or may be greater than or equal to the width of the connector 76. The formed photosensitive adhesive film 78 has a thickness T of from about 1 μm to about 5 μm3. The depth of the opening 80 is equal to the thickness T3. In some embodiments, photosensitive adhesive film 78 is not cured immediately after formation, but rather is cured after subsequent processing steps are performed (see, e.g., fig. 6A and 6B).
In fig. 4A and 4B, a conductive layer 82 is formed in the opening 80 located on the connection member 76. Conductive layer 82 may be formed of a material similar to that of conductive layer 60, and may be formed by a method similar to that used to form conductive layer 60. A reflowable layer 84 is then formed over the conductive layer 82 in the opening 80. The reflowable layer 84 may be formed of a material similar to that of the reflowable layer 62, and may be formed by a method similar to that used to form the reflowable layer 62.
Conductive layer 82 and reflowable layer 84 have a combined thickness T from about 1 μm to about 5 μm4. Thickness T4Less than thickness T3. In this way, the top surface of photosensitive adhesive film 78 extends above the top surface of reflowable layer 84. Form a gap G2Wherein, the gap G2Is equal to the thickness T3And T4The difference between them.
According to some embodiments, an integrated circuit device package is formed by bonding the integrated circuit device 50 to the front side of the wafer 70. Prior to bonding, the integrated circuit device 50 and the wafer 70 may be processed according to the processes described above. Various integrated circuit device packages may be formed using such devices.
Fig. 5A-18 are various diagrams of intermediate steps during a process for forming a device package 200, according to some embodiments. In fig. 5A to 11, an intermediate package 100 is formed by bonding the integrated circuit device 50 to the front side of the wafer 70. The intermediate package 100 is divided. In fig. 12-18, further processing is performed to form a device package 200. In an embodiment, the device package 200 is a chip on wafer (CoW) package, but it should be understood that the embodiment may be applied to other 3DIC packages. Fig. 19 is a diagram of a device package 300 according to some embodiments. Fig. 5A to 19 are sectional views in which a figure ending with an "a" mark shows an overall view, and a figure ending with a "B" mark shows a region R from the corresponding "a" view3Detailed description of the drawings. In particular, the region R3The formation of a conductive connection 102 (shown in fig. 6B) is shown, wherein the conductive connection 102 connects the connection 54 of the integrated circuit device 50 to the connection 76 of the wafer 70.
In fig. 5A and 5B, a plurality of integrated circuit devices 50 are attached to a wafer 70. The integrated circuit device 50 is located in the device regions 100A and 100B, wherein the device regions 100A and 100B are to be divided in a subsequent step to form the intermediate package 100. The integrated circuit devices 50 may be attached to the wafer 70 using, for example, a pick and place tool.
The integrated circuit device 50 is attached to the wafer 70 by surface-to-surface bonding. Integrated circuit device 50 is pressed against wafer 70 such that photosensitive adhesive films 56 and 78 adhere to each other. In embodiments where photosensitive adhesive film 78 is not cured immediately after formation, photosensitive adhesive films 56 and 78 share a cured-uncured bonding interface when adhered, where photosensitive adhesive film 56 is cured and photosensitive adhesive film 78 is uncured. Uncured photosensitive adhesive film 78 may better conform to the shape of cured photosensitive adhesive film 56 during placement. When the photosensitive adhesive films 56 and 78 are pressed together, they mix and form polymer bonds, thereby becoming one continuous PSPL. The use of photosensitive adhesive films 56 and 78 allows integrated circuit device 50 to adhere to wafer 70 with fewer annealing and cleaning processes, thereby reducing manufacturing costs, as compared to other bonding techniques, such as hybrid bonding and fusion bonding.
After the integrated circuit device 50 is attached to the wafer 70, air gaps 104 are formed in the region between the reflowable layers 62 and 84. Thus, the integrated circuit devices 50 are physically connected to the wafer 70, but may not be electrically connected. The air gap 104 includes a gap G1And G2The defined area (shown in fig. 2B and 4B, respectively). The air gaps 104 each have two widths: a width W of the opening 581Defined by the width W of the opening 802And (4) limiting. The air gaps 104 also each have a gap G equal to1And G2Height H of the sum of the heights of1It is also equal to equation 1.
H1＝(T1+T3)-(T2+T4) (1)
In fig. 6A and 6B, a reflow process is performed to reshape the reflowable layers 62 and 84 into the conductive connection 102. The conductive connection 102 includes the material of the reflowable layers 62 and 84, and an intermetallic compound (IMC) may be formed at the interface of the conductive connection 102 and the conductive layers 60 and 82. During the reflow process, the material of the reflowable layers 62 and 84 may change shape due to the surface tension of the reflowed material. The new shapes of the reflowable layers 62 and 84 merge such that the reflowable layers 62 and 84 contact and form the conductive connection 102. An air gap 106 corresponding to gap G2 remains. An air gap 106 is formed around the upper portion of the conductive connection 102 and the lower portion of the conductive connection 102 is disposed between the air gap 106 and the connection 76. Forming the air gaps 106 forms buffer spaces between adjacent conductive connection members 102, thereby allowing the conductive connection members 102 to be formed at a finer pitch. In embodiments where photosensitive adhesive film 78 does not cure immediately after formation, heat from the reflow process may also cure photosensitive adhesive film 78.
In fig. 7, a sealant 108 is formed on each component. Encapsulant 108 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. An encapsulant 108 may be formed over the wafer 70 so as to bury or cover the integrated circuit devices 50. A sealant 108 is also formed on the photosensitive adhesive film 78. The encapsulant 108 is then cured. In some embodiments, encapsulant 108 is thinned such that encapsulant 108 is flush with the top surface of integrated circuit device 50.
In fig. 8, the substrate 72 is thinned to expose the through-holes 74 such that the through-holes 74 protrude from the back side of the substrate 72. The exposure of the through-holes 74 may be accomplished in a two-step thinning process. First, a grinding process may be performed until the through-hole 74 is exposed. The grinding process may be, for example, CMP or other acceptable removal process. After the grinding process, the backside of the substrate 72 is flush with the through-hole 74. Next, a recess process may be performed to recess the substrate 72 around the through-hole 74. The recess process may be, for example, a suitable etch back process. Portions of the conductive material 74b may also be removed during skiving.
In fig. 9, a conductive post 110 is formed on the protruding portion of the through-hole 74. The conductive pillars 110 may be formed by, for example, suitable photolithography and plating processes, and may be formed of copper, aluminum, tungsten, silver, combinations thereof, and the like. Then, on the back side of the substrate 72, an insulating layer 112 is formed around the protruding portion of the through-hole 74 and the conductive post 110. In some embodiments, the insulating layer 112 is formed of a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, PECVD, HDP-CVD, or the like. After deposition, a planarization process such as CMP may be performed to remove excess dielectric material so that the insulating layer 112 and the surfaces of the conductive pillars 110 are flush.
In some embodiments, the insulating layer 112 includes multiple layers. A first insulating layer may be formed on the backside of the substrate 72 around the protruding portion of the through-hole 74. The first insulating layer is patterned with an opening exposing the through-hole 74. A seed layer is formed on the first insulating layer and in the opening, and a photoresist is formed on the seed layer. The photoresist is patterned with openings corresponding to the pattern of the conductive pillars 110, and a plating process is performed, thereby forming the conductive pillars 110 in the openings. The exposed portions of the photoresist and seed layer are removed. A second insulating layer is then formed on the first insulating layer and around the conductive pillars 110.
In fig. 10, the wafer 70 is singulated between adjacent device regions 100A and 100B along scribe line regions 114 to form an intermediate package 100. The singulation may be performed by sawing, cutting, or the like.
Fig. 11 shows the intermediate package 100 after singulation. During the singulation process, an interposer 116 is formed, wherein the interposer 116 includes the wafer 70 and the singulated portions of the insulating layer 112. In some embodiments, interposer 116 has no active devices. In other embodiments, interposer 116 includes active devices. Each intermediate package 100 includes an interposer 116. The divided portions of photosensitive adhesive film 78 are formed on interposer 116. As a result of the singulation process, the edges of interposer 116, sealant 108, and photosensitive adhesive film 78 have a common boundary. In other words, the outer sidewalls of interposer 116 have the same width as the outer sidewalls of sealant 108 and photosensitive adhesive film 78.
In fig. 12, the singulated intermediate package 100 is adhered to a carrier substrate 118. The carrier substrate 118 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 118 may be a wafer such that multiple packages may be formed simultaneously on the carrier substrate 118. The carrier substrate 118 includes a plurality of device regions 200A and 200B, wherein the intermediate package 100 is attached by an adhesive 120.
The adhesive 120 is located on the backside of the intermediate package 100 and adheres the intermediate package 100 to the carrier substrate 118. The adhesive 120 may be any suitable adhesive, epoxy, Die Attach Film (DAF), or the like. The adhesive 120 may be applied to the backside of the intermediate package 100, such as to the backside of the respective encapsulant 108 or may be applied over the surface of the carrier substrate 118. The intermediate package 100 may be adhered to the carrier substrate 118 by the adhesive 120 using, for example, a pick and place tool.
In fig. 13, a sealant 122 is formed on each component. Encapsulant 122 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. An encapsulant 122 may be formed over the intermediate package 100 so as to bury or cover the conductive pillars 110. After curing, the encapsulant 122 may undergo a grinding process to expose the conductive pillars 110. The polishing process may also polish the insulating layer 112. After the grinding process, the top surfaces of the conductive pillars 110, insulating layer 112, and encapsulant 122 are coplanar. The grinding process may be, for example, Chemical Mechanical Polishing (CMP). In some embodiments, for example, if conductive pillars 110 have been exposed, grinding may be omitted.
In fig. 14, a redistribution structure 124 is formed over the encapsulant 122 and the intermediate package 100. The redistribution structure 124 includes a plurality of dielectric layers and metallization patterns. It should be understood that the illustration of redistribution structure 124 is schematic. For example, the redistribution structure 124 is actually patterned into a plurality of discrete portions separated from each other by respective dielectric layers. The redistribution structure 124 may be, for example, a redistribution layer (RDL), and may include metal traces (or metal lines) and vias located below and connected to the metal traces. As an example of forming the redistribution structure 124, each respective dielectric layer may be deposited, and an opening may be formed in the deposited dielectric layer. Metal traces and vias may be formed on the deposited dielectric layer and in the openings by, for example, acceptable photolithography and plating processes.
In fig. 15, conductive connections 126 are formed to connect to the redistribution structure 124. The conductive connections 126 may be formed on pads located on the outside of the redistribution structure 124. The pads may be formed as a metallization pattern in the contact redistribution structure 124 and may be referred to as Under Bump Metallization (UBM). The conductive connections 126 may be Ball Grid Array (BGA) connections, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. The conductive connection 126 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 126 is first formed by forming a solder layer by commonly used methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 126 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be free of solder and have substantially vertical sidewalls.
In fig. 16, carrier substrate debonding is performed to debond (debond) the carrier substrate 118 from the encapsulant 122 and the backside of the intermediate package 100. According to some embodiments, debonding includes projecting light, such as laser or UV light, onto the adhesive 120 such that the adhesive 120 decomposes under the heat of the light and the carrier substrate 118 may be removed.
In fig. 17, adjacent device regions 200A and 200B are separated along scribe line region 160 to form device package 200. The singulation may be performed by sawing, cutting, or the like. Fig. 18 shows the device package 200 obtained after the dicing.
In fig. 19, a device package 300 is formed by mounting the device package 200 to a package substrate 202. In an embodiment, the device package 300 is a chip on wafer on substrate (CoWoS) package, but it should be understood that embodiments may be applied to other 3DIC packages.
The package substrate 202 may be made of a semiconductor material such as silicon, germanium, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Additionally, the package substrate 202 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 202 is based on an insulating core such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin such as FR 4. Alternative materials for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. A build-up film such as ABF or other laminate may be used for the package substrate 202.
The package substrate 202 may include active devices and passive devices. One of ordinary skill in the art will recognize that a variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may result in structural and functional requirements for the design of device package 200. Any suitable method may be used to form the device. In some embodiments, the package substrate 202 is substantially free of active and passive devices.
The package substrate 202 may also include metallization layers and vias and bond pads over the metallization layers and vias. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material, and may be formed by any suitable process, such as deposition, damascene, dual damascene, and the like.
The conductive connectors 126 are reflowed to attach the device package 200 to the package substrate 202. The conductive connectors 126 electrically and physically connect the package substrate 202 (including the metallization layers in the package substrate 202) to the device package 200. An underfill 204 may be formed between the device package 200 and the package substrate 202 around the conductive connectors 126. The underfill 204 may be formed by a capillary flow process after the device package 200 is attached, or may be formed by a suitable deposition method before the device package 200 is attached.
In some embodiments, conductive connections 206 are formed on package substrate 202 on a side opposite conductive connections 126. The conductive connector 206 may be, for example, a BGA connector and may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof.
It should be understood that the device package 300 may be formed with other variations. Fig. 20 illustrates a device package 300 according to some other embodiments. Fig. 21 illustrates a device package 300 according to other embodiments.
In the embodiment of fig. 20, the intermediate package 100 is not singulated and adhered to the carrier substrate 118. Instead, after exposing the through vias 74, redistribution structures 124 are formed on the wafer 70. The conductive posts 110, insulating layer 112, and encapsulant 122 may be omitted and the redistribution structure 124 may be formed directly on the wafer 70, e.g., the bottom dielectric layer of the redistribution structure 124 may physically contact the substrate 72. The wafer 70 and the redistribution structure 124 are then simultaneously singulated to form the device packages 200.
In the embodiment of fig. 21, the intermediate package 100 is formed to include a plurality of stacked integrated circuit devices 50, such as first and second integrated circuit devices 50A and 50B. For example, the first integrated circuit device 50A may be formed to include the connectors 54 on both sides, and the through-holes 64 may be formed between the connectors 54. Photosensitive adhesive film 56 may be formed on both sides of first integrated circuit device 50A. The second integrated circuit device 50B may include a connector 132 and a photosensitive adhesive film 134, and may be adhered to the first integrated circuit device 50A. An additional conductive connection 136 is formed between connections 54 and 132 with an air gap 138. More or fewer integrated circuit devices 50 may be stacked in the intermediate package 100.
Additional processes for forming a device package will now be described in accordance with some embodiments. Some components of subsequent processes and devices may be formed in a similar manner to similarly-named components discussed above. Accordingly, the details of formation are not repeated here.
Fig. 22-33 are various diagrams of intermediate steps during a process for forming a device package 500, according to some embodiments. In the following description of the embodiments, the same reference numerals are usedThe same reference numerals are indicated from the previously described embodiments. In fig. 22-27, an intermediate package 400 is formed by bonding the integrated circuit device 50 to the front side of the wafer 70. The intermediate package 400 is divided. In fig. 28-33, further processing is performed to form a device package 500. FIGS. 22-33 are cross-sectional views, wherein the figure ending with the "A" mark shows the overall view, and the figure ending with the "B" mark shows the region R from the corresponding "A" view4Detailed description of the drawings.
In fig. 22, photosensitive adhesive film 78 is patterned to form openings 402, thereby exposing some of connectors 76. The opening 402 may be patterned simultaneously with the patterning of the opening 80. Openings 80 and 402 may be the same size or may be different sizes.
In fig. 23A and 23B, a conductive layer 82 is formed in the opening 80 located on the connection member 76. A reflowable layer 84 is then formed over the conductive layer 82 in the opening 80. The conductive layer 82 and the reflowable layer 84 are formed in the opening 80 and are not formed in the opening 402.
In fig. 24, a through hole 404 is formed. As an example of forming the through-hole 404, a seed layer is formed over the photosensitive adhesive film 78 and in the opening 402. In some embodiments, the seed layer is a metal layer, wherein the metal layer may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. For example, the seed layer may be formed using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Portions of the photoresist and seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etch process (such as by wet or dry etching). The remaining portions of the seed layer and the conductive material form through vias 404. The through vias 404 may be formed symmetrically or asymmetrically around each integrated circuit device 50.
In fig. 25A and 25B, a plurality of integrated circuit devices 50 are attached to a wafer 70. Prior to attachment, the integrated circuit device 50 may be processed as described herein. For example, the connections 54 are formed on the active side of the integrated circuit device 50, and vias 64 may be formed in the integrated circuit device 50. A photosensitive adhesive film 56 is formed on the integrated circuit device 50 and patterned. Integrated circuit device 50 is then bonded to wafer 70 in a face-to-face manner using photosensitive adhesive films 56 and 78 as an adhesive, and a reflow process is performed to form conductive connections 102 surrounded by air gaps 106.
In fig. 26, the wafer 70 is singulated between adjacent device regions 400A and 400B along scribe line regions 406 to form an intermediate package 400. The singulation may be performed by sawing, cutting, or the like. Fig. 27 shows the intermediate package 400 after singulation.
In fig. 28, the singulated intermediate package 400 is adhered to a carrier substrate 408. The carrier substrate 408 may be similar to the carrier substrate 118. The carrier substrate 408 includes a plurality of device regions 500A and 500B, wherein the intermediate package 400 is attached by an adhesive 410. An adhesive 410 is located on the backside of the middle package 400.
In fig. 29, a sealant 412 is formed on each component. Encapsulant 412 may be similar to encapsulant 122. A sealant 412 may be formed over the intermediate package 400 so as to bury or cover the through-hole 404. After curing, encapsulant 412 may be subjected to a grinding process to expose through vias 64 and 404. After the grinding process, the top surfaces of the through holes 64 and 404 and the sealant 412 are coplanar.
In fig. 30, redistribution structures 414 are formed on encapsulant 412 and intermediate package 100. Redistribution structure 414 may be similar to redistribution structure 124. Conductive connections 416 are then formed to the redistribution structure 414. The conductive connection 416 may be similar to the conductive connection 126.
In fig. 31, carrier substrate debonding is performed to debond (debond) the carrier substrate 408 from the encapsulant 412 and the backside of the intermediate package 400.
In fig. 32, adjacent device regions 500A and 500B are separated along scribe line regions 418 to form a device package 500. The singulation may be performed by sawing, cutting, or the like. Fig. 33 shows the device package 500 obtained after the dicing.
It should be understood that the device package 500 may be formed with other variations. Fig. 34 illustrates a device package 500 according to some other embodiments. Fig. 35 illustrates a device package 500 according to other embodiments. Fig. 36 illustrates a device package 500 according to other embodiments.
In the embodiment of fig. 34, the intermediate package 400 is not singulated and adhered to the carrier substrate 408. Instead, the encapsulant 412 is formed directly on the wafer 70 after the integrated circuit devices 50 are attached. Encapsulant 412 may bury integrated circuit device 50. The integrated circuit device 50 and encapsulant 412 are then planarized and redistribution structures 414 are formed on the integrated circuit device 50 and encapsulant 412. The wafer 70 and redistribution structures 414 are then singulated simultaneously to form the device packages 500.
The embodiment of fig. 35 is similar to the embodiment of fig. 34, but with the intermediate package 400 placed on the dielectric layer 420 and the intermediate package 400 sealed in the encapsulant 412. A through hole 422 may be formed adjacent to the middle package 400 through the sealant 412. Redistribution structures 414 are formed on the intermediate package 400 and the through-holes 420. An opening 424 is formed in dielectric layer 420, exposing through via 422.
The embodiment of fig. 36 is similar to the embodiment of fig. 34 except that an intermediate package 400 is formed to include a plurality of stacked integrated circuit devices 50, such as first and second integrated circuit devices 50A and 50B. Similar to other embodiments described herein, through vias 64 may be formed in some stacked integrated circuit devices 50.
Fig. 37-46 are various diagrams of intermediate steps during a process for forming a device package 600, according to some embodiments. In an embodiment, device package 600 is an integrated fan out (InFO) package, but should not beIt is understood that embodiments may be applied to other 3DIC packages. FIGS. 37-46 are cross-sectional views, wherein the figure ending with the "A" label shows the overall view, and the figure ending with the "B" label shows the region R from the corresponding "A" view5Detailed description of the drawings.
In fig. 37, a carrier substrate 602 is provided and a backside redistribution structure 604 is formed on the carrier substrate 602. The backside redistribution structure 604 includes a plurality of dielectric layers and metallization patterns. The back side redistribution structure 604 may be formed in a similar manner as the back side redistribution structure 124.
In fig. 38, through-holes 606 are formed on the back side redistribution structure 604. The through-holes 606 may be similar to the through-holes 404.
In fig. 39, an integrated circuit die 608 is adhered to the backside redistribution layer 604 by an adhesive 610. In other embodiments, a plurality of integrated circuit dies 608 can be adhered to the back side redistribution structure 604. Die connections 612, such as conductive pillars (e.g., comprising a metal such as copper), are located on the active side of the integrated circuit die 608, and a dielectric material 614 is located on the active side of the integrated circuit die 608, around the die connections 612.
In fig. 40, an encapsulant 616 is formed over and around the through vias 606 and the integrated circuit die 608. Encapsulant 616 may be similar to encapsulant 122. The encapsulant 616 may be planarized such that the through-holes 606, die attach 612, dielectric material 614, and the top surface of the encapsulant 616 are flush.
In fig. 41, a front side redistribution structure 618 is formed over the through vias 606, integrated circuit die 608, and encapsulant 616. The front side redistribution structure 618 includes a plurality of dielectric layers 620 and metallization patterns 622. The topmost layer of front-side redistribution structure 618 is a photosensitive adhesive film 624, and is formed on the topmost metallization pattern 622. Photosensitive adhesive film 624 is patterned to form openings 626, exposing metallization pattern 622.
In fig. 42A and 42B, a conductive layer 82 is formed in an opening 626 located over the metallization pattern 622. A reflowable layer 84 is then formed over the conductive layer 82 in the openings 626. In other embodiments, conductive layer 82 and reflowable layer 84 may be formed at this location.
In fig. 43A and 43B, the integrated circuit device 50 is attached to the front side redistribution structure 618. Prior to attachment, the integrated circuit device 50 may be processed as described herein; for example, the integrated circuit device may be a processor, a memory, or the like. For example, the connection 54 is formed on the active side of the integrated circuit device 50. A photosensitive adhesive film 56 is formed on the integrated circuit device 50 and patterned. Integrated circuit device 50 is pressed against front-side redistribution structure 618, thereby causing photosensitive adhesive films 56 and 624 to adhere to one another. An air gap 104 is thus formed between the reflowable layers 62 and 84.
In fig. 44A and 44B, a reflow process is performed to reflow the reflowable layers 62 and 84 to form the conductive connection 102. An air gap 106 is formed around the conductive connection 102.
In fig. 45, carrier substrate debonding is performed to debond (debond) the carrier substrate 602 from the backside redistribution structure 604.
In fig. 46, conductive connections 628 are formed to connect to the backside redistribution structure 604. Openings may be formed in the backside of the backside redistribution structure 604, exposing the metallization pattern of the backside redistribution structure 604. Conductive connections 628 are then formed in the openings.
Fig. 47-57 are various diagrams of intermediate steps during a process for forming a device package 700, according to some embodiments. In an embodiment, the device package 700 is a multi-stack (MUST) package, but it should be understood that embodiments may be applied to other 3DIC packages. FIGS. 47-57 are cross-sectional views, with the figure ending with an "A" label showing the overall view, and the figure ending with a "B" label showing the region R from the corresponding "A" view6Detailed description of the drawings.
In fig. 47, a carrier substrate 702 is provided and an integrated circuit die 704 is adhered to the carrier substrate 702 by an adhesive 706. Die connections 708, such as conductive pillars (e.g., comprising a metal such as copper), are located on the active side of the integrated circuit die 704, and a dielectric material 710 is located on the active side of the integrated circuit die 704 around the die connections 708.
In fig. 48, an encapsulant 712 is formed over and around integrated circuit die 704. Encapsulant 712 may be planarized such that the top surfaces of die attach 708, dielectric material 710, and encapsulant 712 are flush.
In fig. 49, a photosensitive adhesive film 714 is formed over the integrated circuit die 704 and encapsulant 712. Photosensitive adhesive film 714 is patterned to form openings 716 and 718, exposing die connectors 708. Openings 716 and 718 are located in different areas of integrated circuit die 704.
In fig. 50A and 50B, conductive layer 82 is formed in opening 716 located over die attach 708. A reflowable layer 84 is then formed over the conductive layer 82 in the opening 716. The conductive layer 82 and the reflowable layer 84 are not formed in the opening 718.
In fig. 51, a through hole 720 is formed in the photosensitive adhesive film 714. Through-hole 720 may be similar to through-hole 404.
In fig. 52A and 52B, an integrated circuit device 50 is attached to a photosensitive adhesive film 714. Prior to attachment, the integrated circuit device 50 may be processed as described herein. For example, the connection 54 is formed on the active side of the integrated circuit device 50. A photosensitive adhesive film 56 is formed on the integrated circuit device 50 and patterned. Integrated circuit device 50 is pressed against photosensitive adhesive film 714 so that photosensitive adhesive films 56 and 714 adhere to each other. An air gap 104 is thus formed between the reflowable layers 62 and 84.
In fig. 53A and 53B, a reflow process is performed to reflow the reflowable layers 62 and 84, thereby forming the conductive connection 102. An air gap 106 is formed around the conductive connection 102.
In fig. 54, a sealant 722 is formed on the photosensitive adhesive film 714 and around the integrated circuit device 50 and the through-hole 720. The encapsulant 722 may be planarized such that the integrated circuit device 50, the through via 720, and the top surface of the encapsulant 722 are flush.
In fig. 55, a front side redistribution structure 724 is formed on the through via 720, the integrated circuit device 50, and the encapsulant 722. The front side redistribution structure 724 includes a plurality of dielectric layers and metallization patterns.
In fig. 56, carrier substrate debonding is performed to debond (debond) the carrier substrate 702 from the integrated circuit die 704 and the encapsulant 712.
In fig. 57, conductive connections 726 are formed to connect to the front side redistribution structures 724. Openings may be formed in the front side of the front side redistribution structure 724 exposing the metallization pattern of the front side redistribution structure 724. Conductive connections 726 are then formed in the openings.
It should be understood that the conductive connection 102 may be formed in other ways. Fig. 58A-58F illustrate a process for forming the conductive connection 102 according to some other embodiments. Fig. 59A-59K illustrate processes for forming conductive connections 102 according to other embodiments. Fig. 60A-60F illustrate processes for forming conductive connections 102 according to other embodiments. The conductive connection 102 formed according to the subsequent description may be used in any of the above-described embodiments.
In the embodiment of fig. 58A to 58F, a seed layer 802 is formed in the opening 80 of the photosensitive adhesive film 78. A photoresist 804 is formed on photosensitive adhesive film 78 and patterned with openings exposing connectors 76. Conductive layer 82 and reflowable layer 84 are formed in openings in photoresist 804 over connectors 76. Thus, conductive layer 82 extends along the sides of opening 80. The photoresist 804 is removed and excess material of the conductive layer 82 and the reflowable layer 84 outside the opening 80 is removed by, for example, a CMP process. This process may be repeated in opening 58 of photosensitive adhesive film 56. Subsequently, as described above in fig. 5A to 6B, the photosensitive adhesive films 56 and 78 are bonded, and the reflowable layers 62 and 84 are reflowed.
In the embodiment of fig. 59A to 59K, a seed layer 902 is formed in the opening 58 of the photosensitive adhesive film 56. A photoresist 904 is then formed on the seed layer 902. Photoresist 904 extends along photosensitive adhesive film 56 and portions are formed in openings 58. Photoresist 904 is patterned with an opening that exposes a portion of seed layer 902 on connection 54. The seed layer 902 is used in the plating process for forming the conductive layer 60, and in the plating process for forming the reflowable layer 62. The combined thickness T of the seed layer 902, the conductive layer 60, and the reflowable layer 625May be greater than the thickness T of the photosensitive adhesive film 561. In forming the conductive layer 60 and the reflowable layer 62The photoresist 904 and the exposed portions of the seed layer 902 are then removed. Notably, the width of reflowable layer 62 is less than the width of opening 58, and thus exposes portions of connectors 54 when photoresist 904 in opening 58 is removed.
A photoresist 906 is formed on the substrate 72 and patterned with openings that expose the connections 76. A metal etching process, such as a dry etch or a wet etch, is performed to form an opening 908 in the connection 76. Conductive layer 82 and reflowable layer 84 are then formed in opening 908. The combined thickness of conductive layer 82 and reflowable layer 84 may be greater than or less than the depth of opening 908, but does not extend above the top surface of subsequently formed photosensitive adhesive film 78. In the illustrated embodiment, the conductive layer 82 and the reflowable layer 84 are plated in the openings 908 by an electroless plating process, but it is understood that the seed layer may be formed in other plating processes. Photoresist 906 is then removed and photosensitive adhesive film 78 is formed and patterned with openings that expose conductive layer 82.
The integrated circuit device 50 is then attached to the wafer 70. Due to the thickness T of the seed layer 902, the conductive layer 60, and the reflowable layer 625(see fig. 59E), reflowable layer 62 extends into openings 58 in photosensitive adhesive film 56. In an embodiment, integrated circuit device 50 is attached after curing photosensitive adhesive film 56 but before curing photosensitive adhesive film 78. As described above with reference to fig. 5A-6B, a reflow process is performed to form the conductive connection 102 surrounded by the air gap 106. The reflow process may also cure photosensitive adhesive film 78, thereby bonding photosensitive adhesive films 56 and 78 together.
In the embodiment of fig. 60A-60F, a seed layer 952 is formed on the front side of the integrated circuit device 50. A photoresist 954 is then formed on the seed layer 952. Photoresist 954 is patterned with openings that expose portions of seed layer 952 on connections 54. Seed layer 952 is used in the plating process used to form conductive layer 60, and in the plating process used to form reflowable layer 62. After conductive layer 60 and reflowable layer 62 are formed, exposed portions of photoresist 954 and seed layer 952 are removed. Then, a photosensitive adhesive film 56 is formed on the substrate 52, and particularly, a reflowable layer 62 is formed over the photosensitive adhesive filmPhotosensitive adhesive film 56. Openings 58 are then formed in photosensitive adhesive film 56, exposing conductive layer 60 and reflowable layer 62. Notably, the width of reflowable layer 62 is less than the width of opening 58, and portions of connectors 54 are exposed when opening 58 is formed. The combined thickness T of seed layer 952, conductive layer 60, and reflowable layer 626May be greater than the thickness T of the photosensitive adhesive film 561。
The integrated circuit device 50 is then attached to the wafer 70. Similar to the embodiments described above, openings may be formed in the connection 76 of the wafer 70. Due to the thickness T of the seed layer 952, the conductive layer 60, and the reflowable layer 626 Reflowable layer 62 extends into openings 58 in photosensitive adhesive film 56. In the illustrated embodiment, the conductive layer 82 and the reflowable layer 84 are plated in openings formed in the connection 76. In an embodiment, integrated circuit device 50 is attached after curing photosensitive adhesive film 56 but before curing photosensitive adhesive film 78. Photosensitive adhesive film 78 is then cured, thereby adhering photosensitive adhesive films 56 and 78 together. As described above with reference to fig. 5A-6B, a reflow process is performed to form the conductive connection 102 surrounded by the air gap 106.
Fig. 61A-61B illustrate a process for forming a conductive connection 102 according to some other embodiments. Fig. 61B is a top view of the structure of fig. 61A. In the illustrated embodiment, photosensitive adhesive films 56 and 78 are patterned such that they are formed only around the perimeter of integrated circuit device 50. As such, after bonding and reflow, cavities 1002 are formed, wherein each conductive connection 102 is exposed to the cavities 1002. The cavity 1002 may be formed with an opening 1004 around the perimeter to provide an air movement path. The opening 1004 may have a width from about 5 μm to about 50 μm. In some embodiments, the opening 1004 may be formed with a bend in a top view to prevent the encapsulant 108 from flowing into the cavity 1002.
