阅读说明：本技术 功率放大电路 (Power amplifying circuit ) 是由 浪江寿典 于 2019-05-27 设计创作，主要内容包括：本发明提供一种能够抑制增益特性的频率偏差的功率放大电路。功率放大电路具备：第一晶体管,基极或栅极与信号线路连接,发射极或源极通过第一导电体接地,将从信号线路供给到基极或栅极的输入信号放大,并从集电极或漏极输出放大信号；第一元件,在第一晶体管的前级,一端与信号线路连接,使得从信号线路分岔,另一端通过第二导电体接地；以及第一电容器,一端连接于第一晶体管的发射极或源极与第一导电体的连接点,另一端连接于第一元件与第二导电体的连接点。(The invention provides a power amplifier circuit capable of suppressing frequency deviation of gain characteristics. The power amplifier circuit includes: a first transistor having a base or a gate connected to a signal line, an emitter or a source grounded via a first conductor, amplifying an input signal supplied from the signal line to the base or the gate, and outputting the amplified signal from a collector or a drain; a first element having one end connected to the signal line at a preceding stage of the first transistor so as to branch from the signal line and the other end grounded via a second conductor; and a first capacitor having one end connected to a connection point between the emitter or source of the first transistor and the first conductor and the other end connected to a connection point between the first element and the second conductor.)

1. A power amplification circuit is provided with:

a first transistor having a base or a gate connected to a signal line, an emitter or a source grounded via a first conductor, amplifying an input signal supplied from the signal line to the base or the gate, and outputting an amplified signal from a collector or a drain;

a first element having one end connected to the signal line at a preceding stage of the first transistor so as to branch from the signal line and the other end grounded via a second conductor; and

and a first capacitor having one end connected to a connection point between the emitter or source of the first transistor and the first conductor and the other end connected to a connection point between the first element and the second conductor.

2. The power amplification circuit of claim 1,

the first electrical conductor includes: a bump electrically connecting an emitter or a source of the first transistor to a ground provided on a substrate,

the second electrical conductor includes: and a bump electrically connecting the other end of the first element to the ground portion.

3. The power amplification circuit of claim 1,

the first electrical conductor includes: a via electrically connecting an emitter or a source of the first transistor to a ground provided on a substrate,

the second electrical conductor includes: a via hole electrically connecting the other end of the first element to the ground portion.

4. The power amplification circuit of any one of claims 1 to 3,

the first transistor further includes, at a stage preceding the first transistor: a second capacitor and a third capacitor connected in series with the signal line,

the first element comprises: and one end of the inductor is connected to the connection point of the first capacitor and the second capacitor.

5. The power amplification circuit of any one of claims 1 to 4,

further provided with: and a second transistor disposed at a subsequent stage of the first transistor.

Technical Field

The present invention relates to a power amplifier circuit.

Background

A mobile communication device such as a mobile phone is equipped with a power amplifier circuit using a transistor. In such a power amplifier circuit, a matching circuit for matching impedance is often provided between the input terminal and the amplifier, or between the amplifier and the amplifier. For example, patent document 1 discloses a matching circuit including two capacitors connected in series and an inductor connected between the two capacitors and a ground.

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication (JP 2015-46858)

In such a power amplification circuit, it is desirable that the gain is constant regardless of the frequency of the amplified signal. However, in the power amplifier circuit disclosed in patent document 1, for example, in a signal of a relatively high frequency band of the GHz band, there is a problem that variation in gain characteristics may occur due to a difference in frequency.

Disclosure of Invention

Problems to be solved by the invention

The present invention has been made in view of such circumstances, and an object thereof is to provide a power amplifier circuit capable of suppressing frequency deviation of gain characteristics.

Means for solving the problems

To achieve the above object, a power amplifier circuit according to one aspect of the present invention includes: a first transistor having a base or a gate connected to a signal line, an emitter or a source grounded via a first conductor, amplifying an input signal supplied from the signal line to the base or the gate, and outputting the amplified signal from a collector or a drain; a first element having one end connected to the signal line at a preceding stage of the first transistor so as to branch from the signal line and the other end grounded via a second conductor; and a first capacitor having one end connected to a connection point between the emitter or source of the first transistor and the first conductor and the other end connected to a connection point between the first element and the second conductor.

Effects of the invention

According to the present invention, a power amplifier circuit capable of suppressing frequency deviation of gain characteristics can be provided.

Drawings

Fig. 1 is a diagram showing a configuration example of a power amplifier circuit according to an embodiment of the present invention.

Fig. 2 is a graph showing simulation results of frequency characteristics of gains in the power amplification circuits according to the present embodiment and comparative example.

Fig. 3 is a graph showing simulation results of P2dB in the power amplifier circuits according to the present embodiment and the comparative example.

Fig. 4 is a graph showing the capacitance value of the capacitor C1 versus gain.

Fig. 5 is a graph showing the relationship between the impedance value and the gain in the case where the capacitor C1 is expressed by the impedance.

Fig. 6 is a graph showing simulation results of frequency characteristics of gain in the power amplifier circuit including the via hole and the power amplifier circuit according to the comparative example.

Description of the reference numerals

100: power amplifier circuit, 10, 11: amplifier, 20, 21: matching circuit, 30, 31: bias circuit, 40: semiconductor chip, Tr1, Tr 2: transistors, C1-C3: a capacitor, LI: inductor, T1: input terminals, T2, T3: power supply terminals, B1 to B3: and (4) a bump.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same elements are denoted by the same reference numerals, and redundant description thereof is omitted.

Fig. 1 is a diagram showing a configuration example of a power amplifier circuit according to an embodiment of the present invention. The power amplifier circuit 100 shown in fig. 1 is mounted in a mobile communication device such as a mobile phone, for example, and amplifies power of a Radio-Frequency (RF) signal transmitted to a base station. The power amplifier circuit 100 amplifies a transmission signal of a communication standard such as 2G (second generation mobile communication system), 3G (third generation mobile communication system), 4G (fourth generation mobile communication system), 5G (fifth generation mobile communication system), LTE (long term Evolution) -FDD (Frequency Division Duplex), LTE-TDD (time Division Duplex), LTE-Advanced, and LTE-Advanced Pro. The frequency of the RF signal is, for example, in the range of several hundred MHz to several tens GHz. The communication standard and frequency of the signal amplified by the power amplifier circuit 100 are not limited to these.

In the present embodiment, the power amplification circuit 100 includes, for example, amplifiers 10 and 11, matching circuits 20 and 21, bias circuits 30 and 31, a capacitor C1, and bumps B1 to B3.

The power amplification circuit 100 amplifies the power of an RF signal through two stages. Specifically, the amplifier 10 of the primary stage (driving stage) amplifies the input signal RFin input from the input terminal T1 via the signal line W1, and outputs an amplified signal RFout 1. The amplifier 11 of the subsequent stage (power stage) amplifies the amplified signal RFout1 output from the amplifier 10 of the primary stage and outputs an amplified signal RFout 2. In the present embodiment, the amplifiers 10 and 11 are respectively composed of transistors Tr1 and Tr2 such as Heterojunction Bipolar Transistors (HBTs). Instead of the HBT, the amplifiers 10 and 11 may be formed of a Field effect transistor (MOSFET) or a Metal-oxide-semiconductor Field-effect transistor. In this case, the collector, base, and emitter described below may be referred to as the drain, gate, and source, respectively.

In the transistor Tr1 (first transistor), the power supply voltage Vcc is supplied to the collector from the power supply terminal T2, the base is connected to the signal line W1 and the input signal RFin is supplied from the input terminal T1, and the emitter is grounded via the bump B1. A bias current or voltage is supplied from the bias circuit 30 to the base of the transistor Tr 1. Thus, the amplified signal RFout1 obtained by amplifying the input signal RFin is output from the collector of the transistor Tr 1. The gain of the transistor Tr1 may be controlled by a bias current or voltage supplied from the bias circuit 30.

In the transistor Tr2 (second transistor), the power supply voltage Vcc is supplied from the power supply terminal T3 to the collector, the amplified signal RFout1 is supplied from the collector of the transistor Tr1 via the matching circuit 21 to the base, and the emitter is grounded via the bump B2. A bias current or voltage is supplied from the bias circuit 31 to the base of the transistor Tr 2. Thus, the amplified signal RFout2 obtained by amplifying the amplified signal RFout1 is output from the collector of the transistor Tr 2. The gain of the transistor Tr2 may be controlled by a bias current or voltage supplied from the bias circuit 31.

A Matching circuit 20 (MN: Matching Network) is provided at a stage preceding the first-stage amplifier 10, and matches the impedance of a circuit (not shown) provided at the stage preceding the Matching circuit 20 with the impedance of the amplifier 10. The matching circuit 21 is provided between the first-stage amplifier 10 and the subsequent-stage amplifier 11, and matches the impedance of the amplifier 10 with the impedance of the amplifier 11.

In this embodiment, the matching circuit 20 is formed of a T-type filter circuit including two capacitors C2 and C3 and one inductor L1, as an example. Specifically, a capacitor C2 (second capacitor) and a capacitor C3 (third capacitor) are connected in series with the signal line W1 that supplies the input signal RFin. One end of an inductor L1 (first element) is connected to a connection point of the capacitor C2 and the capacitor C3, and the other end is grounded via a bump B3. That is, the inductor L1 is connected to the signal line W1 so as to branch from the signal line W1. The matching circuit 21 can have the same configuration as the matching circuit 20, and therefore, the description thereof is omitted.

In this embodiment mode, the transistors Tr1 and Tr2 and the matching circuits 20 and 21 are formed in the semiconductor chip 40 by the HBT process. The semiconductor chip 40 is mounted on a substrate (not shown) by a so-called flip chip structure. At this time, the emitter of the transistor Tr1, the emitter of the transistor Tr2, and the other end of the inductor L1 in the matching circuit 20 are electrically connected to a ground provided on a substrate (not shown) through bumps B1 to B3, respectively. That is, the bumps B1 and B3 are specific examples of a first conductor and a second conductor for electrically connecting the emitter of the transistor Tr1 and the other end of the inductor L1 to the ground of the substrate, respectively. The ground portion of the substrate is an electrode to which a reference potential (for example, a ground potential) is supplied, among the electrodes formed on the substrate. Fig. 1 shows a simulation in which the bumps B1 to B3 and the wirings, vias, and the like on the semiconductor chip 40 up to the bumps B1 to B3 have inductance components. The structure of the bump is not particularly limited, and may be, for example, a copper pillar bump.

One end of the capacitor C1 (first capacitor) is connected to the emitter of the transistor Tr1 (i.e., the connection point of the emitter of the transistor Tr1 and the bump B1), and the other end is connected to the other end of the inductor L1 included in the matching circuit 20 (i.e., the connection point of the inductor L1 and the bump B3). The capacitor C1 is formed in the semiconductor chip 40, for example, and has a function of feeding back a signal from the emitter to the base of the transistor Tr 1. Specifically, a part of the amplified signal RFout1 flowing through the emitter of the transistor Tr1 is fed back to the base of the transistor Tr1 via the capacitor C1, the inductor L1, and the capacitor C3 in this order. This achieves the following effects.

That is, if it is assumed that the power amplification circuit 100 does not include the capacitor C1, for example, the gain decreases with an increase in the frequency of the input signal RFin, and thus there is a possibility that a frequency deviation of the gain characteristic occurs. In this regard, according to the present embodiment, a signal is fed back from the emitter to the base of the transistor Tr1 via the capacitor C1. Thereby, a part of the amplified signal RFout1 is supplied again to the transistor Tr1 as an input signal. Therefore, even if the frequency of the input signal RFin increases, the decrease in gain can be suppressed, and as a result, the frequency deviation of the gain characteristic can be suppressed.

Further, by adjusting the capacitance value of the capacitor C1, the feedback amount in the transistor Tr1 can be adjusted to control the gain characteristic.

In the power amplification circuit 100, the capacitor C1 is provided in the first-stage amplifier 10, but the case where the element corresponding to the capacitor C1 is provided in the subsequent-stage amplifier 11 is not intended to be excluded. For example, an element corresponding to the capacitor C1 may be provided in the amplifier 11 at the subsequent stage in addition to the first stage, or an element corresponding to the capacitor C1 may be provided in the amplifier 11 at the subsequent stage instead of the first stage.

The power amplifier circuit is not limited to two stages, and may include three or more stages of amplifiers. When the power amplification circuit includes, for example, a three-stage amplifier, frequency deviation of the gain characteristic can be suppressed even if the capacitor C1 is not provided. However, in the case of the three-stage structure, the consumption current may increase as compared with the two-stage structure. That is, by adopting the two-stage configuration for the power amplification circuit 100, it is possible to suppress frequency deviation of the gain characteristic while avoiding an increase in the consumption current as compared with the three-stage configuration.

The matching circuit 20 is not limited to the C-L-C T-type filter circuit shown in fig. 1, and may be formed of, for example, an L-C-L T-type filter circuit, or a C-L-C or L-C-L pi-type filter circuit, instead of the C-L-C T-type filter circuit. When the matching circuit 20 is configured by these filter circuits, an element (for example, a capacitor in the case of an L-C-L T-filter circuit) connected so as to branch from the signal line W1 may be connected to the ground of the substrate via a bump, as in the case of the inductor L1 described above, and the other end of the capacitor C1 may be connected between the element and the bump.

Fig. 2 is a graph showing simulation results of frequency characteristics of gains in the power amplification circuits according to the present embodiment and comparative example. Specifically, the power amplifier circuit according to the present embodiment has a configuration in which, as shown in fig. 1, the capacitor C1 is provided in the amplifier 10 at the first stage and the capacitor C1 is not provided in the amplifier 11 at the subsequent stage. On the other hand, the power amplification circuit according to the comparative example has a configuration in which the capacitor C1 is not provided in both the first-stage amplifier and the subsequent-stage amplifier. In the present embodiment, the results are shown when the capacitance value of the capacitor C1 is 0.0pF (comparative example), 1.2pF, 1.6pF, and 2.4 pF. In the graph shown in the same figure, the horizontal axis shows the frequency (Hz) of the input signal, the vertical axis shows the gain (dB) of the power amplifier circuit, and 3.4GHz to 3.7GHz are defined as the frequency band of the signal to be amplified.

First, the gain of the power amplifier circuit according to the comparative example was about 32dB at 3.4GHz of the input signal, but decreased with an increase in the frequency of the input signal, and about 31dB at 3.7 GHz. That is, according to the power amplifier circuit of the comparative example, it is known that the gain varies within the frequency band, and the frequency of the gain characteristic varies. On the other hand, it is found that, in the power amplifier circuit 100, regardless of the capacitance value of the capacitor C1, the gain can be suppressed from decreasing due to the increase in frequency compared to the comparative example. The larger the capacitance value of the capacitor C1, the smaller the degree of gain reduction, and for example, when the capacitance value is 2.4pF, the gain is maintained at around 32dB even at 3.7 GHz. That is, it can be said that the power amplifier circuit 100 can suppress frequency deviation of gain characteristics as compared with the comparative example.

Fig. 3 is a graph showing simulation results of a 2dB gain compression point (so-called P2dB) in the power amplifier circuits according to the present embodiment and the comparative example. In the graph shown in the same figure, the horizontal axis shows frequency (Hz) and the vertical axis shows P2dB (dB). Fig. 3 shows the calculation results of the simulation in the case where the output power is large, as compared with the simulation shown in fig. 2.

As shown in fig. 3, in the power amplifier circuit according to the comparative example, P2dB is about 30.4dB at a frequency of 3.4GHz, but it is reduced to about 29dB at 3.7 GHz. On the other hand, according to the power amplifier circuit 100 of the present embodiment, the P2dB maintains 30.6dB at both frequencies of 3.4GHz and 3.6GHz, and falls slightly at 3.7GHz, but stays at 30 dB. Accordingly, it can be said that, according to the power amplifier circuit 100, even if the output power is relatively large, the frequency deviation of the gain characteristic can be suppressed as compared with the comparative example.

Further, as for the capacitance value of the capacitor C1, if it is too small, the feedback amount decreases and the effect of providing the capacitor C1 is reduced, but if it is too large, the feedback amount increases and there is a possibility that the transistor Tr1 oscillates. Therefore, the capacitance value of the capacitor C1 is preferably set within an appropriate range. This point will be described with reference to fig. 4 and 5.

Fig. 4 is a graph showing the capacitance value of the capacitor C1 versus gain. Specifically, the same figure shows the calculation results of the gain in the case where the frequency of the input signal RFin is set to 3.4GHz, 3.6GHz, and 3.7GHz, and the capacitance value of the capacitor C1 is set to 0.0pF (comparative example), 2.4pF, 3.9pF, and 5.4pF in the power amplification circuit 100. In the graph shown in the same figure, the horizontal axis shows the capacitance value (pF) of the capacitor C1, and the vertical axis shows the gain (dB).

As shown in fig. 4, as the capacitance value of capacitor C1 increases from 0.0pF, the gain also increases. However, if the capacitance value exceeds 4.0pF, the gain starts to decrease particularly at a frequency of 3.7GHz, for example. Therefore, the capacitance value of the capacitor C1 is preferably set to about 2.0pF to 4.0 pF.

Fig. 5 is a graph showing the relationship of the impedance value and the gain in the case where the capacitor C1 is expressed by the impedance in the simulation shown in fig. 4. The impedance value Z of the capacitor C1 is determined by Z1/2 pi fC (f: frequency, C: capacitance value). In the graph shown in fig. 5, the horizontal axis shows the impedance value (-j Ω) of the capacitor C1, and the vertical axis shows the gain (dB).

As shown in fig. 5, it is found that when the capacitor C1 is expressed by impedance, it is preferable that the gain characteristic be within a range of about 32dB to 34dB when the impedance value is about-10 j Ω to-20 j Ω.

In the above-described embodiment, the example in which the semiconductor chip 40 is mounted on the substrate by the flip chip structure has been described, but instead, the semiconductor chip 40 may be mounted on the substrate by a so-called wire bonding structure. In this case, the emitter of the transistor Tr1 and the other end of the inductor L1 may be electrically connected to the ground of the substrate through a via hole formed in the semiconductor substrate instead of the bumps B1 and B3, respectively. That is, these vias are also a specific example of the first conductor and the second conductor. Even with such a configuration, the same effects as those of the above-described embodiment are obtained.

Fig. 6 is a graph showing simulation results of frequency characteristics of gain in the power amplifier circuit including via holes instead of bumps B1 and B3 in the configuration of the power amplifier circuit 100 and the power amplifier circuit according to the comparative example. Specifically, fig. 6 shows the calculation results of the gain in the case where the frequency of the input signal RFin is set to 3.2GHz to 4.0GHz and the capacitance value of the capacitor C1 is set to 0.0pF (comparative example), 2.4pF, and 3.9 pF. In the graph shown in fig. 6, the horizontal axis shows frequency (GHz) and the vertical axis shows gain (dB).

As is clear from fig. 6, even in the wire bonding structure, the frequency deviation of the gain characteristic in the frequency band of 3.4GHz to 3.7GHz can be suppressed as compared with the power amplifier circuit according to the comparative example. The conductor connecting the emitter of the transistor Tr1 and the other end of the inductor L1 to the ground of the substrate is not limited to a bump or a via, and may be another conductive material such as a wire.

The exemplary embodiments of the present invention have been described above. The power amplifier circuit 100 includes: a transistor Tr1 having a base or a gate connected to the signal line W1, an emitter or a source grounded through a bump B1, amplifying an input signal RFin supplied from the signal line W1 to the base or the gate, and outputting an amplified signal RFout1 from a collector or a drain; an inductor L1 having one end connected to the signal line W1 at the front stage of the transistor Tr1 so as to branch from the signal line W1 and the other end grounded through a bump B3; and a capacitor C1 having one end connected to a connection point between the emitter or source of the transistor Tr1 and the bump B1 and the other end connected to a connection point between the inductor L1 and the bump B3. Thereby, a signal is fed back from the emitter of the transistor Tr1 to the base via the capacitor C1. Therefore, even if the frequency of the input signal RFin increases, the decrease in gain can be suppressed, and the frequency deviation of the gain characteristic can be suppressed.

In the power amplifier circuit 100, the emitter of the transistor Tr1 and the other end of the inductor L1 may be grounded through a via hole instead of the bumps B1 and B3.

In the power amplification circuit 100, the configuration of the matching circuit 20 is not particularly limited, and may include, for example, a capacitor C2 and a capacitor C3 connected in series to the signal line W1, and an inductor having one end connected to a connection point between the capacitor C2 and the capacitor C3.

The power amplifier circuit 100 includes a transistor Tr2 provided at a subsequent stage of the transistor Tr1, and the capacitor C1 is connected to the transistor Tr1, but an element corresponding to the capacitor C1 is not connected to the transistor Tr 2. This can suppress the influence of variations in phase or the like when the capacitor C1 is connected.

The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention can be modified or improved without departing from the gist thereof, and the present invention also includes equivalents thereof. That is, embodiments to which design changes are appropriately made by those skilled in the art to each embodiment as long as the features of the present invention are provided are also included in the scope of the present invention. For example, the elements and their arrangement, materials, conditions, shapes, sizes, and the like included in the embodiments are not limited to the illustrated elements and their arrangement, materials, conditions, shapes, sizes, and the like, and can be appropriately modified. Further, each element included in each embodiment can be combined as long as it is technically feasible, and embodiments combining them are also included in the scope of the present invention as long as they include the features of the present invention.