阅读说明：本技术 动态d触发器 (Dynamic D flip-flop ) 是由 刘杰尧 张楠赓 吴敬杰 马晟厚 于 2018-06-25 设计创作，主要内容包括：本发明提供一种在计算设备中应用的动态D触发器,一输入端、一输出端以及至少一时钟信号端；一第一锁存单元,用于传输所述输入端的数据并在时钟信号控制下锁存所述数据；一第二锁存单元,用于锁存所述输出端的数据并在时钟信号控制下将所述第一锁存单元锁存的所述数据反相传输；一输出驱动单元,用于反相并输出从所述第二锁存单元接收到的所述数据；所述第一锁存单元、所述第二锁存单元以及所述输出驱动单元依次串接在所述输入端和所述输出端之间；其中,所述第二锁存单元在时钟信号控制下通过单一元件实现高电平、低电平和高阻三种状态的输出。借此,本发明可以有效减小芯片面积,降低功耗、减小逻辑延时。(The invention provides a dynamic D trigger applied in computing equipment, which comprises an input end, an output end and at least one clock signal end, wherein the input end is connected with the output end of the dynamic D trigger; the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal; the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal; an output driving unit for inverting and outputting the data received from the second latch unit; the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end; the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal. Therefore, the invention can effectively reduce the area of the chip, reduce the power consumption and reduce the logic delay.)

1. A dynamic D flip-flop, comprising:

an input terminal, an output terminal and at least one clock signal terminal;

the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal;

the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal;

an output driving unit for inverting and outputting the data received from the second latch unit;

the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal.

2. The dynamic D flip-flop of claim 1, wherein: the second latch unit is a tri-state inverter.

3. The dynamic D flip-flop of claim 2, wherein: the tri-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and the ground.

4. The dynamic D flip-flop of claim 3, wherein: and the first PMOS transistor and the second NMOS transistor are subjected to switch control according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are in opposite phases.

5. The dynamic D flip-flop of claim 3, wherein: and the second PMOS transistor and the first NMOS transistor are subjected to switch control according to clock signals, and the clock signals of the second PMOS transistor and the first NMOS transistor are in reverse phase.

6. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of dynamic D triggers which are connected in an interconnecting way, wherein the plurality of dynamic D triggers are connected in series and/or in parallel; the method is characterized in that: the plurality of dynamic D flip-flops are the dynamic D flip-flops of any one of claims 1-5.

7. A chip comprising a data arithmetic unit as claimed in any one of claim 6.

8. An algorithm board for a computing device comprising a plurality of the chips of any one of claim 7.

9. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force calculation board is the force calculation board as set forth in claim 8.

10. The computing device of claim 9, wherein: the computing device is for mining operations of virtual digital currency.

Technical Field

The present invention relates to a clocked memory device, and more particularly, to a dynamic D flip-flop applied in a computing device.

Background

Virtual currency (e.g., bitcoin, ethernet) is a digital currency in the form of P2P, which has received much attention since the 2009 bitcoin system. The system constructs the distributed shared general ledger based on the block chain, thereby ensuring the safety, reliability and decentralization of the system operation.

In hashing and proof of workload, bitcoin is the only correct hash value calculated to prove the workload to obtain accounting packed block right and thus the reward, which is proof of workload (Pow).

At present, no effective algorithm is available for hash operation except for brute force calculation. The bitcoin mining starts with low-cost hardware such as a CPU or a GPU, but with the prevalence of bitcoins, the mining process changes greatly. Today, excavation activities are transferred to Field Programmable Gate Arrays (FPGAs) or application specific chips (ASICs), which are very efficient in excavation mode.

The D trigger has wide application and can be used as a register of a digital signal, a shift register, a frequency division generator, a waveform generator and the like. The D flip-flop has two inputs, Data and Clock (CLK), with one output (Q), into or from which Data can be written or read.

CN1883116A discloses a positive feedback D flip-flop circuit 106 as shown in fig. 1, comprising an analog switch 300, an inverter 302, an analog switch 304, an inverter 306, an inverter 308, an analog switch 310, an inverter 312, and an analog switch 314. The analog switches 300, 304, 310, and 314 are analog switches using P-channel/N-channel transistors, and perform switching operations by CKP in phase with CK and CKN in phase opposite to CK. Inverters 302, 306, inverters 308, and 312 are CMOS inverters. It can be seen that a conventional D flip-flop basically needs 16 PMOS/NMOS transistors, which occupies a large area.

For a new generation of computing devices for mining virtual digital currency, the mining process is a logical computing pipeline that performs a large number of iterations, requiring several D-flip-flops to store data. Therefore, in a computing device requiring a large number of D flip-flops, the defects of increased chip area, slow operation speed and poor control of leakage can be caused.

CN1883116A also discloses a dynamic D flip-flop circuit 102 as shown in fig. 2, where the dynamic D flip-flop circuit 102 includes a 1 st analog switch 200, a 1 st inverter 202, a 2 nd analog switch 204, and a 2 nd inverter 206. The dynamic D flip-flop circuit 102 constitutes a sample-and-hold circuit by an analog switch of the 1 st analog switch 200 and the 2 nd analog switch 204, and a parasitic capacitance such as a gate capacitance and a wiring capacitance of the 1 st inverter 202 and the 2 nd inverter 206.

In the dynamic D flip-flop, the inverter 202 and the analog switch 204 are separately provided, and thus there are problems that the analog switch is not easily controlled and the access speed is slow.

Disclosure of Invention

In order to solve the above problems, the present invention provides a dynamic D flip-flop for a computing device, which can effectively reduce chip area, power consumption, and logic delay.

In order to achieve the above object, the present invention provides a dynamic D flip-flop, comprising:

an input terminal, an output terminal and at least one clock signal terminal;

the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal;

the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal;

an output driving unit for inverting and outputting the data received from the second latch unit;

the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal.

In the above dynamic D flip-flop, the second latch unit is a tri-state inverter.

In the above dynamic D flip-flop, the tri-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are sequentially connected in series between the power supply and the ground.

In the dynamic D flip-flop, the first PMOS transistor and the second NMOS transistor perform switching control according to a clock signal, and clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

In the dynamic D flip-flop, the second PMOS transistor and the first NMOS transistor perform switching control according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

By using the dynamic D trigger, the area of a chip can be reduced by nearly 30 percent, so that the production cost of the chip is reduced, and the product competitiveness is increased. In extension, the dynamic D flip-flop can replace a D flip-flop in digital logic, so that the area advantage is obtained.

In order to better achieve the above object, the present invention further provides a data operation unit, which includes a control circuit, an operation circuit, and a plurality of dynamic D flip-flops connected in series and/or in parallel; wherein the plurality of dynamic D flip-flops are any one of the dynamic D flip-flops.

In order to better achieve the above object, the present invention further provides a chip, which employs any one of the above data operation units.

In order to better achieve the above object, the present invention further provides a computing board for a computing device, which employs any one of the above chips.

In order to better achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards through the connecting board, the heat sink is disposed around the computing boards, and the power board is configured to provide power to the connecting board, the control board, the heat sink, and the computing boards are any one of the computing boards.

Preferably, the computing device is for operations to mine virtual digital currency.

The computing equipment can better save the chip area, reduce the production cost and further reduce the power consumption of the computing equipment.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

Drawings

FIG. 1 is a schematic diagram of a conventional positive feedback D flip-flop;

FIG. 2 is a diagram of a conventional dynamic D flip-flop;

FIG. 3 is a diagram of a dynamic D flip-flop according to the present invention;

FIG. 4A is a schematic diagram of a dynamic D flip-flop circuit according to an embodiment of the present invention;

FIG. 4B is a schematic diagram of a dynamic D flip-flop circuit according to another embodiment of the present invention;

FIG. 5A is an equivalent circuit diagram of the dynamic D flip-flop when writing data according to the present invention;

FIG. 5B is an equivalent circuit diagram of the dynamic D flip-flop under the data retention state of the present invention;

FIG. 6 is a timing diagram of the dynamic D flip-flop of the present invention;

FIG. 7 is a schematic diagram of a data operation unit according to the present invention;

FIG. 8 is a diagram of a chip according to the present invention;

FIG. 9 is a schematic view of a force computation plate according to the present invention;

FIG. 10 is a schematic diagram of a computing device of the present invention.

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

FIG. 3 is a diagram of a dynamic D flip-flop according to the present invention. Referring to fig. 3, the dynamic D flip-flop 400 is composed of a first latch unit 401, a second latch unit 402, and an output driving unit 403. The first latch unit 401, the second latch unit 402, and the output driving unit 403 are sequentially connected in series between the input terminal 404 and the output terminal 405 of the dynamic D flip-flop 400.