阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 谷江尚史 岛津浩美 伊藤博之 于 2018-07-02 设计创作，主要内容包括：本发明的目的在于,提供一种在陶瓷层中形成有配线层的半导体器件,其能够使半导体开关元件的栅极端子与配线层之间可靠地导通。本发明的半导体器件在形成于绝缘层上的陶瓷层的内部具有配线层,并且具有与半导体开关元件的栅极端子以外的端子连接的金属层,所述半导体开关元件的栅极端子与所述配线层经由用导电材料形成的连接部电连接,与所述金属层相比,所述连接部更加向所述半导体开关元件突出(参照图1)。(The present invention provides a semiconductor device having a wiring layer formed in a ceramic layer, which can reliably conduct between a gate terminal of a semiconductor switching element and the wiring layer. The semiconductor device of the present invention includes a wiring layer inside a ceramic layer formed on an insulating layer, and a metal layer connected to a terminal other than a gate terminal of a semiconductor switching element, wherein the gate terminal of the semiconductor switching element is electrically connected to the wiring layer via a connection portion formed of a conductive material, and the connection portion protrudes toward the semiconductor switching element more than the metal layer (see fig. 1).)

1. A semiconductor device including a semiconductor switching element, characterized by comprising:

a first insulating substrate on which the semiconductor switching element is mounted; and

a second insulating substrate having an insulating layer with a wiring layer and a metal layer on one surface thereof,

the one surface of the insulating layer and the surface of the first insulating substrate on which the semiconductor switching element is mounted are disposed opposite to each other,

the wiring layer is formed inside a ceramic layer formed on the one surface of the insulating layer,

the gate terminal of the semiconductor switching element is electrically connected to the wiring layer via a connection portion formed of a conductive material and a first bonding material,

a terminal of the semiconductor switching element other than the gate terminal is electrically connected to the metal layer via a second bonding material,

a distance from the one surface of the insulating layer to an end of the connecting portion on the first insulating substrate side is larger than a distance from the one surface of the insulating layer to a surface of the metal layer on the first insulating substrate side.

2. The semiconductor device according to claim 1, wherein:

the connection portion is formed as a protrusion protruding from the wiring layer toward the gate terminal.

3. The semiconductor device according to claim 2, wherein:

the connecting portion has a shape tapered from the insulating layer toward the gate terminal.

4. The semiconductor device according to claim 2, wherein:

the connecting part has a spring structure.

5. The semiconductor device according to claim 1, wherein:

the connecting portion is formed as a core member disposed inside the first joining material.

6. The semiconductor device according to claim 1, wherein:

the first insulating substrate is also mounted with a diode chip,

the ceramic layer is formed at the following positions, namely: a position overlapping with the semiconductor switching element and not overlapping with the diode chip when the first insulating substrate and the second insulating substrate are projected onto the opposing faces.

7. The semiconductor device according to claim 1, wherein:

the semiconductor switching element is an IGBT or a MOSFET,

the ceramic layer is formed at the following positions, namely: a position overlapping with a gate terminal of the semiconductor switching element when the first insulating substrate and the second insulating substrate are projected onto the opposing faces,

the metal layer is disposed at the following positions: a position which does not overlap with the ceramic layer and overlaps with an emitter terminal of the semiconductor switching element when the first insulating substrate and the second insulating substrate are projected onto the opposing faces.

8. The semiconductor device according to claim 1, wherein:

the first insulating substrate has a heat dissipation layer on a surface on which the semiconductor switching element is not mounted,

the second insulating substrate has a heat dissipation layer on the other surface without the wiring layer and the metal layer.

9. The semiconductor device according to claim 1, wherein:

the semiconductor switching element is an IGBT or a MOSFET,

the first insulating substrate has a metal layer on a surface on which the semiconductor switching element is mounted, and the metal layer of the first insulating substrate is electrically connected to a collector terminal of the semiconductor switching element.

10. The semiconductor device according to claim 1, wherein:

the first insulating substrate mounts a plurality of the semiconductor switching elements,

the wiring layer has a rectangular flat plate shape,

the wiring layer is formed at the following positions: a position overlapping with a gate terminal of each of the semiconductor switching elements when the first insulating substrate and the second insulating substrate are projected onto the opposing faces.

11. The semiconductor device according to claim 1, wherein:

the first insulating substrate mounts a plurality of the semiconductor switching elements,

the wiring layer has a shape branched to the gate terminal of each semiconductor switching element.

12. A manufacturing method of manufacturing the semiconductor device according to claim 1, characterized in that:

the semiconductor switching element is an IGBT or a MOSFET,

the method comprises the following steps:

a step of coating the first bonding member on a gate terminal and an emitter terminal of the semiconductor switching element;

simultaneously bonding the semiconductor switching element and the second insulating substrate using the first bonding material,

a step of bonding the semiconductor switching element to the first insulating substrate.

13. The manufacturing method according to claim 12, characterized in that:

the method also has the step of forming the ceramic layer by sintering the ceramic material at 1000 ℃ or less.

Technical Field

The present invention relates to a power semiconductor device and a method for manufacturing the same.

Background

In recent years, electric driving of various devices has been advanced, and in a power module for controlling the number of revolutions of an AC motor and rectifying a high-power AC/dc current composed of a voltage of several kV and a current of several hundreds a, which are used as power of the devices, miniaturization, high performance, and high reliability have been demanded. Since the semiconductor chip mounted inside generates heat during operation of the power module, high heat dissipation is required to achieve miniaturization. Further, since the semiconductor chip operates at a high voltage of several kV, insulation from the outside needs to be secured. In order to efficiently control the semiconductor chip, it is necessary to provide a control circuit having a high degree of freedom in design and manufacturing processes.

Patent document 1 below discloses a technique relating to the above problem. In this document, a module is constructed by stacking green sheets of Low Temperature fired ceramic (LTCC) on a sintered ceramic substrate, firing the green sheets to form a composite ceramic substrate, and mounting electronic components such as a capacitor and an IC chip on the composite ceramic substrate.

Disclosure of Invention

Technical problem to be solved by the invention

A power module can be constructed by using a ceramic substrate having a control signal circuit layer made of wiring and ceramic and a circuit layer made of metal, forming a gate circuit by the wiring layer of the control signal circuit layer, and forming an emitter circuit or a collector circuit by a thick metal layer for a circuit. In order to operate such a power module with high reliability, it is necessary to reliably obtain electrical conduction between the mounted semiconductor chip and the circuit of the power module. That is, it is necessary to ensure conduction between the gate terminal of the semiconductor chip and the wiring layer of the control signal circuit, and to ensure conduction between the emitter terminal or the collector terminal and the circuit layer made of metal. In this case, the gate terminal of the semiconductor chip is smaller in area than the emitter terminal or the collector terminal, and therefore, it is more difficult to ensure conduction than the emitter terminal or the collector terminal in view of thermal deformation resistance after positioning or bonding. The thermal conductivity of the control signal circuit layer made of ceramic is smaller than that of the circuit layer made of metal.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which a wiring layer is formed in a ceramic layer, and which can achieve both high heat dissipation and high reliability by securing conduction between a gate terminal of a semiconductor switching element and the wiring layer and securing heat dissipation.

Means for solving the problems

The semiconductor device of the present invention has a wiring layer inside a ceramic layer formed on an insulating layer, and has a metal layer connected to a terminal other than a gate terminal of a semiconductor switching element, wherein the gate terminal of the semiconductor switching element is electrically connected to the wiring layer via a connection portion formed of a conductive material, and the connection portion protrudes toward the semiconductor switching element more than the metal layer.

Effects of the invention

According to the semiconductor device of the present invention, conduction between the gate terminal of the semiconductor switching element and the wiring layer can be ensured, and heat dissipation can be ensured, so that high heat dissipation and high reliability can be achieved at the same time.

Drawings

Fig. 1 is a structural diagram of a semiconductor device 1 of embodiment 1.

Fig. 2 is a structural view of the first insulating substrate 13.

Fig. 3 is a structural view of the second insulating substrate 14.

Fig. 4 is a structural diagram of a semiconductor chip.

Fig. 5 is a diagram illustrating development of components of the semiconductor device 1.

Fig. 6 is a cross-sectional view of the semiconductor device 1.

Fig. 7 is a diagram illustrating a method of manufacturing the semiconductor device 1.

Fig. 8 is a cross-sectional view of semiconductor device 1 of embodiment 2.

Fig. 9 is a sectional view of semiconductor device 1 of embodiment 3.

Fig. 10 is a cross-sectional view of semiconductor device 1 of embodiment 4.

Fig. 11 is an overall configuration diagram of semiconductor device 1 according to embodiment 5.

Detailed Description

< embodiment 1 >

Fig. 1 is a structural diagram of a semiconductor device 1 according to embodiment 1 of the present invention. The semiconductor device 1 internally mounts an igbt (insulated Gate Bipolar transistor) chip 11 and a diode chip 12. The semiconductor device 1 can function as a part of an inverter circuit by being led out to the outside of the semiconductor device 1 through the gate terminal 15 for external lead-out, the emitter terminal 16 for external lead-out, and the collector terminal 17 for external lead-out. Here, an example is shown in which two IGBT chips 11 and one diode chip 12 are disposed inside the semiconductor device 1.

A second insulating substrate 14 for an emitter terminal and a gate terminal is disposed on one surface of the semiconductor device 1, and a first insulating substrate 13 for a collector terminal is disposed on the other surface. Heat generated when the semiconductor chip operates can be dissipated from both surfaces of the semiconductor device 1. The IGBT chip 11, the diode chip 12, the second insulating substrate 14, and the first insulating substrate 13 are molded by a molding resin 18. This ensures insulation and reliability. In the present embodiment, a highly heat-resistant epoxy-based resin is used for the molding resin 18.

Fig. 2 is a structural view of the first insulating substrate 13. The first insulating substrate 13 for the collector terminal has an insulating layer 21. A circuit layer 22 as a metal layer is disposed on one surface of the insulating layer 21, and a heat dissipation layer 23 is disposed on the other surface. The external lead-out collector terminal 17 is connected to the circuit layer 22, and the external device and the semiconductor device 1 are electrically conducted through the collector terminal 17. In embodiment 1, a ceramic made of silicon nitride is used as the insulating layer 21. Since the same material is excellent in insulation and thermal conductivity and has high strength, the same material is selected from the viewpoint of heat dissipation and reliability. Other ceramics such as alumina and aluminum nitride can be used depending on the use and use environment of the semiconductor device 1. Copper is used for the circuit layer 22, the heat dissipation layer 23, and the external extraction collector terminal 17. This is because the electrical conductivity and the thermal conductivity are excellent. Other metal materials such as aluminum can be used depending on the use and use environment of the semiconductor device 1. In the present embodiment, the surface of the heat dissipation layer 23 is formed in a smooth shape. This is for easy connection of heat dissipation fins and the like when the present semiconductor device 1 is used. Further, fins may be provided on the surface of the heat dissipation layer 23, and the heat dissipation layer 23 itself may be used as the heat dissipation fins. In this case, although the fins need to be provided, heat dissipation can be further improved without increasing thermal resistance due to the connecting members between the heat dissipation layer 23 and the heat dissipation fins.

Fig. 3 is a structural view of the second insulating substrate 14. The second insulating substrate 14 for a gate terminal has an insulating layer 31. A heat dissipation layer 34 is disposed on one main surface of the insulating layer 31. On the other main surface of the insulating layer 31, a circuit layer 32 as a metal layer and an insulating wiring 33 as a wiring layer for a gate terminal are arranged.

In embodiment 1, a ceramic made of silicon nitride is used as the insulating layer 31. For the same reason as the insulating layer 21. By using the same material as the insulating layer 21 of the first insulating substrate 13, the thermal deformation balance of the entire semiconductor device 1 can be obtained. Other ceramics such as alumina and aluminum nitride can be used depending on the use and use environment of the semiconductor device 1. Copper is used for the circuit layer 32, the heat dissipation layer 34, and the emitter terminal 16 for external extraction. This is because the electrical conductivity and the thermal conductivity are excellent. Other metal materials such as aluminum can be used depending on the use and use environment of the semiconductor device 1.

A protrusion 35 serving as a connection portion is provided at a portion of the circuit layer 32 to be bonded to the semiconductor chip. The bumps 35 are used to ensure pressure resistance by spacing the circuit layer 32 from the peripheral portion of the semiconductor chip when the semiconductor chip is bonded to the circuit layer 32. The protrusion 35 disposed at a portion facing the IGBT chip 11 is formed in an コ shape so as to avoid the gate terminal of the IGBT chip 11. Since the diode chip 12 does not have a gate terminal, the protrusion 35 disposed at a position facing the diode chip 12 is formed in a rectangular shape instead of an コ shape. The surface of the heat dissipation layer 34 is formed to have a smooth shape. This is for easy connection of heat dissipation fins and the like when the semiconductor device 1 is used. Further, fins may be provided on the surface of the heat dissipation layer 34, and the heat dissipation layer 34 itself may be used as the heat dissipation fins. In this case, although the fins need to be provided, heat dissipation can be further improved without increasing thermal resistance due to the connecting members between the heat dissipation layer 34 and the heat dissipation fins.

An insulated wire 33 for a gate terminal, which is electrically connected to the gate terminal, is disposed at a portion of the IGBT chip 11 facing the gate terminal. Low-temperature sintered ceramics are used as the insulated wiring 33. The ceramic insulator having the metal wiring layer disposed therein can be formed by stacking sheets composed of a ceramic material and a metal paste before sintering, and simultaneously sintering the ceramic and the metal at a low temperature of about 1000 ℃. In embodiment 1, a material in which three or more oxides containing magnesium, aluminum, and silicon as main components are mixed is used as the low-temperature sintered ceramic. A polycrystalline sintered body obtained by sintering these materials at 1000 ℃ is preferred because it is easy to freely design an internal wiring layer by forming and laminating a metal paste by printing or the like. Further, an insulating wiring 33 made of ceramic having a metal wiring layer therein is formed, wherein the metal wiring layer electrically connects the projection 36 for connection to the gate terminal and the gate terminal 15 for external extraction. The low-temperature sintered ceramic is sintered and then disposed on the surface of the wiring disposed inside the ceramic. In embodiment 1, a protrusion 36 for gate terminal connection prepared in advance is bonded to the surface of the wiring by diffusion bonding. In addition, the projection may be provided for bonding using a bonding material or by plating the surface of the wiring. In this case, the bumps 36 are smaller in area than the bumps 35, but larger in height than the bumps 35 and protrude further toward the gate terminal of the IGBT chip 11 than the bumps 35.

Fig. 4 is a structural diagram of a semiconductor chip. Gate terminal 41 and emitter terminal 42 are arranged on the surface of IGBT chip 11, and gate terminal 41 has a smaller area than emitter terminal 42. A collector terminal 43 is disposed on the rear surface of the IGBT chip 11. The diode chip 12 does not have a gate terminal. A gate terminal 41 on the chip surface and an emitter terminal 42 on the chip surface are arranged on the surface of the IGBT chip 11, and the area of the gate terminal 41 on the chip surface is smaller than the area of the emitter terminal 42 on the chip surface. The IGBT chip 11 has a collector terminal 43 on its back surface. On the other hand, the diode chip 12 does not have a gate terminal, and has a cathode terminal on the front surface and an anode terminal on the back surface. In the present embodiment, two IGBT chips 11 and one diode chip 12 are provided inside the semiconductor device 1, but the number of the IGBT chips 11 or the diode chips 12 may be changed. Instead of the IGBT chip 11, a MOS-FET chip or the like may be used. As long as they are selected according to the capacity and characteristics required for the semiconductor device 1.

Fig. 5 is a diagram illustrating development of components of the semiconductor device 1. Here, components other than the molding resin 18 are shown. In the semiconductor device 1, the second insulating substrate 14 and the first insulating substrate 13 are arranged in the vertical direction, and the IGBT chip 11 and the diode chip 12 are arranged between these substrates, thereby forming a circuit. Emitter terminal 42 of IGBT chip 11 and emitter terminal of diode chip 12 are connected to second insulating substrate 14 via bonding material 51. The gate terminal 41 is connected to the second insulating substrate 14 via a bonding material 52. The collector terminal 43 of the IGBT chip 11 and the collector terminal of the diode chip 12 are connected to the first insulating substrate 13 via a bonding material 53. This bonding method does not require a bonding wire or the like, and therefore can provide a circuit which is easy to control the length and resistance of the circuit and has excellent electrical characteristics.

The heat dissipation layer 34 of the second insulating substrate 14 and the heat dissipation layer 23 of the first insulating substrate 13 are disposed on the upper and lower surfaces of the semiconductor device 1, respectively. This enables efficient heat dissipation from both sides of the semiconductor device 1, and therefore, the semiconductor device 1 having excellent heat dissipation characteristics of heat generated from the semiconductor chip during operation can be provided.

When the components of the semiconductor device 1 are projected onto the main surface, the region where the IGBT chip 11, the diode chip 12, and the insulating wiring 33 overlap is only in the vicinity of the gate terminal 41 of the IGBT chip 11, and the other region of the IGBT chip 11 does not overlap the insulating wiring 33. The diode chip 12 does not overlap the insulating wiring 33 in the entire region.

The copper constituting the circuit layer 32 has a higher thermal conductivity than the low-temperature sintered ceramic constituting the insulating wiring 33. Therefore, the area of the insulating wiring 33 disposed in the region between each semiconductor chip and the heat dissipation layer 34 is minimized, and the area of the circuit layer 32 is increased as much as possible, thereby improving heat dissipation. In embodiment 1, since the insulating wiring 33 is formed only around the gate terminal, the area of the circuit layer 32 can be greatly secured, and heat dissipation can be improved. In order to improve heat dissipation, it is effective to dissipate heat generated from the semiconductor chip in the thickness direction and to diffuse it quickly in the horizontal direction. In the present embodiment, one of the copper composing the circuit layer 32 has a thermal conductivity higher than that of silicon nitride composing the insulating layer of the insulating substrate disposed above and below the semiconductor chip, and diffusion of heat in the horizontal direction can be further promoted by setting the thickness of the circuit layer 32 to be equal to or greater than the thickness of the insulating layer.

Fig. 6 is a cross-sectional view of the semiconductor device 1. Here, a cross-sectional enlarged view of the vicinity of the IGBT chip 11 is shown. As described with reference to fig. 3, the height of the gate terminal connection protrusion 36 protruding from the gate terminal insulating wire 33 toward the semiconductor chip is larger than the height of the emitter circuit layer connection protrusion 35. That is, the projection 36 for gate terminal connection protrudes further than the tip of the projection 35 for emitter circuit layer connection than the principal surface of the insulating layer 31 of the emitter terminal and gate terminal insulating substrate. In other words, the distance between the IGBT 11-side end of the protrusion 36 and the IGBT chip 11 is smaller than the distance between the IGBT chip 11-side end of the protrusion 35 and the IGBT chip 11. Bonding materials 51 and 52 are disposed between the respective protrusions (protrusion 35 and protrusion 36) and the IGBT chip 11. As described in the manufacturing method described later, the applied joining members 51 and 52 have the same thickness, but the projection 36 for connecting the gate terminal protrudes to further press the joining member 52 in the manufacturing process, so that the finished joining member 52 is thinner than the joining member 51. In this way, by further pressing the bonding material 52 for manufacturing, conduction of the gate terminal can be ensured more reliably, and therefore, connection reliability can be improved.

Fig. 7 is a diagram illustrating a method of manufacturing the semiconductor device 1. First, a state in which no processing is performed on the IGBT chip 11 and the diode chip 12 is an initial state (fig. 7 (a)).

Fig. 7(b) shows a step of coating the bonding material. In embodiment 1, first, a bonding material is applied to the surfaces of the IGBT chip 11 and the diode chip 12. Among the solder materials mainly containing Sn as a bonding material, materials mainly containing Sn and Cu having high melting points are used as the bonding materials 51 and 52, and flux-like solder containing volatile components is applied to the surface of each semiconductor chip using a mask. At this time, the bonding materials 51 and 52 are arranged so that the gate terminal 41 and the emitter terminal 42 of the IGBT chip 11 are not electrically short-circuited. When coating a bonding material using a mask, a complicated mask needs to be prepared and a plurality of coating processes need to be performed in order to coat bonding materials having different thicknesses. Therefore, in embodiment 1, the thickness of the bonding material to be coated is set to be the same, and the bonding material is coated by a single coating process using one mask for each semiconductor chip.

Fig. 7(c) shows a step of bonding the semiconductor chip to the second insulating substrate 14 using the bonding materials 51 and 52. The positioning of the second insulating substrate 14 and the semiconductor chip is performed using a carbon jig. The joining materials 51 and 52 are melted by using a reflow apparatus and then solidified, thereby joining the members. The carbon jig is a vertically divided jig, and a pin for positioning with the upper jig and a recess for positioning the insulating substrate 14 for the emitter terminal and the gate terminal are provided on the upper surface of the lower jig. The upper jig is provided with holes through which pins of the lower jig pass and holes penetrating the upper and lower surfaces for positioning the respective semiconductor chips. In manufacturing, the insulating substrate 14 for the emitter terminal and the gate terminal is disposed in the recess of the lower jig with the heat dissipation layer 34 facing downward, the lower jig and the upper jig are positioned using the pins of the lower jig and the holes of the upper jig, and the semiconductor chips are disposed with the bonding materials 51, 52 applied from the holes for positioning the semiconductor chips of the upper jig facing downward. In this state, each semiconductor chip is bonded to the insulating substrate 14 for the emitter terminal and the gate terminal by bonding using a reflow apparatus. Since the height of the protrusion 36 is larger than the height of the protrusion 35, when the bonding materials 51 and 52 have the same thickness, the bonding material 52 is further pressed while allowing the slope of the semiconductor chip and the dimensional tolerance of each member at the time of bonding, whereby the gate terminal can be reliably connected. Therefore, the semiconductor device 1 with high reliability can be improved.

Fig. 7(d) shows the surface of the first insulating substrate 13 on the circuit layer 22 side. Fig. 7(e) shows a step of applying a bonding material 53 to the surface of the circuit layer 22. A solder material containing Sn as a main component is used as the bonding material 53, and a paste-like solder material is applied using a mask. As the bonding material 53, a solder material containing Sn, Ag, and Cu as main components, which have a lower melting point than the bonding materials 51 and 52, is used.

Fig. 7(f) is a process of bonding the first insulating substrate 13 (bonded semiconductor chip) and the second insulating substrate 14. The positioning of the first insulating substrate 13 and the second insulating substrate 14 is performed using a carbon jig. The bonding material 53 is melted by using a reflow apparatus and then solidified, thereby bonding the substrates. Since the melting point of the bonding material 53 is lower than the melting points of the bonding materials 51 and 52, the bonding materials 51 and 52 can be prevented from being melted again in the reflow process. In the present embodiment, the melting point is set to be different by the difference In Ag content, but the melting point may be controlled by using an additive such as Bi or In.

Fig. 7(g) shows a step of sealing the entire device with a mold resin 18. The semiconductor device 1 is completed by this process. Namely, a manufacturing method of forming the following semiconductor device: first, a bonding material is applied to the gate terminal and the emitter terminal of the semiconductor chip, and then the semiconductor chip and the insulating substrate for the emitter terminal and the gate terminal are simultaneously bonded using the bonding material, and then the semiconductor chip and the insulating substrate for the collector terminal are bonded. The manufacturing method can obtain the following effects: first, the gate terminal is connected to reliably ensure conduction of the gate terminal having a small area, and the emitter terminal and the gate terminal are simultaneously bonded to each other, thereby simplifying the manufacturing process.

< embodiment 1: summary of the invention

In the semiconductor device 1 of embodiment 1, the bumps 36 protrude from the insulated wires 33 made of a ceramic material and a wiring layer toward the IGBT chip 11 more than the bumps 35. This makes it possible to reliably conduct the gate terminal having a small area to the wiring layer.

In the semiconductor device 1 of embodiment 1, the insulating wiring 33 having a small thermal conductivity is disposed only around the gate terminal, so that a larger area of the circuit layer 32 having a large thermal conductivity is secured. This ensures sufficient heat dissipation.

< embodiment 2 >

Fig. 8 is a cross-sectional view of semiconductor device 1 of embodiment 2 of the present invention. In embodiment 2, the protrusion 36 has a tapered shape as it gets closer to the tip (end closer to the IGBT chip 11 side). The other structure is the same as embodiment 1. In embodiment 2, since the projection 36 has a tapered shape, the projection 36 is recessed into the bonding material 52 when the bonding material 52 is softened in the reflow step, and the gate terminal can be connected more reliably. In the present embodiment, the gate terminal connection protrusion 36 prepared in advance is bonded to the wiring surface by diffusion bonding. In addition, a protrusion may be provided for bonding using a bonding material, or a protrusion may be provided by plating the surface of the wiring.

< embodiment 3 >

Fig. 9 is a cross-sectional view of semiconductor device 1 according to embodiment 3 of the present invention. In embodiment 3, the projection 36 has a curved structure, and the rigidity in the height direction is lower than that in embodiment 1. The other structure is the same as embodiment 1. When the protrusion 36 is connected to the gate terminal, if the surface of the IGBT chip 11 is strongly pressed by the protrusion 36, there is a possibility that the electrode on the surface of the IGBT chip 11 and the semiconductor element inside may be damaged. By reducing the rigidity of the projections 36 in the height direction, it is possible to reliably prevent the electrodes on the surface of the IGBT chip 11 and the semiconductor elements inside from being pressed extremely strongly, and a semiconductor device with higher reliability can be provided.

In embodiment 3, the rigidity in the height direction can be reduced by another structure such as a spring shape or a zigzag shape instead of or in addition to the bending structure. Alternatively, by using a material having a small longitudinal elastic coefficient for the protrusion 36, the rigidity in the height direction can be reduced. Any one of them can be selected and used according to the manufacturing method and manufacturing process of the protrusion 36.

< embodiment 4 >

Fig. 10 is a cross-sectional view of semiconductor device 1 of embodiment 4 of the present invention. In embodiment 4, a substantially spherical core member 101 is disposed inside the joining material 52 instead of the projection 36. The other structure is the same as embodiment 1. As the core member 101, a copper core ball is used, in which nickel plating is performed on the surface of the copper ball and Sn plating is performed thereon. In embodiment 4, at least a part of the core member 101 is disposed at a position closer to the IGBT chip 11 than the protrusion 35. This allows the gate terminal 41 to be more reliably connected to the wiring layer.

In the manufacturing process, when the bonding material 52 is melted and solidified by the reflow apparatus, the Sn plating on the surface of the core member 101 is melted and solidified to reliably conduct electricity to the gate terminal 41, while the copper and nickel constituting the core member 101 are not melted, so that the insulated wiring 33 and the IGBT chip 11 can be connected to each other with a distance secured therebetween.

In embodiment 4, the core member 101 having a substantially spherical shape is used, but if it has a shape capable of obtaining the above-described function, it may be used in another shape such as a polygonal shape or a shape in a state of being crushed into particles. As the core member 101, other materials such as a polyimide ball material can be used as long as they are high-temperature materials subjected to the reflow process. These may be selected according to the manufacturing method and manufacturing process of the core member 101.

< embodiment 5 >

Fig. 11 is an overall configuration diagram of semiconductor device 1 according to embodiment 5 of the present invention. While the insulated wire 33 is substantially rectangular in embodiment 1, in embodiment 5, the insulated wire 33 has a shape branched into the projections 36 (i.e., the gate terminals).

In embodiment 5, when each component of the semiconductor device 1 is projected onto the main surface, the insulated wire 33 and the IGBT chip 11 overlap only in the vicinity of the gate terminal 41. This allows the front surface of emitter terminal 42 to be connected to protrusion 35. The thermal conductivity of copper constituting the protrusion 35 is higher than that of low-temperature sintered ceramics constituting the insulating wiring 33. Therefore, as in embodiment 5, by further increasing the area where the IGBT chip 11 and the protrusion 35 are joined, the semiconductor device 1 can be cooled efficiently. In the present embodiment, the IGBT is used for the switching element, but when the MOS-FET is used, the insulated wire 33 for the gate terminal overlaps only in the vicinity of the MOS-FET chip and the gate terminal.

In embodiment 5, since the insulated wire 33 has a branched complex shape, it is necessary to cut the insulated wire 33 by dicing or the like after manufacturing the insulated wires 33 for a plurality of gate terminals one by one, and the manufacturing difficulty is increased. However, the insulated wire 33 can be manufactured by a manufacturing method different from that of embodiment 1, such as cutting and sintering a green sheet before sintering ceramic. An appropriate embodiment can be selected according to the processing method, the cooling performance required for the semiconductor device 1, and the like.

< modification of the present invention >

The present invention is not limited to the above embodiment, and includes various modifications. For example, the above-described embodiments are described in detail to facilitate understanding of the present invention, and are not necessarily limited to the embodiments having all the configurations described. In addition, a part of the structure of one embodiment may be replaced with the structure of another embodiment, and the structure of another embodiment may be added to the structure of one embodiment. Further, a part of the configuration of each embodiment can be added, deleted, or replaced with another configuration.

In the above embodiment, the example word having two IGBT chips 11 and one diode chip 12 inside the semiconductor device 1 was described, but the number of the IGBT chips 11 and the diode chips 12 may be changed. Instead of the IGBT chip 11, a MOS-FET (Metal-Oxide-Semiconductor Field-Effect Transistor) chip or the like may be used. These may be selected according to the capacity and characteristics required in the semiconductor device 1.

Description of the symbols

1: semiconductor device with a plurality of transistors

11: IGBT chip

12: diode chip

13: first insulating substrate

14: second insulating substrate

15: gate terminal

16: emitter terminal

17: collector terminal

18: molding resin

21: insulating layer of first insulating substrate

22: circuit layer of first insulating substrate

23: heat sink layer of first insulating substrate

31: insulating layer of second insulating substrate

32: circuit layer of second insulating substrate

33: insulated wiring

34: heat sink layer of second insulating substrate

35: protrusion

36: protrusion

41: gate terminal

42: emitter terminal

43: collector terminal

51: joining material

52: joining material

53: joining material

101: a core member.