阅读说明：本技术 具有中间电路电容器级联以及dc侧共模和差模滤波器的逆变器 (Inverter with intermediate circuit capacitor cascade and DC-side common-mode and differential-mode filters ) 是由 海因茨·林登伯格 于 2018-05-15 设计创作，主要内容包括：本发明涉及一种具有中间电路电容器的逆变器(1),中间电路电容器的连接端连接到用于供电的电源线(3、4)和包括多个半桥(13)的开关装置(10),其中中间电路电容器具有预先设定的中间电路电容(C),其大小使得由开关装置(10)中的开关过程在电源线(3、4)中形成的纹波电压在预先设定的工作条件下减少到预先设定的最大纹波电压。为了减少差模干扰,本发明提出了提供并联连接的多个中间电路电容器(11、12),其中所述多个中间电路电容器(11、12)的电容(C1、C2)之和对应于中间电路电容(C)。(The invention relates to an inverter (1) having an intermediate circuit capacitor, the terminals of which are connected to supply lines (3, 4) for supplying power and to a switching device (10) comprising a plurality of half-bridges (13), wherein the intermediate circuit capacitor has a predetermined intermediate circuit capacitance (C) which is dimensioned such that a ripple voltage formed in the supply lines (3, 4) by a switching process in the switching device (10) is reduced to a predetermined maximum ripple voltage under predetermined operating conditions. In order to reduce differential mode interference, the invention proposes to provide a plurality of intermediate circuit capacitors (11, 12) connected in parallel, wherein the sum of the capacitances (C1, C2) of the plurality of intermediate circuit capacitors (11, 12) corresponds to the intermediate circuit capacitance (C).)

1. An inverter (2) having an intermediate circuit capacitor, the connection of which is connected to supply lines (3, 4) for supplying power and a switching device (10) comprising a plurality of half bridges (13),

wherein the intermediate circuit capacitor has a predetermined intermediate circuit capacitance (C) which is dimensioned such that a ripple voltage formed in the power supply lines (3, 4) by a switching process in the switching device (10) is reduced to a predetermined maximum ripple voltage under predetermined operating conditions,

it is characterized in that the preparation method is characterized in that,

in order to reduce differential mode interference, a plurality of intermediate circuit capacitors (11, 12) connected in parallel is provided, wherein the sum of the capacitances (C1, C2) of the plurality of intermediate circuit capacitors (11, 12) corresponds to the predetermined intermediate circuit capacitance (C).

2. The inverter (2) of claim 1, wherein a first capacitance (C1) of a first intermediate circuit capacitor (11) connected to the switching device (10) is greater than a second capacitance (C2) of a second intermediate circuit capacitor (12) connected upstream of the first intermediate circuit capacitor (11) at an input.

3. The inverter (2) of any one of the preceding claims, wherein a plurality of second intermediate circuit capacitors (12) are connected upstream of the first intermediate circuit capacitor (11) at an input.

4. The inverter (2) of any one of the preceding claims, wherein the first capacitance (C1) accounts for 95-70% of the preset intermediate circuit capacitance and the second capacitance (C2) accounts for 5-30% of the preset intermediate circuit capacitance (C).

5. The inverter (2) of any one of the preceding claims, wherein a filter circuit (5) for reducing common-mode interference is connected to the supply lines (3, 4), wherein the filter circuit (5) comprises one or more filter stages, which filter stages are connected one after the other.

6. The inverter (2) of any one of the preceding claims, wherein an X-capacitor (6) is connected between the power supply lines (3, 4) in the filter stage, and each power supply line (3, 4) is connected to ground (G) by a Y-capacitor (7).

7. The inverter (2) of any one of the preceding claims, wherein the filter stage comprises a toroidal core inductor (8) around the power supply lines (3, 4) and further comprises a filter inductor (9) joined around each of the power supply lines (3, 4), respectively.

Technical Field

The present invention relates to an inverter according to the preamble of claim 1.

Such inverters are generally known and are used, for example, for supplying power to a three-phase motor in an electric or partially electric vehicle.

Background

In order to convert direct current into alternating current, the inverter has a plurality of half-bridge circuits or half-bridges which are driven by a controller by means of pulse-width-modulated signals in order to generate a predetermined AC voltage. A so-called intermediate circuit capacitor is connected to the supply line for supplying the direct current and is used for supplying the half bridge.

Common-mode (CM) interference, which causes ripple voltage, is generated in the power supply line due to the clock driving of the half bridge. In order to avoid the electromagnetic interference field formed by the ripple voltage, it is necessary to reduce the ripple voltage to a maximum preset value. For this purpose, the intermediate circuit capacitance of the intermediate circuit capacitor is selected in a suitable manner. The correspondingly selected intermediate circuit capacitance is greater than the capacitance required for supplying the half-bridge.

In addition, differential-mode (DM) interference may be generated during operation of the inverter. DM interference is the result of current variations in the parasitic inductances of the power transistors used in the half-bridge and the intermediate circuit capacitors. The DM interference increases with the magnitude of the phase current supplied to the motor by the half bridge. Heretofore, in the case of a high-demand phase current, there have been cases where DM interference cannot be sufficiently filtered.

Disclosure of Invention

The object of the present invention is to eliminate the drawbacks of the prior art. In particular, it is an object to propose an improved inverter suppressing DM interference. According to another object of the invention, it is an object to be able to manufacture an inverter in a manner that is as simple and cost-effective as possible.

This object is achieved by the features of claim 1. Advantageous developments of the invention can be found in the features of the dependent claims.

According to the invention it is proposed to provide a plurality of intermediate circuit capacitors connected in parallel, wherein the sum of the capacitances of the plurality of intermediate circuit capacitors corresponds to a predetermined intermediate circuit capacitance, in order to reduce differential mode or DM interference. In other words, the intermediate circuit capacitor provided according to the prior art is replaced by a plurality of intermediate circuit capacitors connected in series. In the process, the preset intermediate circuit capacitances previously preset for the individual intermediate circuit capacitors are retained. By providing a plurality of intermediate circuit capacitors, the ripple voltage is kept substantially constant.

The separation of the intermediate circuit capacitor into a plurality of intermediate circuit capacitors according to the invention advantageously greatly reduces DM interference, in particular when high phase currents arise. The intermediate circuit capacitor can be separated into a plurality of intermediate circuit capacitors in a simple and cost-effective manner. The separation is thus possible, in particular because the necessary capacitance for driving the switching device is generally lower than another necessary capacitance for reducing the ripple voltage to a predetermined maximum value. The sum of the capacitances of the separate intermediate circuit capacitors is crucial for regulating the preset maximum ripple voltage.

The predetermined maximum ripple voltage and the selection of the size of the intermediate circuit capacitance are based on customer requirements. In case of a preset maximum ripple voltage, the intermediate circuit capacitance may be dimensioned, for example by simulation using a model representative of the inverter circuit in question. This model takes into account, among other things, the modulation type, the cosine phi of the motor, the clock frequency of the power transistors in the half-bridge and the intermediate circuit capacitance. In the simulation, boundary conditions were set so that the maximum ripple voltage was generated. The intermediate circuit capacitance is then set such that a predetermined maximum ripple voltage is generated under this boundary condition. For inverters used in the automotive field, typical intermediate circuit capacitances are in the range of 400 to 1000 μ F.

A plurality of second intermediate circuit capacitors may also be connected upstream of the first intermediate circuit capacitor. Also in this case, the sum of the first and second capacitances corresponds to a predetermined intermediate circuit capacitance. By providing a plurality of second intermediate circuit capacitors, DM interference can be reduced more effectively.

Advantageously, the first capacitance represents 95% to 70% of the predetermined intermediate circuit capacitance and the second capacitance represents 5% to 30% of the predetermined intermediate circuit capacitance.

According to a further advantageous development of the invention, the first capacitance of a first intermediate circuit capacitor connected to the switching device is greater than the second capacitance of a second intermediate circuit capacitor connected upstream of the first intermediate circuit capacitor at the input. The first capacitance of the first intermediate circuit capacitor is selected to be so high that sufficient current can always be supplied to the switching means. The second capacitance is a result of a difference between the predetermined intermediate circuit capacitance and the first capacitance. Due to the proposed provision of the first and second intermediate circuit capacitors, an LC element is formed which reduces DM interference. In this case, the inductance L is formed by the connecting line between the first and second intermediate circuit capacitors.

According to a further advantageous development of the invention, a filter circuit, in particular for reducing CM interference, is connected to the supply line for supplying the intermediate circuit capacitor, wherein the filter circuit comprises one or more filter stages, which are connected one after the other. The X-capacitor is advantageously connected between the supply lines in the filter stage. Further, each power supply line is grounded through a Y capacitor. The ground is formed by the housing of the inverter or the housing potential of the housing.

According to another refinement, the filter stage comprises a toroidal core inductor surrounding the supply lines and also comprises a filter inductor, respectively, joined around each supply line. Toroidal core inductors and filter inductors may be combined in appropriately designed assemblies.

Drawings

Exemplary embodiments of the invention will be described in more detail below with reference to the accompanying drawings, in which:

figure 1 shows a schematic first circuit arrangement of an inverter,

FIG. 2 shows a schematic circuit arrangement of a second inverter, an

Fig. 3 shows the interference level in relation to frequency.

Detailed Description

In fig. 1 and 2, reference numeral 1 denotes a battery that supplies, for example, a voltage of 200 to 400V. The battery 1 supplies power to an inverter, generally indicated by reference numeral 2. The first power line is denoted by reference numeral 3 and the second power line by reference numeral 4. The filter circuit is generally indicated by reference numeral 5 and comprises two filter stages connected to the supply lines 3, 4. Each filter stage has an X-capacitor 6 connected between the supply lines 3, 4 and a Y-capacitor 7 connected between each of the supply lines 3, 4 and the ground G of the housing. A toroidal core inductor surrounding the power supply lines 3, 4 is schematically indicated by reference numeral 8. Reference numeral 9 denotes a filter inductor surrounding each of the power supply lines 3, 4. Here, the filter circuit 5 has two identical filter stages. The filter circuit is particularly useful for reducing CM interference.

The inverter element 10 is connected downstream of the filter circuit 5. The inverter element 10 comprises at an input a first intermediate circuit capacitor 11 and a second intermediate circuit capacitor 12 connected in parallel with the first intermediate circuit capacitor. Half-bridges 13 are connected downstream of the first intermediate circuit capacitor 11, each half-bridge 13 comprising two power transistors 14. The power transistor may be a so-called IGBT (insulated gate bipolar transistor). A controller, indicated by reference numeral 15, is provided for driving the half bridge 13. The pulse width modulated signal is generated by the controller 15.

The phases u, v and w generated by the half-bridge 13 substantially form a sinusoidal alternating current for driving the three-phase motor M. If the three-phase electric machine M is operated as a generator, the three-phase current generated by said generator is converted into direct current by the half-bridge 13 and stored in the battery 1.

In this circuit arrangement, the first capacitance C1 of the first intermediate circuit capacitor 11 and the second capacitance C2 of the second intermediate circuit capacitor 12 are added to form a predetermined intermediate circuit capacitance C.

A second intermediate circuit capacitor 12 connected in parallel upstream of the first intermediate circuit capacitor 11 forms an LC element. In this case, the inductance L is formed by the connecting line 16 arranged between the first intermediate circuit capacitor 11 and the second intermediate circuit capacitor 12. The LC element reduces DM interference occurring during operation of the inverter element 10.

Although the intermediate circuit capacitor is separated into the first intermediate circuit capacitor 11 and the second intermediate circuit capacitor 12 according to the invention, the predetermined intermediate circuit capacitance C is maintained overall.

The intermediate circuit capacitance C is given by the sum of the first capacitance C1 and the second capacitance C2. In this case, the first capacitor C1 may occupy 95% to 70% of the predetermined intermediate circuit capacitance C, and the second capacitor C2 may occupy 5% to 30% of the predetermined intermediate circuit capacitance C.

Fig. 2 shows a schematic circuit arrangement of a further inverter, which differs from the circuit arrangement shown in fig. 1 only in that two second intermediate circuit capacitors 12 are connected in parallel upstream of the first intermediate circuit capacitor 11. The two LC elements formed by the two second intermediate circuit capacitors 12 can reduce the DM interference even more effectively. Here, the sum of the first capacitance C1 of the first intermediate circuit capacitor and the second capacitance C2 of the second intermediate circuit capacitor 12 again corresponds to the preset intermediate circuit capacitance C, which is obtained from the preset maximum ripple voltage under the preset boundaries or operating conditions.

In the present exemplary embodiment, the first capacitance C1 may be in the range of 300 to 600 μ F. Each second capacitance C2 may be in the range of 30 to 150 μ F.

Fig. 3 shows the interference level on the supply lines 3, 4 as a function of frequency. Curve a in fig. 3 shows the interference level in a conventional inverter in which only one intermediate circuit capacitor is provided. The intermediate circuit capacitance C of the single intermediate circuit capacitor is 500 muf. Curve B shows the disturbance level for the following inverter: wherein the second intermediate circuit capacitor 12 is connected in parallel upstream of the first intermediate circuit capacitor 11. The first capacitance C1 of the first intermediate circuit capacitor 11 is 400 μ F and the second capacitance C2 of the second intermediate circuit capacitor 12 is 100 μ F. In this case (as in the case of curve a) an intermediate circuit capacitance of 500 muf is produced as a whole. Also, as is clear from fig. 3, the voltage level represented by curve B is significantly lower than the interference level represented by curve a.

List of reference numerals:

1 Battery

2 inverter

3 first power line

4 second power line

5 filter circuit

6X capacitor

7Y capacitor

8 toroidal core inductor

9 filtering inductor

10 inverter element

11 first intermediate circuit capacitor

12 second intermediate circuit capacitor

13 half bridge

14 power transistor

15 controller

16 connecting line

C intermediate circuit capacitor

C1 first capacitor

C2 second capacitor

G ground

M three-phase motor

u, v, w phase