阅读说明：本技术 沟渠式金氧半p-n接面二极管制作方法 (Method for manufacturing trench type metal oxide semiconductor P-N junction diode ) 是由 陈美玲 于 2013-12-20 设计创作，主要内容包括：本发明公开一种沟渠式金氧半P-N接面二极管制作方法,包含一第一导电型基板；多个的沟渠结构,形成于该第一导电型基板的表面上；一栅极氧化层,至少形成于该沟渠结构内侧壁上；一多晶硅层,形成于该沟渠结构内；一第二导电型第二浓度离子注入区域,至少形成于第一导电型基板中；一第二导电型第一浓度离子注入区域,形成于该沟渠结构底表面下,所述第一浓度高于第二浓度；及一电极层,覆盖于该第一导电型基板、该第二导电型第二浓度离子注入区域、该栅极氧化层及该多晶硅层上。位于沟渠结构底壁下的第一浓度离子注入区域可在反向偏压时提供夹止区电压支撑,因此可以降低此二极管结构的漏电流。(The invention discloses a method for manufacturing a trench type metal oxide semiconductor P-N junction diode, which comprises a first conductive substrate; a plurality of trench structures formed on the surface of the first conductive substrate; a gate oxide layer at least formed on the inner sidewall of the trench structure; a polysilicon layer formed in the trench structure; a second conductive type second concentration ion implantation region at least formed in the first conductive type substrate; a second conductive type first concentration ion implantation area formed under the bottom surface of the trench structure, wherein the first concentration is higher than the second concentration; and an electrode layer covering the first conductive substrate, the second conductive second concentration ion implantation region, the gate oxide layer and the polysilicon layer. The first concentration ion implantation region under the bottom wall of the trench structure can provide voltage support for the clamping region during reverse bias, thereby reducing the leakage current of the diode structure.)

1. A method for fabricating a trench MOS P-N junction diode structure includes the following sequential steps:

(a) providing a first conductive substrate;

(b) forming a plurality of trench structures in the device region on the surface of the first conductive substrate;

(b1) performing a second conductivity type second concentration ion implantation process on the trench structure to form a second conductivity type second concentration ion implantation region in the first conductivity type substrate, wherein the trench structure has ion implantation portions on the sidewall and bottom surface thereof;

(b2) performing anisotropic etching on the trench structure to remove a second conductivity type second concentration ion implantation region portion on the bottom surface of the trench structure and form a second conductivity type second concentration ion implantation region outside the sidewall of the trench structure;

(b3) performing an oxygen-introducing heating process in the trench structure to form a sacrificial oxide layer on the inner side wall and the bottom of the trench structure;

(b4) performing an ion implantation process in the trench structure to form a second conductive type first concentration ion implantation region at the bottom of the trench structure, wherein the first concentration is higher than the second concentration;

(b5) removing the sacrificial oxide layer;

(c) forming a gate oxide layer on the inner side wall of the trench structure, wherein a gate oxide layer structure is formed on the inner wall of the trench structure and the part containing the bottom surface, and then removing the gate oxide layer on the bottom surface to form the gate oxide layer on the inner side wall of the trench structure;

(d) forming a polysilicon layer in the trench structure, wherein the polysilicon layer is surrounded by the gate oxide layer on at least part of the side surface;

(d1) removing part of the polysilicon layer by an etch-back method, and covering a TEOS oxide layer on part of the trench structure, wherein the trench structure covered by the TEOS oxide layer also has a second conductive type second concentration ion implantation region outside the sidewall and a second conductive type first concentration ion implantation region at the bottom;

(e) forming an electrode layer covering the first conductive substrate, the second conductive second concentration ion implantation region, the gate oxide layer, the polysilicon layer and the TEOS oxide layer;

the second conductive type second concentration ion implantation area is formed on only part of the exposed surface of the first conductive type substrate, and the second conductive type second concentration ion implantation area is formed on the extending depth of the first conductive type substrate and does not exceed the bottom surface of the trench structure.

2. The method as claimed in claim 1, wherein the polysilicon layer directly contacts the second conductivity type first concentration ion implantation region.

3. The method as claimed in claim 1, wherein the gate oxide layer is also formed on the bottom surface of the trench structure, and the second conductive type first concentration ion implantation region is formed under the gate oxide layer.

4. The method as claimed in claim 1, wherein the second conductivity type second concentration ion implantation region has a dopant amount of 10¹²cm^-2The doping amount of the second conductive type first concentration ion implantation region is 10^13-16cm^-2。

Technical Field

The invention relates to a method for manufacturing a metal oxide semiconductor P-N junction diode structure, in particular to a method for manufacturing a trench type metal oxide semiconductor P-N junction diode structure.

Background

The Schottky diode is a unipolar element with electrons as carriers and features high speed and forward conduction voltage drop (V)_F) Low, but large reverse bias leakage current (related to the schottky barrier caused by the metal work function and the semiconductor doping concentration). The P-N diode, a bipolar device, conducts large amounts of current. But the forward operating pressure drop value (V) of the element_F) Generally higher than the Schottky diode, and the reaction speed of the P-N diode is slower and the reverse recovery time is longer due to the action of the hole carrier.

In addition to schottky diodes as rectifier diodes, active devices (such as mos transistors) may be further processed to fabricate mos P-N junction rectifier diodes. U.S. patent publication No. 2912/9156862 discloses a trench mos P-N junction diode structure, which mainly uses a trench structure to fabricate a gate oxide layer to increase the device density. However, in the above-mentioned prior art, there is a problem that the leakage current is large when the reverse bias is applied.

Disclosure of Invention

The present invention provides a trench MOS P-N junction diode structure and a method for fabricating the same, which can reduce the leakage current of the diode structure.

To achieve the above objective, the present invention provides a trench mos P-N junction diode structure, which includes a first conductive substrate; a plurality of trench structures formed on the surface of the first conductive substrate; a gate oxide layer at least formed on the inner sidewall of the trench structure; a polysilicon layer formed in the trench structure and surrounded by the gate oxide layer at least partially on the side surface; a second conductive type second concentration ion implantation area at least formed in the first conductive type substrate and outside the gate oxide layer; a second conductive type first concentration ion implantation area formed under the bottom surface of the trench structure, wherein the first concentration is higher than the second concentration; and an electrode layer covering the first conductive substrate, the second conductive second concentration ion implantation region, the gate oxide layer and the polysilicon layer.

Wherein the polysilicon layer is in direct contact with the second conductive type first concentration ion implantation region.

Wherein the gate oxide layer is also formed on the bottom surface of the trench structure, and the second conductive type first concentration ion implantation region is formed under the gate oxide layer.

Wherein, in the device region of the trench MOS P-N junction diode structure, the second conductive type second concentration ion implantation region is formed on the whole exposed surface of the first conductive type substrate.

Wherein the second conductive type second concentration ion implantation region has a dopant amount of 10¹²cm^-2The doping amount of the second conductive type first concentration ion implantation region is 10¹³-16cm^-2。

Furthermore, the present invention also provides a method for fabricating a trench MOS P-N junction diode structure, comprising: providing a first conductive substrate; forming a plurality of trench structures on the surface of the first conductive substrate; forming a second conductive type second concentration ion implantation region outside the side wall of the trench structure; forming a second conductive type first concentration ion implantation area at the bottom of the ditch structure, wherein the first concentration is higher than the second concentration; forming a gate oxide layer on the inner sidewall of the trench structure; forming a polysilicon layer in the trench structure, wherein the polysilicon layer is surrounded by the gate oxide layer on at least part of the side surface; forming an electrode layer covering the first conductive substrate, the second conductive second concentration ion implantation region, the gate oxide layer and the polysilicon layer.

Wherein the polysilicon layer is in direct contact with the second conductive type first concentration ion implantation region.

Wherein the gate oxide layer is also formed on the bottom surface of the trench structure, and the second conductive type first concentration ion implantation region is formed under the gate oxide layer.

Wherein, in the device region of the trench MOS P-N junction diode structure, the second conductive type second concentration ion implantation region is formed on the whole exposed surface of the first conductive type substrate.

Wherein the second conductive type second concentration ion implantation region has a dopant amount of 10¹²cm^-2The doping amount of the second conductive type first concentration ion implantation region is 10^13-16cm^-2。

Since the first concentration ion implantation region under the bottom wall of the trench structure can provide the voltage support of the clamping region during reverse bias, the leakage current of the diode structure can be reduced.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1 is a schematic view of a trench MOS P-N junction diode structure according to a first embodiment of the present invention.

FIGS. 2A to 2N are schematic views illustrating a method for fabricating a trench MOS P-N junction diode structure according to a first embodiment of the present invention.

FIG. 3 is a diagram illustrating a trench MOS P-N junction diode structure according to a second embodiment of the present invention.

FIGS. 4A to 4N are schematic views illustrating a method for fabricating a trench MOS P-N junction diode structure according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a trench MOS P-N junction diode structure according to a third embodiment of the present invention.

FIGS. 6A to 6L are schematic flow charts of a method for fabricating a trench MOS P-N junction diode structure according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a trench MOS P-N junction diode structure according to a fourth embodiment of the present invention.

FIGS. 8A to 8L are schematic views illustrating a manufacturing method of a trench MOS P-N junction diode structure according to a fourth embodiment of the present invention.

Wherein, the reference numbers:

20 base plate

201 high doping concentration N-type silicon substrate

202 low doping concentration N type epitaxial layer

210 oxide layer

211,214,216 Photoresist Pattern

212 oxide pattern

34 sacrificial oxide layer

30 trench structure

32,35 second concentration ion implantation region

36 first concentration ion implantation region

40 grid oxide layer

42 polysilicon layer

44 TEOS oxide layer

5 electrode layer

50 first metal layer

52 second metal layer

Detailed Description

Referring to fig. 1, a schematic diagram of a first embodiment of a trench mos P-N junction diode structure developed to improve the defects generated by the prior art is shown. The trench mos P-N junction diode structure mainly includes a substrate 20 (including a high-doping concentration N-type silicon substrate 201 and a low-doping concentration N-type epitaxial layer (low-doping concentration N-type epitaxial layer) 202), a plurality of trench structures (see fig. 2C, reference numeral 30) formed on the low-doping concentration N-type epitaxial layer 202, a first concentration (high concentration) ion implantation region 36 located under the bottom wall of the trench structure, a gate oxide layer 40 located on the inner side wall of the trench structure, a polysilicon layer 42 filled in the trench structure, and a second concentration (low concentration) ion implantation region 32 located outside the trench structure and outside the gate oxide layer 40. Furthermore, the left side of the dotted line is the device region, and the right side of the dotted line is the termination region. The low dopant concentration N-type epitaxial layer 202 without the trench structure at the termination structure region has an oxide pattern 212 thereon, and the trench structure and the oxide pattern 212 at the termination structure region have a TEOS oxide layer 44 thereon. The trench MOS P-N junction diode structure further has an electrode layer 5 (including a first metal layer 50 and a second metal layer 52) on the low-doped N-type epitaxial layer 202 and the polysilicon layer 42 of the device region, and the electrode structure extends to a portion of the termination structure region.

Please refer to fig. 2A to 2N, which are schematic flow charts of a method for fabricating a trench mos P-N junction diode structure according to a first preferred embodiment of the present invention. As can be clearly seen from the figure, first, a substrate 20 (as shown in fig. 2A) is provided, the substrate 20 includes a high-dopant concentration N-type silicon substrate 201(N + silicon substrate) and a low-dopant concentration N-type epitaxial layer 202 (N-epitaxial layer); and a first oxide layer 210 is formed on the substrate 20 through an oxidation process.

Then, as shown in fig. 2B, a photoresist layer is formed on the oxide layer 210; defining a photoresist pattern 211 on the photoresist layer, wherein the portion uncovered by the photoresist pattern 211 corresponds to a trench structure to be formed in the future; the first oxide layer 210 is etched using the photoresist pattern 211 to form a first oxide pattern 212. Subsequently, as shown in fig. 2C, after the remaining photoresist pattern 211 is removed, the low-dopant concentration N-type epitaxial layer 202 is etched using the exposed first oxide pattern 212 to form a trench structure 30. Next, as shown in FIG. 2D, a low concentration of P-type ions (e.g., 10 dose) is performed on the trench structure 30¹²cm^-2Boron ions) implantation process to form a second concentration (low concentration) ion implantation region 32 in the low doping concentration N-type epitaxial layer 202, at which stage there is an ion implantation portion on both the inner sidewall and bottom surface of the trench structure 30.

Subsequently, as shown in fig. 2E, performing anisotropic etching (anisotropic etching) on the trench structure 30 to remove the ion implantation portion on the bottom surface of the trench structure 30; then, an oxygen-filling heating process is performed in the trench structure 30, so as to form a sacrificial oxide layer 34 on the inner sidewall and the bottom of the trench structure 30, thereby smoothing the inner sidewall and the bottom surface of the trench structure 30; followed by the trench structure30, an ion implantation process is performed to form a first concentration (high concentration) ion implantation region 36 (e.g., 10 dose) at the bottom of the trench structure 30^13-16cm^-2Boron ions, as shown in fig. 2F).

Subsequently, as shown in fig. 2G, after removing the sacrificial oxide layer 34, a gate oxide layer structure is formed on the inner wall (including the bottom surface) of the trench structure 30 by thermal oxidation, and then the gate oxide layer on the bottom surface is removed to form the gate oxide layer 40 on the inner sidewall of the trench structure 30 as shown in fig. 2G.

Subsequently, as shown in fig. 2H, a polysilicon layer 42 is deposited on the oxide pattern 212 and in the trench structure 30 by a Chemical Vapor Deposition (CVD). The polysilicon layer 42 contacts the gate oxide layer 40 on the inner sidewall of the trench structure 30 and the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure 30. After the polysilicon layer 42 is formed, an ion drive-in step is performed.

Subsequently, as shown in fig. 2I, the polysilicon layer 42 deposited on the oxide pattern 212 is removed by an Etch back (Etch back); a low pressure chemical vapor deposition (LP CVD) is then performed on the resulting structure to form a Tetraoxyethylsilane (TEOS) oxide layer 44 over the oxide pattern 212 and the polysilicon layer 42 within the trench structure 30. As shown in fig. 2J, a photoresist layer is formed on the TEOS oxide layer 44, and a photoresist pattern 214 is defined on the photoresist layer.

Then, as shown in fig. 2K, the TEOS oxide layer 44 and the oxide pattern 212, which are not shielded by the photoresist pattern 214, are etched using the photoresist pattern 214 as a mask to expose the polysilicon layer 42, the gate oxide layer 40 on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 32 in the inner sidewall of the trench structure 30, and a portion of the upper surface of the low-doping-concentration N-type epitaxial layer 202. After the etching step, the photoresist pattern 214 is removed.

As shown in fig. 2L, a first metal layer 50 is formed on the polysilicon layer 42, the gate oxide layer 40 located on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 32 located in the inner sidewall of the trench structure 30, the exposed N-type epitaxial layer 202 with low doping concentration, and the sidewall portion originally shielded by the photoresist, wherein the first metal layer 50 is mainly made of titanium (Ti) or titanium nitride (TiN); then, a second metal layer 52 is formed on the first metal layer 50, wherein the second metal layer 52 is mainly made of aluminum or other metals.

Then, as shown in fig. 2M, a photoresist layer is formed on the second metal layer 52, a photoresist pattern 216 is defined on the photoresist layer, and the remaining photoresist layer 216 is removed after etching the second metal layer 52 and the first metal layer 50 according to the photoresist pattern 216, thereby completing the mos P-N junction diode structure shown in fig. 2N.

In the trench mos P-N junction diode structure, the trench structure 30 can transform the originally horizontal gate oxide layer into the vertically extending gate oxide layer 40, so that a large area of the gate oxide layer 40 is formed on the limited N-type epitaxial layer 202 with low doping concentration, thereby increasing the device density. Furthermore, the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure can provide a voltage support for the clamp region during reverse bias, thereby reducing leakage current.

Fig. 3 is a schematic diagram of a trench mos P-N junction diode structure according to a second preferred embodiment of the invention, which mainly includes a substrate 20 (including a high-doping concentration N-type silicon substrate 201 and a low-doping concentration N-type epitaxial layer 202), a plurality of trench structures (see fig. 4C, reference numeral 30) formed on the low-doping concentration N-type epitaxial layer 202, a gate oxide layer 40 located on the inner sidewall (including the bottom sidewall) of the trench structures, a first concentration (high concentration) ion implantation region 36 located under the gate oxide layer under the bottom wall of the trench structures, a polysilicon layer 42 filled in the trench structures, and a second concentration (low concentration) ion implantation region 32 located outside the trench structures and outside the gate oxide layer 40. Furthermore, as shown in FIG. 3, the device region is located on the left side of the dotted line, and the termination region is located on the right side of the dotted line. The low dopant concentration N-type epitaxial layer 202 without the trench structure at the termination structure region has an oxide pattern 212 thereon, and the trench structure and the oxide pattern 212 at the termination structure region have a TEOS oxide layer 44 thereon. The trench MOS P-N junction diode structure further has an electrode layer 5 (including a first metal layer 50 and a second metal layer 52) on the low-doped N-type epitaxial layer 202 and the polysilicon layer 42 of the device region, and the electrode structure extends to a portion of the termination structure region.

Please refer to fig. 4A to 4N, which are schematic flow charts illustrating a method for fabricating a trench mos P-N junction diode structure according to a second preferred embodiment of the present invention, wherein fig. 4A to 4F are similar to the first embodiment and therefore will not be described again.

After removing the sacrificial oxide layer 34, a gate oxide layer 40 is formed on the inner wall (including the bottom surface) of the trench structure 30 by thermal oxidation, as shown in fig. 4G.

Subsequently, as shown in fig. 4H, a polysilicon layer 42 is deposited on the oxide pattern 212 and in the trench structure 30 by a Chemical Vapor Deposition (CVD). The polysilicon layer 42 contacts the gate oxide layer 40 on the inner sidewalls of the trench structure 30. After the polysilicon layer 42 is formed, an ion drive-in step is performed.

Subsequently, as shown in fig. 4I, the polysilicon layer 42 deposited on the oxide pattern 212 is removed by an Etch back (Etch back); a low pressure chemical vapor deposition (LP CVD) is then performed on the resulting structure to form a Tetraoxyethylsilane (TEOS) oxide layer 44 over the oxide pattern 212 and the polysilicon layer 42 within the trench structure 30. As shown in fig. 4J, a photoresist layer is formed on the TEOS oxide layer 44, and a photoresist pattern 214 is defined on the photoresist layer.

Then, as shown in fig. 4K, the TEOS oxide layer 44 and the oxide pattern 212, which are not shielded by the photoresist pattern 214, are etched using the photoresist pattern 214 as a mask to expose the polysilicon layer 42, the gate oxide layer 40 on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 32 in the inner sidewall of the trench structure 30, and a portion of the upper surface of the low-doping-concentration N-type epitaxial layer 202. After the etching step, the photoresist pattern 214 is removed.

As shown in fig. 4L, a first metal layer 50 is formed on the polysilicon layer 42, the gate oxide layer 40 located on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 32 located in the inner sidewall of the trench structure 30, the exposed N-type epitaxial layer 202 with low doping concentration, and the sidewall portion originally shielded by the photoresist, wherein the first metal layer 50 is mainly made of titanium (Ti) or titanium nitride (TiN); then, a second metal layer 52 is formed on the first metal layer 50, wherein the second metal layer 52 is mainly made of aluminum or other metals.

Subsequently, as shown in fig. 4M, a photoresist layer is formed on the second metal layer 52, a photoresist pattern 216 is defined on the photoresist layer, and the remaining photoresist layer 216 is removed after etching the second metal layer 52 and the first metal layer 50 according to the photoresist pattern 216, thereby completing the mos P-N junction diode structure 60 shown in fig. 4N.

In the trench mos P-N junction diode structure, the trench structure 30 can transform the originally horizontal gate oxide layer into the vertically extending gate oxide layer 40, so that a large area of the gate oxide layer 40 is formed on the limited N-type epitaxial layer 202 with low doping concentration, thereby increasing the device density. Furthermore, the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure can provide a voltage support for the clamp region during reverse bias, thereby reducing leakage current.

Fig. 5 is a schematic diagram of a trench mos P-N junction diode structure according to a third preferred embodiment of the invention, which mainly includes a substrate 20 (including a high-doping concentration N-type silicon substrate 201 and a low-doping concentration N-type epitaxial layer 202), a plurality of trench structures (see fig. 6C, reference numeral 30) formed on the low-doping concentration N-type epitaxial layer 202, a first concentration (high concentration) ion implantation region 36 located under the bottom wall of the trench structure, a gate oxide layer 40 located on the inner sidewall of the trench structure, a polysilicon layer 42 filled in the trench structure, and a second concentration (low concentration) ion implantation region 35 located outside the trench structure and outside the gate oxide layer 40. Furthermore, as shown in fig. 6L, the device region is located on the left side of the dotted line, and the termination region is located on the right side of the dotted line. The low dopant concentration N-type epitaxial layer 202 without the trench structure at the termination structure region has an oxide pattern 212 thereon, and the trench structure and the oxide pattern 212 at the termination structure region have a TEOS oxide layer 44 thereon. The trench MOS P-N junction diode structure further has an electrode structure (including a first metal layer 50 and a second metal layer 52) on the low-doped N-type epitaxial layer 202 and the polysilicon layer 42 of the device region, and the electrode structure extends to a portion of the termination structure region.

Please refer to fig. 6A to 6L, which are schematic flow charts of a method for fabricating a trench mos P-N junction diode structure according to a third preferred embodiment of the present invention. As can be clearly seen from the figure, first, a substrate 20 (as shown in fig. 6A) is provided, the substrate 20 includes a high-dopant concentration N-type silicon substrate 201(N + silicon substrate) and a low-dopant concentration N-type epitaxial layer 202 (N-epitaxial layer); and a first oxide layer 210 is formed on the substrate 20 through an oxidation process.

Then, as shown in fig. 6B, a photoresist layer is formed on the oxide layer 210; defining a photoresist pattern 211 on the photoresist layer, wherein the portion uncovered by the photoresist pattern 211 corresponds to a trench structure to be formed in the future; the first oxide layer 210 is etched using the photoresist pattern 211 to form a first oxide pattern 212. Subsequently, as shown in fig. 6C, after the remaining photoresist pattern 211 is removed, the low-dopant concentration N-type epitaxial layer 202 is etched using the exposed first oxide pattern 212 to form a trench structure 30. As shown in fig. 6D, an oxygen-filling heating process is performed in the trench structure 30 to form a sacrificial oxide layer 34 on the inner sidewall and the bottom of the trench structure 30, so that the inner sidewall and the bottom surface of the trench structure 30 become smoother; an ion implantation process is then performed in the trench structure 30 to form a first concentration (high concentration) ion implantation region 36 (e.g., with a dose of 10) at the bottom of the trench structure 30^13-16cm^-2Boron ions).

Subsequently, as shown in fig. 6E, after removing the sacrificial oxide layer 34, a gate oxide layer structure is formed on the inner wall (including the bottom surface) of the trench structure 30 by thermal oxidation, and then the gate oxide layer on the bottom surface is removed to form the gate oxide layer 40 on the inner sidewall of the trench structure 30.

Subsequently, as shown in fig. 6F, a polysilicon layer 42 is deposited on the oxide pattern 212 and in the trench structure 30 by a Chemical Vapor Deposition (CVD). The polysilicon layer 42 contacts the gate oxide layer 40 on the inner sidewall of the trench structure 30 and the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure 30.

Subsequently, as shown in fig. 6G, the polysilicon layer 42 formed on the oxide pattern 212 is removed by an Etch back (Etch back); a low pressure chemical vapor deposition (LP CVD) is then performed on the resulting structure to form a Tetraoxyethylsilane (TEOS) oxide layer 44 over the oxide pattern 212 and the polysilicon layer 42 within the trench structure 30. As shown in fig. 6H, a photoresist layer is formed on the TEOS oxide layer 44, and a photoresist pattern 214 is defined on the photoresist layer.

Then, as shown in fig. 6I, the TEOS oxide layer 44 and the oxide pattern 212, which are not masked by the photoresist pattern 214, are etched using the photoresist pattern 214 as a mask to expose the polysilicon layer 42, the gate oxide layer 40 on the inner sidewall of the trench structure 30, and the upper surface of the N-type epitaxial layer 202 with low doping concentration. After the etching step, the photoresist pattern 214 is removed. Then, a low concentration P-type ion (e.g., 10 dose) is performed on the upper surface of the low doping concentration N-type epitaxial layer 202¹²cm^-2Boron ions) implantation process to form a second concentration (low concentration) ion implantation region 35 in the low doping concentration N-type epitaxial layer 202. The second concentration (low concentration) ion implantation region 35 is different from the second concentration (low concentration) ion implantation region 32 shown in fig. 2E in that the second concentration (low concentration) ion implantation region 35 substantially covers the entire exposed upper surface of the low doping concentration N-type epitaxial layer 202.

As shown in fig. 6J, a first metal layer 50 is formed on the polysilicon layer 42, the gate oxide layer 40 located on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 35 located in the inner sidewall of the trench structure 30, the exposed N-type epitaxial layer 202 with low doping concentration, and the sidewall portion originally shielded by the photoresist, wherein the first metal layer 50 is mainly made of titanium (Ti) or titanium nitride (TiN); then, a second metal layer 52 is formed on the first metal layer 50, wherein the second metal layer 52 is mainly made of aluminum or other metals.

Then, as shown in fig. 6K, a photoresist layer is formed on the second metal layer 52, a photoresist pattern 216 is defined on the photoresist layer, and the remaining photoresist layer 216 is removed after etching the second metal layer 52 and the first metal layer 50 according to the photoresist pattern 216, thereby completing the mos P-N junction diode structure shown in fig. 6L.

As shown in fig. 6L, in the above-mentioned trench mos P-N junction diode structure, the trench structure 30 can transform the originally horizontal gate oxide layer into the vertically extending gate oxide layer 40, so that a large area of gate oxide layer 40 is formed on the limited N-type epitaxial layer 202 with low doping concentration, thereby increasing the device density. Furthermore, the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure can provide a voltage support for the clamp region during reverse bias, thereby reducing leakage current.

Fig. 7 is a schematic diagram of a trench mos P-N junction diode structure according to a fourth preferred embodiment of the invention, which mainly includes a substrate 20 (including a high-doping concentration N-type silicon substrate 201 and a low-doping concentration N-type epitaxial layer 202), a plurality of trench structures (see fig. 8C, reference numeral 30) formed on the low-doping concentration N-type epitaxial layer 202, a first concentration (high concentration) ion implantation region 36 located under the bottom wall of the trench structure, a gate oxide layer 40 located on the inner side wall and the bottom wall of the trench structure, a polysilicon layer 42 filled in the trench structure, and a second concentration (low concentration) ion implantation region 35 located outside the trench structure and outside the gate oxide layer 40. Furthermore, as shown in fig. 6L, the device region is located on the left side of the dotted line, and the termination region is located on the right side of the dotted line. The low dopant concentration N-type epitaxial layer 202 without the trench structure at the termination structure region has an oxide pattern 212 thereon, and the trench structure and the oxide pattern 212 at the termination structure region have a TEOS oxide layer 44 thereon. The trench MOS P-N junction diode structure further has an electrode structure (including a first metal layer 50 and a second metal layer 52) on the low-doped N-type epitaxial layer 202 and the polysilicon layer 42 of the device region, and the electrode structure extends to a portion of the termination structure region.

Please refer to fig. 8A to 8L, which are schematic flow charts illustrating a method for fabricating a trench mos P-N junction diode structure according to a fourth preferred embodiment of the present invention, wherein fig. 8A to 8D are similar to the third embodiment and therefore will not be described again.

After removing the sacrificial oxide layer 34, a gate oxide layer structure is formed on the inner wall (including the bottom surface) of the trench structure 30 by thermal oxidation to form a gate oxide layer 40 on the inner sidewall and the bottom wall of the trench structure 30, as shown in fig. 8E.

Subsequently, as shown in fig. 8F, a polysilicon layer 42 is deposited on the oxide pattern 212 and in the trench structure 30 by a Chemical Vapor Deposition (CVD). The polysilicon layer 42 contacts the gate oxide layer 40 on the inner sidewalls and bottom wall of the trench structure 30.

Subsequently, as shown in fig. 8G, the polysilicon layer 42 formed on the oxide pattern 212 is removed by an Etch back (Etch back); a low pressure chemical vapor deposition (LP CVD) is then performed on the resulting structure to form a Tetraoxyethylsilane (TEOS) oxide layer 44 over the oxide pattern 212 and the polysilicon layer 42 within the trench structure 30. As shown in fig. 8H, a photoresist layer is formed on the TEOS oxide layer 44, and a photoresist pattern 214 is defined on the photoresist layer.

Then, as shown in FIG. 8I, the TEOS oxide layer 44 and the oxide pattern 212 not shielded by the photoresist pattern 214 are etched using the photoresist pattern 214 as a mask to expose the polysilicon layer 42, the gate oxide layer 40 on the inner sidewall of the trench structure 30, and the low-doped N-type epitaxy layerThe upper surface of layer 202. After the etching step, the photoresist pattern 214 is removed. Then, a low concentration P-type ion (e.g., 10 dose) is performed on the upper surface of the low doping concentration N-type epitaxial layer 202¹²cm^-2Boron ions) implantation process to form a second concentration (low concentration) ion implantation region 35 in the low doping concentration N-type epitaxial layer 202. The second concentration (low concentration) ion implantation region 35 is different from the second concentration (low concentration) ion implantation region 32 shown in fig. 2E in that the second concentration (low concentration) ion implantation region 35 substantially covers the entire exposed upper surface of the low doping concentration N-type epitaxial layer 202.

As shown in fig. 8J, a first metal layer 50 is formed on the polysilicon layer 42, the gate oxide layer 40 located on the inner sidewall of the trench structure 30, the second-concentration (low-concentration) ion implantation region 35 located in the inner sidewall of the trench structure 30, the exposed N-type epitaxial layer 202 with low doping concentration, and the sidewall portion originally shielded by the photoresist, wherein the first metal layer 50 is mainly made of titanium (Ti) or titanium nitride (TiN); then, a second metal layer 52 is formed on the first metal layer 50, wherein the second metal layer 52 is mainly made of aluminum or other metals.

Then, as shown in fig. 8K, a photoresist layer is formed on the second metal layer 52, a photoresist pattern 216 is defined on the photoresist layer, and the remaining photoresist layer 216 is removed after etching the second metal layer 52 and the first metal layer 50 according to the photoresist pattern 216, thereby completing the mos P-N junction diode structure shown in fig. 8L.

As shown in fig. 8L, in the above-mentioned trench mos P-N junction diode structure, the trench structure 30 can transform the originally horizontal gate oxide layer into the vertically extending gate oxide layer 40, so that a large area of gate oxide layer 40 is formed on the limited N-type epitaxial layer 202 with low doping concentration, thereby increasing the device density. Furthermore, the first concentration (high concentration) ion implantation region 36 under the bottom wall of the trench structure can provide a voltage support for the clamp region during reverse bias, thereby reducing leakage current.

In view of the above description, it can be clearly understood that the trench MOS P-N junction diode structure of the present invention can provide a clamp region voltage support during reverse bias, thereby reducing leakage current, compared to the conventional MOS P-N junction diode structure.

The present invention is capable of other embodiments, and various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.