阅读说明：本技术 半导体结构及其制作方法 (Semiconductor structure and manufacturing method thereof ) 是由 叶柏良 吴振中 邓德彰 张家铭 于 2019-10-18 设计创作，主要内容包括：一种半导体结构及其制作方法,其中半导体结构配置于基板上,包括第一金属层设置于基板上、栅绝缘层设置于基板上、氧化物半导体层设置于栅绝缘层上、蚀刻阻挡图案设置于氧化物半导体层上以及第二金属层设置于蚀刻阻挡图案上。第一金属层包括栅极线。栅绝缘层覆盖栅极线。氧化物半导体层的图案化定义出氧化物半导体图案。第二金属层包括源极与漏极电性连接至氧化物半导体图案。部分蚀刻阻挡图案位于第二金属层与氧化物半导体层之间。第二金属层还包括信号线设置于蚀刻阻挡图案上并电性连接氧化物半导体图案。一种半导体结构的制作方法亦被提出。(A semiconductor structure and a manufacturing method thereof are provided, wherein the semiconductor structure is arranged on a substrate and comprises a first metal layer arranged on the substrate, a gate insulating layer arranged on the substrate, an oxide semiconductor layer arranged on the gate insulating layer, an etching barrier pattern arranged on the oxide semiconductor layer and a second metal layer arranged on the etching barrier pattern. The first metal layer includes a gate line. The gate insulating layer covers the gate line. The patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer comprises a source electrode and a drain electrode which are electrically connected to the oxide semiconductor pattern. The partial etching barrier pattern is positioned between the second metal layer and the oxide semiconductor layer. The second metal layer further comprises a signal line arranged on the etching barrier pattern and electrically connected with the oxide semiconductor pattern. A method for fabricating a semiconductor structure is also provided.)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first metal layer on the substrate and patterning the first metal layer to define a gate line and a shielding metal pattern, wherein the gate line is electrically connected with a gate;

forming a gate insulating layer on the substrate and covering the gate line and the shielding metal pattern;

forming an oxide semiconductor material layer on the gate insulating layer;

annealing the oxide semiconductor material layer;

forming an etch stop material layer on the oxide semiconductor material layer;

forming a photoresist material layer on the etching barrier material layer;

defining the photoresist material layer by using a half-tone mask to form a photoresist pattern;

patterning the etch stop material layer using the photoresist pattern as a mask to form an etch stop pattern;

patterning the oxide semiconductor material layer by using the photoresist pattern as a mask to form an oxide semiconductor layer and define a first opening, wherein the first opening overlaps the gate insulating layer;

performing an ashing process to remove the photoresist pattern;

patterning the gate insulating layer by using the etching barrier pattern as a mask to form a first contact window overlapping the shielding metal pattern, wherein an orthographic projection of the first contact window on the substrate is located within an orthographic projection of the first opening on the substrate;

forming a second metal layer on the etching barrier pattern and patterning the second metal layer to define a source electrode, a drain electrode, a signal line and a data line, wherein part of the etching barrier pattern is located between the second metal layer and the oxide semiconductor layer, and the data line is electrically connected to the shielding metal pattern through the first contact window; and

the oxide semiconductor layer is patterned to define an oxide semiconductor pattern, and the source electrode, the drain electrode and the signal line are electrically connected to the oxide semiconductor pattern.

2. The method of fabricating a semiconductor structure according to claim 1, further comprising:

forming a first planarization layer on the etching barrier pattern, covering a part of the gate insulating layer, the etching barrier pattern and the second metal layer, wherein the first planarization layer has a second contact window;

forming a color resistance layer on the first flat layer, wherein the color resistance layer is provided with a second opening overlapping the second contact window, and the orthographic projection of the second contact window on the substrate is positioned in the orthographic projection of the second opening on the substrate;

forming a second flat layer on the color resistance layer, wherein the second flat layer is provided with a third opening overlapping the second contact window; and

and forming a pixel electrode on the second flat layer, wherein the pixel electrode is electrically connected to the drain electrode through the second contact window.

3. The method according to claim 1, wherein the oxide semiconductor material layer comprises a stack of one or more selected from indium gallium zinc oxide, indium gallium oxide, and indium tin zinc oxide.

4. The method according to claim 1, wherein the etch stop material layer comprises hafnium oxide, silicon oxide or aluminum oxide.

5. The method according to claim 1, further comprising performing an electrical test to inspect the source, the drain and the signal line after the step of defining the oxide semiconductor pattern.

6. A semiconductor structure disposed on a substrate, comprising:

a first metal layer disposed on the substrate, the first metal layer including a gate line electrically connected to a gate electrode;

a gate insulating layer disposed on the substrate and covering the gate line, the gate insulating layer having a first contact window overlapping the first metal layer;

an oxide semiconductor layer disposed on the gate insulating layer, the oxide semiconductor layer having a first opening, and an oxide semiconductor pattern defined by patterning the oxide semiconductor layer;

an etch stop pattern disposed on the oxide semiconductor layer and on a portion of the oxide semiconductor pattern; and

a second metal layer disposed on the etching barrier pattern, the second metal layer including a source and a drain electrically connected to the oxide semiconductor pattern, and a portion of the etching barrier pattern being between the second metal layer and the oxide semiconductor layer,

the second metal layer also includes a signal line disposed on the etching barrier pattern and electrically connected to the oxide semiconductor pattern, and the second metal layer is electrically connected to the first metal layer through the first contact hole.

7. The semiconductor structure of claim 6, wherein the first metal layer further comprises a shielding metal pattern, the second metal layer further comprises a data line, and the etching stop pattern and the oxide semiconductor layer are sandwiched between the data line and the shielding metal pattern.

8. The semiconductor structure of claim 7, wherein the data line is electrically connected to the shielding metal pattern through the first contact via, and an orthogonal projection of the first contact via on the substrate is located within an orthogonal projection of the first opening on the substrate.

9. The semiconductor structure of claim 6, further comprising:

a first flat layer disposed on the etching barrier pattern and covering a part of the gate insulating layer, the etching barrier pattern, and the second metal layer, the first flat layer having a second contact window;

a color resistance layer arranged on the first flat layer, the color resistance layer having a second opening overlapping the second contact window;

a second flat layer disposed on the color resistance layer, the second flat layer having a third opening overlapping the second contact window; and

a pixel electrode disposed on the second planarization layer and electrically connected to the drain electrode through the second contact window.

10. The semiconductor structure of claim 6, wherein a short side of an orthographic projection of said oxide semiconductor pattern on said substrate is parallel to a long side of an orthographic projection of said signal line overlapping said oxide semiconductor pattern on said substrate, and a distance between said short side and said long side is 0.5 to 1 μm.

11. The semiconductor structure of claim 6, wherein the other short side of the orthographic projection of the oxide semiconductor pattern on the substrate is parallel to one long side of the orthographic projection of the source electrode on the substrate, and the distance between the other short side and the long side is 0.5 microns to 1 micron.

Technical Field

The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure including an etch stop pattern and a method for fabricating the same.

Background

With the advancement of modern information technology, displays of various specifications have been widely used in screens of consumer electronic products. In the market trend, the process of fabricating high-quality Liquid Crystal Displays (LCDs) and Organic electroluminescent displays (OELDs or OLEDs) includes arranging an array of semiconductor devices including Thin Film Transistors (TFTs) and pixel structures on a substrate.

In general, a metal oxide semiconductor layer is used for a thin film transistor of a high-definition display. A metal Oxide semiconductor layer (e.g., Indium Gallium Zinc Oxide (IGZO)) generates carriers (electrons) due to oxygen vacancy, and thus is in an on state, and a threshold voltage (Vt) is generally negative, which may cause a leakage current problem. Therefore, the conventional process method cannot perform the open-circuit and short-circuit test and the wire repair procedure after the source and drain electrodes and other signal wires connected to the metal oxide semiconductor layer are manufactured in the same layer. Therefore, how to develop a semiconductor structure with excellent electrical characteristics and convenient inspection and repair processes is one of the goals that developers want to achieve.

Disclosure of Invention

The invention provides a semiconductor structure and a manufacturing method thereof, which are suitable for conveniently carrying out detection and repair procedures, have excellent electrical property, and can reduce the number of masks and reduce the cost.

The manufacturing method of the semiconductor structure comprises the following steps. A substrate is provided. A first metal layer is formed on the substrate and patterned to define a gate line and a shielding metal pattern. A gate insulating layer is formed on the substrate and covers the gate line and the shielding metal pattern. And forming an oxide semiconductor material layer on the gate insulating layer. And annealing the oxide semiconductor material layer. Forming an etching barrier material layer on the oxide semiconductor material layer. A photoresist material layer is formed on the etching barrier material layer. The photoresist material layer is defined by a half tone mask to form a photoresist pattern. The etch barrier material layer is patterned using the photoresist pattern as a mask to form an etch barrier pattern. The oxide semiconductor material layer is patterned by using the photoresist pattern as a mask to form an oxide semiconductor layer and define a first opening, and the first opening overlaps the gate insulating layer. An ashing process is performed to remove the photoresist pattern. The gate insulating layer is patterned by etching the barrier pattern as a mask to form a first contact hole, and the first contact hole overlaps and shields the metal pattern, wherein an orthographic projection of the first contact hole on the substrate is positioned in an orthographic projection of the first opening on the substrate. Forming a second metal layer on the etching barrier pattern and patterning the second metal layer to define a source electrode, a drain electrode, a signal line and a data line. The partial etching blocking pattern is positioned between the second metal layer and the oxide semiconductor material layer, and the data line is electrically connected to the shielding metal pattern through the first contact window. And patterning the oxide semiconductor layer to define an oxide semiconductor pattern. The source and drain electrodes and the signal line are electrically connected to the oxide semiconductor pattern.

The semiconductor structure of the invention is configured on the substrate, and comprises a first metal layer arranged on the substrate and comprising a gate line electrically connected to the gate electrode, a gate insulating layer arranged on the substrate and covering the gate line, an oxide semiconductor layer arranged on the gate insulating layer and having a first opening, an etching barrier pattern arranged on the oxide semiconductor layer and on a part of the oxide semiconductor pattern, and a second metal layer arranged on the etching barrier pattern. The gate insulating layer has a first contact window overlapping the first metal layer. The patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source and a drain electrically connected to the oxide semiconductor pattern, and a portion of the etch barrier pattern is between the second metal layer and the oxide semiconductor. The second metal layer further comprises a signal line arranged on the etching barrier pattern and electrically connected to the oxide semiconductor pattern, and the second metal layer is electrically connected to the first metal layer through the first contact window.

In view of the above, the semiconductor structure and the method for fabricating the same according to the embodiment of the invention can directly dispose the etching barrier pattern having oxygen atoms on the oxide semiconductor layer and/or the oxide semiconductor pattern, so that the etching barrier pattern can provide oxygen atoms to the oxide semiconductor layer and/or the oxide semiconductor pattern, thereby improving the problem of oxygen vacancy. Therefore, the electrical property of the oxide semiconductor pattern is improved, and the oxide semiconductor pattern can have the characteristics of a semiconductor. Thus, the semiconductor structure of the present embodiment can directly perform the open circuit test and the short circuit test after completing the steps of forming the source, the drain and the signal line. Therefore, the method is suitable for conveniently carrying out detection and repair procedures without additionally carrying out opening procedures, and can reduce the risk of wire breakage so as to have excellent electrical property, further shorten the process time and reduce the cost. Further, the etch barrier pattern and the oxide semiconductor layer may be formed through a mask, and the gate insulating layer may be patterned by using the etch barrier pattern as a mask. Therefore, the semiconductor structure and the manufacturing method thereof can reduce the number of masks used and further reduce the manufacturing cost.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a partial top view of a semiconductor structure according to an embodiment of the invention.

FIGS. 2A-2H are schematic cross-sectional views of the process flow of FIG. 1 along the sectional lines A-A 'and B-B'.

Fig. 3A to 3D are schematic cross-sectional views of the manufacturing process of fig. 1 along the section line C-C'.

FIG. 4 is a cross-sectional view taken along section line D-D' of FIG. 1.

Description of reference numerals:

10: semiconductor structure

100: substrate

111: gate line

112: masking metal pattern

112a, 145, DLa: side edge

120: gate insulating layer

140: oxide semiconductor layer

140': oxide semiconductor material layer

141: the other short side

142: oxide semiconductor pattern

143: short side

160: etching barrier pattern

160': layer of etch stop material

180: photoresist pattern

180': layer of photoresist material

182: projection after development

182': convex part

184': concave part

191: a first flat layer

192: a second flat layer

210: signal line

213. Sa: long side

A-A ', B-B', C-C ', D-D': section line

C1, C2: storage capacitor

CF: color resist layer

CH: channel region

COM: common electrode wire

D: drain electrode

DL: data line

G: grid electrode

H1: a first thickness

H2: second thickness

K1, K2, K3: distance between two adjacent plates

M1: a first metal layer

M2: second metal layer

O1: first opening

O2: second opening

O3: third opening

PE: pixel electrode

S: source electrode

T: thin film transistor

V1: first contact window

V2: second contact window

Detailed Description

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.

In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about," "substantially," or "approximately" includes the stated value and the average value within an acceptable range of deviation of the stated value, taking into account the particular number of measurements in question and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic partial top view of a semiconductor structure according to an embodiment of the present invention, and fig. 1 schematically illustrates only some components for convenience of illustration and observation. FIGS. 2A-2H are schematic cross-sectional views of the process flow of FIG. 1 along the sectional lines A-A 'and B-B'. Fig. 3A to 3D are schematic cross-sectional views of the manufacturing process of fig. 1 along the section line C-C'. Referring to fig. 1 and fig. 2H, the semiconductor structure 10 of the present embodiment is disposed on the substrate 100, and the semiconductor structure 10 includes a first metal layer M1, a gate insulating layer 120, an oxide semiconductor layer 140, an oxide semiconductor pattern 142, an etching stop pattern 160, a second metal layer M2, a first flat layer 191, a color barrier layer CF, a second flat layer 192, and a pixel electrode PE. In the present embodiment, the first metal layer M1 defines the gate line 111 and the shielding metal layer 112. The second metal layer M2 defines a source S, a drain D, a signal line 210 and a data line DL. In some embodiments, the first metal layer M1 may also define a plurality of common electrode lines COM. The common electrode line COM is disposed parallel to the gate line 111 and crosses the signal line 210 and the data line DL. As shown in fig. 1, the common electrode line COM may partially overlap the storage capacitances C1, C2. In the present embodiment, the storage capacitor C1 may be electrically connected to the oxide semiconductor pattern 142. The storage capacitor C2 may be electrically connected to the drain D. Thus, the storage capacitors C1 and C2 can improve the charging and discharging efficiency and performance of the semiconductor structure 10. The method of fabricating the semiconductor structure 10 will be briefly described below with reference to an embodiment.

Referring to fig. 1 and 2A, a method for fabricating the semiconductor structure 10 includes the following steps. First, a substrate 100 is provided. The substrate 100 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be made of thick glass or other applicable materials, and the flexible substrate may be made of thin glass, Polyimide (PI), Polyethylene Naphthalate (PEN), Polyethylene terephthalate (PET), Polyethersulfone (PES), thin metal, or other applicable materials, but the invention is not limited thereto.

Referring to fig. 2A, a first metal layer M1 is formed on the substrate 100. The first metal layer M1 may be patterned to define the gate line 111 and the shielding metal pattern 112. In some embodiments, the first metal layer M1 may also define a common electrode line COM, but the invention is not limited thereto. In other embodiments, the common electrode line COM may also be formed on the substrate 100 simultaneously with the first metal layer M1, but not in the same layer. In the present embodiment, the gate line 111 is, for example, a scan line, and the gate line 111 can be electrically connected to the gate G. As shown in fig. 1, the gate G can be directly formed in the gate line 111, but the invention is not limited thereto. In the embodiment, the first metal layer M1 and the common electrode line COM are made of a metal material, but the invention is not limited thereto, and in other embodiments, other conductive materials (e.g., an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials) may be used for the first metal layer M1 and the common electrode line COM. In the present embodiment, the forming method of the first metal Layer M1 and the common electrode line COM includes a Physical Vapor Deposition (PVD) method, a Chemical Vapor Deposition (CVD) method, an Atomic Layer Deposition (ALD) method, or other suitable methods, which is not limited to the above.

Referring to fig. 2B, a gate insulating layer 120 is formed on the substrate 100 to cover the gate line 111, the gate electrode G, the common electrode line COM and a portion of the substrate 100. The material of the gate insulating layer 120 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof.

Next, an oxide semiconductor material layer 140' is formed on the gate insulating layer 120. In the present embodiment, the material of the Oxide semiconductor material layer 140' includes Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Indium Tin Zinc Oxide (ITZO), Zinc Oxide (ZnO), or other suitable materials. The oxide semiconductor material layer 140' may be a single layer of any one of the above materials or a stacked layer of more than one of the above materials, which is not limited by the invention. In some embodiments, the material of the oxide semiconductor material layer 140' may further include a metal Silicide, such as Indium Silicide (IS), but the invention IS not limited thereto. In the present embodiment, the forming method of the oxide semiconductor material layer 140' includes, for example, a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method, or other suitable methods, which is not limited in the invention.

Then, an annealing process (annealing) is performed on the oxide semiconductor material layer 140 'to crystallize the oxide semiconductor material layer 140' to have electrical properties. At this time, the oxide semiconductor material layer 140 'may generate carriers (electrons) due to oxygen vacancies (oxygen vacancies), for example, so that the oxide semiconductor material layer 140' is in an on state.

Next, an etch barrier material layer 160 'is formed on the oxide semiconductor material layer 140'. In the embodiment, the material of the etching stop material layer 160' is, for example, an oxide, including hafnium oxide, silicon oxide, or aluminum oxide, or other suitable materials, but the invention is not limited thereto. In the present embodiment, the forming method of the etching barrier material layer 160' includes, for example, a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method, or other suitable methods, which is not limited in the invention.

It should be noted that since the etching stop material layer 160 'having oxygen atoms can be directly disposed on the oxide semiconductor material layer 140', the etching stop material layer 160 'can be used to provide oxygen atoms to the oxide semiconductor material layer 140' to improve the problem of oxygen vacancy. Therefore, the threshold voltage of the oxide semiconductor material layer 140 'can be a positive value, thereby improving the problem of leakage current and enhancing the electrical property of the oxide semiconductor material layer 140'. Under the above arrangement, the oxide semiconductor material layer 140' may also be in a non-conductive state and have the characteristics of a semiconductor.

Referring to fig. 2C, a photoresist material layer 180 'is then formed on the etch stop material layer 160'. The photoresist material layer 180' may be, for example, a positive photoresist material or a negative photoresist material. This embodiment is exemplified by the photoresist material layer 180' being a positive photoresist material. In other words, the exposed portions of the photoresist material layer 180' will dissolve in the developer. However, the invention is not limited thereto.

Referring to fig. 2C and fig. 2D, next, the photoresist material layer 180 'may be exposed and developed by using a Half Tone Mask (HTM), a phase shift mask (phase shift mask), or a gray tone mask (gray tone mask) as a mask (not shown) to define the photoresist material layer 180'. In detail, as shown in fig. 2C, different portions of the photoresist layer 180' may be exposed to light to different degrees through a half-tone mask (not shown), and then the different portions may be dissolved in a developer through a developing process to define portions with different thicknesses. For example, the photoresist material layer 180 'may include a protrusion 182' and a recess 184 ', and the protrusion 182' and the recess 184 'are continuously disposed on the etch barrier material layer 160'. The thickness of the convex portion 182 'is greater than that of the concave portion 184'. In other words, the first thickness H1 of the convex portion 182 'is greater than the second thickness H2 of the concave portion 184'. As shown in fig. 2C, the first thickness H1 is, for example, twice the second thickness H2, but the invention is not limited thereto. In some embodiments, the first thickness H1 may also be, for example, three, four, or more times the second thickness H2, depending on the needs of the user. In some embodiments, the first thickness H1 is, for example, 2.4 microns, but the invention is not limited thereto.

As shown in fig. 2C and 2D, the photoresist material layer 180 ' is defined by the half tone mask and is developed, so that the concave portions 184 ' of the photoresist material layer 180 ' are removed, and the developed convex portions 182 are remained to form the photoresist pattern 180. In the present embodiment, the thickness of the projection 182' is larger than the thickness of the projection 182 after the development. In another aspect, the thickness of the projection 182 after the development is, for example, half of the first thickness H1 of the projection 182', but the invention is not limited thereto.

Referring to fig. 2D and 2E, in the present embodiment, in a direction perpendicular to the substrate 100, the patterned photoresist pattern 180 only overlaps a portion of the etch stop material layer 160 'and exposes a surface of the etch stop material layer 160'. Then, the etch barrier material 160' is patterned using the photoresist pattern 180 as a mask to form the etch barrier pattern 160. The method of patterning the etch barrier material 160 'includes using an acidic or basic solution to remove a portion of the etch barrier material 160' that does not overlap the photoresist pattern 180, but the present invention is not limited thereto. As shown in fig. 2E, the etch barrier pattern 160 overlaps the photoresist pattern 180, thereby transferring the pattern of the photoresist pattern 180 onto the etch barrier pattern 160.

As shown in fig. 2D and 2E, after the step of forming the etch barrier pattern 160, the oxide semiconductor material layer 140' may be patterned to form the oxide semiconductor layer 140 by using the photoresist pattern 180 and the etch barrier pattern 160 as masks. As shown in fig. 2E, the oxide semiconductor layer 140 partially overlaps the gate line 111 without overlapping the common electrode line COM, but the invention is not limited thereto. In some embodiments, the oxide semiconductor layer 140 may also overlap the common electrode line COM. In another aspect, in the step of patterning the oxide semiconductor material layer 140 ', a portion of the oxide semiconductor material layer 140' may be removed to expose a portion of the gate insulating layer 120. In the above steps, a first opening O1 (shown in fig. 3C) may be defined to electrically connect the first metal layer M1 to the second metal layer M2 in the subsequent process. The above-mentioned step of defining the first opening O1 is described in the later paragraphs of the specification. It is further noted that fig. 2E is a partial cross-sectional view of the semiconductor structure 10 of fig. 1 along the sectional lines a-a ' and B-B ', and therefore does not illustrate the patterning of the oxide semiconductor material layer 140 ' to form the oxide semiconductor layer 140 having the first opening O1.

Referring to fig. 1, 2E and 2F, an ashing process is performed to remove the photoresist pattern 180. Next, a second metal layer M2 is formed on the etch barrier pattern 160. The second metal layer M2 may partially cover the gate insulating layer 120, the oxide semiconductor layer 140, and the etch barrier pattern 160. From another perspective, the partial etch barrier pattern 160 may be located between the second metal layer M2 and the oxide semiconductor layer 140.

Next, the second metal layer M2 may be patterned to define the source S, the drain D, the signal line 210 and the data line DL. In some embodiments, the second metal layer M2 may further define a storage capacitor C1 (shown in fig. 1), C2, but the invention is not limited thereto. In some embodiments, the storage capacitors C1, C2 may also be disposed separately from the second metal layer M2. As shown in fig. 1 and fig. 2F, the storage capacitor C2 is electrically connected to the drain D and belongs to the same layer, and the storage capacitor C2 may partially overlap the common electrode line COM. As such, a capacitance may be generated in the gate insulating layer 120 between the storage capacitor C2 and the common electrode line COM.

Then, the oxide semiconductor layer 140 is patterned to define an oxide semiconductor pattern 142. In other words, as shown in fig. 1 and 2F, the oxide semiconductor pattern 142 and the oxide semiconductor layer 140 are the same layer and the oxide semiconductor pattern 142 may be defined as a portion of the oxide semiconductor layer 140 overlapping the source S, the drain D and the signal line 210. From another perspective, the orthographic projection of the oxide semiconductor pattern 142 on the substrate 100 overlaps the orthographic projection of the gate G on the substrate 100. In this embodiment, the second metal layer M2 (e.g., including the source S, the drain D, the signal line 210 and the data line DL) is usually made of a metal material, however, the invention is not limited thereto, and in other embodiments, the second metal layer M2 may be made of other conductive materials (e.g., alloy, metal nitride, metal oxide, metal oxynitride or other suitable materials) or stacked layers of metal materials and other conductive materials. In this manner, a Thin Film Transistor (TFT) of the semiconductor structure 10 of the present embodiment is completed.

Referring to fig. 1 and 2F, in the present embodiment, the thin film transistor T is disposed on the substrate 100 and includes a gate G, an oxide semiconductor pattern 142, a source S and a drain D. The source S and the drain D are respectively disposed on the etch stopper pattern 160 oppositely. The gate electrode G is spaced apart from the oxide semiconductor pattern 142 by the gate insulating layer 120. The oxide semiconductor pattern 142 between the source S and the drain D is a channel region CH, and the channel region CH overlaps the gate G on the gate line 111. In this embodiment, a portion of the etch barrier pattern 160 may overlap the channel region CH and the gate electrode G. The etching barrier pattern 160 may expose a portion of the oxide semiconductor pattern 142 to electrically connect the source S and the drain D with the oxide semiconductor pattern 142. in the embodiment, the thin film transistor T is, for example, a bottom-gate thin film transistor (bottom-gate TFT), but the invention is not limited thereto. In other embodiments, the thin film transistor T may also be a top-gate thin film transistor (top-gate TFT) or other suitable type of thin film transistor. It should be noted that fig. 1 and 2F only show one thin film transistor T, but the number of the thin film transistors T is not limited to the number shown in fig. 1 and 2F. It should be understood by those skilled in the art that a plurality of thin film transistors T may be actually disposed on the substrate 100 in an array manner, and there may be thousands, tens of thousands or millions of thin film transistors T.

In the present embodiment, as shown in fig. 1, the data line DL is defined by a metal layer M2. The data lines DL and the gate lines 111 are disposed in a staggered manner and belong to different horizontal layers. In the present embodiment, the thin film transistor T is electrically connected to the gate line 111 and the data line DL. In detail, the gate G is electrically connected to the gate line 111, and the source S is electrically connected to the data line DL.

As shown in fig. 1 and fig. 2F, the second metal layer M2 can further define a signal line 210, and the extending direction of the signal line 210 is substantially parallel to the extending direction of the data line DL. In the present embodiment, the signal line 210 partially overlaps the etch barrier pattern 160 and contacts the oxide semiconductor pattern 142 through an opening (not shown) on the etch barrier pattern 160. As a result, the signal line 210 may be electrically connected to the thin film transistor T through the oxide semiconductor pattern 142. In the embodiment, the thin film transistor T of the semiconductor structure 10 can achieve the voltage division effect through the signal line 210, so that the performance of the semiconductor structure 10 can be improved.

In the present embodiment, a distance K1 is provided between the edge of the signal line 210 and the edge of the oxide semiconductor pattern 142. In detail, as shown in fig. 1 and 2F, the oxide semiconductor pattern 142 has a short side 143 and another short side 141 opposite to the short side 143. A short side 143 of the orthographic projection of the oxide semiconductor pattern 142 on the substrate 100 is parallel to a long side 213 of the orthographic projection of the signal line 210 overlapping the oxide semiconductor pattern 142 on the substrate 100. The long side 213 is an edge of the short side 143 of the adjacent oxide semiconductor pattern 142. The distance K1 between short side 143 and long side 213 is 0.5 to 1 micrometer. In other words, the orthographic projection of the oxide semiconductor pattern 142 on the substrate 100 is protruded from the orthographic projection of the signal line 210 on the substrate 100, but the invention is not limited thereto.

In the present embodiment, a distance K2 is provided between the edge of the source S and the edge of the oxide semiconductor pattern 142. In detail, as shown in fig. 1, the other short side 141 of the orthographic projection of the oxide semiconductor pattern 142 on the substrate 100 is parallel to the one long side Sa of the orthographic projection of the source S on the substrate 100. The long side Sa is an edge of the other short side 141 of the adjacent oxide semiconductor pattern 142. The distance K2 between the other short side 141 and the long side Sa is 0.5 to 1 micrometer. In other words, the orthographic projection of the oxide semiconductor pattern 142 on the substrate 100 is protruded from the orthographic projection of the source S on the substrate 100, but the invention is not limited thereto.

It should be noted that the embodiment can improve the problem of oxygen vacancy by directly disposing the etching barrier pattern 160 on the oxide semiconductor layer 140 and/or the oxide semiconductor pattern 142 to provide oxygen atoms to the oxide semiconductor layer 140 and/or the oxide semiconductor pattern 142. Thus, compared to the conventional process in which the source S and the drain D are formed and then the passivation layer is formed on the oxide semiconductor pattern 142 to perform the open circuit test and the short circuit test, the oxide semiconductor pattern 142 of the present embodiment has the characteristics of a semiconductor after the step of forming the etching stopper pattern 160. Therefore, after the patterning of the second metal layer M2 (e.g., the step of forming the source S, the drain D, the signal line 210 and the data line DL) and the step of defining the oxide semiconductor pattern 142 are completed, an electrical test procedure (not shown) may be performed. Therefore, the source S, the drain D and the signal line 210 are directly subjected to an open circuit test and a short circuit test. Under the above configuration, it is not necessary to perform an opening procedure to expose the source S, the drain D and the signal line 210 to be tested, so that the testing and repairing procedures can be conveniently performed, and the procedure of opening the hole to expose the source S, the drain D and the signal line 210 can be avoided, thereby reducing the risk of wire breakage and providing excellent electrical properties. Therefore, the process time can be shortened and the cost can be reduced.

Referring to fig. 2G, a first planarization layer 191 is formed on the etch stop pattern 160. The first planarization layer 191 covers a portion of the gate insulating layer 120, the etch barrier pattern 160, and the second metal layer M2 (e.g., the source S, the drain D, the signal line 210, and the storage capacitor C2). The first planarization layer 191 has a second contact V2. As shown in fig. 1 and 2G, the second contact window V2 overlaps the storage capacitors C1 and C2 in the direction perpendicular to the substrate 100. From another perspective, the second contact windows V2 may expose the surfaces of the storage capacitors C1, C2 (fig. 2G shows only the storage capacitor C2). In the present embodiment, the material of the first planarization layer 191 includes, for example, an inorganic material. The inorganic material is, for example, a stacked layer including silicon oxide, silicon nitride, silicon oxynitride, or at least two of the above materials, but the present invention is not limited thereto.

Then, a color resist layer CF is formed on the first planarization layer 191. The color resist layer CF is exemplified by a photoresist layer having a color filter function. In the present embodiment, the color resistance layer CF is disposed on the substrate 100 having the thin film transistor T array. In other words, the substrate 100 is a technology of integrating a Color Filter layer (Color Filter layer) into an array substrate (COA), for example. However, the invention is not limited thereto, and in some embodiments, the color resist layer CF may also be disposed on the color substrate and opposite to the substrate 100.

In the present embodiment, the color-resist layer CF has a second opening O2, and the second opening O2 overlaps the second contact window V2 and the storage capacitor C2 in a direction perpendicular to the substrate 100. In other words, the second opening O2 and the second contact V2 together expose the storage capacitor C2. In addition, as shown in fig. 2G, an orthographic projection of the second contact hole V2 on the substrate 100 is located within an orthographic projection of the second opening O2 on the substrate 100.

Next, a second planarization layer 192 is formed on the color resist layer CF. The second planarization layer 192 has a third opening O3, and the third opening O3 overlaps the second contact V2 in the direction perpendicular to the substrate 100. In the embodiment, the third opening O3 may completely overlap the second contact V2, but the invention is not limited thereto. In this embodiment, the material of the second flat layer 192 includes, for example, an organic material. Examples of the organic material include Polyesters (PET), polyolefins, polyacryls, polycarbonates, polyalkylenes, polyphenylenes, polyethers, polyketones, polyols, polyaldehydes, other suitable materials, and combinations thereof, but the present invention is not limited thereto. In other embodiments, the material of the second flat layer 192 may also include a photoresist material.

The above description is given by way of example only when the first planarization layer 191, the color resist layer CF and the second planarization layer 192 are formed with the second contact window V2, the second opening O2 and the third opening O3, respectively, but the present invention is not limited thereto. In some embodiments, the color-resist layer CF may be patterned to form the second opening O2 after the color-resist layer CF is formed. A second planarization layer 192 is then formed and partially conformally fills the second opening O2. Then, a photolithography (photolithography) etching process is performed to simultaneously pattern the first and second planarization layers 191 and 192, thereby simultaneously forming the third opening O3 and the second contact V2 overlapping the third opening O3 and exposing the drain D. Therefore, the orthographic projections of the third opening O3 and the second contact window V2 on the substrate 100 are both located within the orthographic projection of the second opening O2 on the substrate 100, but the invention is not limited thereto.

Referring to fig. 2H, a pixel electrode PE is then formed on the second planarization layer 192. In the present embodiment, the pixel electrode PE is electrically connected to the thin film transistor T. In detail, the pixel electrode PE is electrically connected to the storage capacitor C2 through the second opening O2, the third opening O3, and the second contact V2. Then, the storage capacitor C2 contacts the drain D to electrically connect to the tft T. The pixel electrode PE is a transparent conductive material, which includes a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxide, or a stacked layer of at least two of the above, but the invention is not limited thereto. Thus, the fabrication of the thin film transistor T of the semiconductor structure 10 is substantially completed.

It is noted that the present embodiment may simultaneously pattern the gate insulating layer 120 and define the first contact windows V1 by forming a mask for etching the barrier pattern 160. The method for electrically connecting the first metal layer M1 to the second metal layer M2 will be briefly described as an example.

Referring to fig. 1, fig. 2A and fig. 3A, in the present embodiment, when the step of defining the gate line 111 by the first metal layer M1 is performed, the shielding metal pattern 112 can be defined at the same time. As shown in fig. 1, the number of the shielding metal patterns 112 may be multiple, for example, 4, but the number is not limited to that shown in fig. 1.

Referring to fig. 1, fig. 2C and fig. 3B, a gate insulating layer 120, an oxide semiconductor layer 140 'and an etch stop material layer 160' are sequentially formed on the shielding metal pattern 112. Next, a photoresist material layer 180 'is formed on the etch barrier material layer 160'. As shown in fig. 3B, the photoresist material layer 180 ' includes a relatively thick protrusion 182 ' and a relatively thin recess 184 '. The method for forming the protrusion 182 ' and the recess 184 ' of the photoresist material layer 180 ' of fig. 3B is the same as the method shown in fig. 2C, and therefore, the description thereof is omitted.

Referring to fig. 1, 2D, 3B and 3C, the photoresist material layer 180 ' is then defined by a half-tone mask (not shown) and a developing process is performed to remove portions of the recesses 184 ' in the photoresist material layer 180 ' and leave portions of the developed protrusions 182 to form the photoresist pattern 180. Referring to fig. 2E and 3C, the etch stopper pattern 160 and the oxide semiconductor layer 140 are formed using the photoresist pattern 180 as a mask. In the present embodiment, the edges of the etch stop pattern 160 and the oxide semiconductor layer 140 may be cut off, but not limited thereto. In the above step of forming the oxide semiconductor layer 140, a first opening O1 may be defined at a position overlapping the shielding pattern 112. As shown in fig. 3C, the first opening O1 overlaps the gate insulating layer 120 and the shielding pattern 112 in a direction perpendicular to the substrate 100. From another perspective, the first opening O1 exposes the gate insulating layer 120.

Referring to fig. 1, 2F, 3C and 3D, the gate insulating layer 120 is patterned by using the photoresist pattern 180 and the etch barrier pattern 160 as a mask to form a first contact window V1. As shown in fig. 1 and 3D, the first contact windows V1 overlap the shielding metal patterns 112. From another perspective, the orthographic projection of the first contact window V1 on the substrate 100 is located within the orthographic projection of the first opening O1 on the substrate 100.

In short, under the above configuration, the present embodiment may form the etch barrier pattern 160 and the oxide semiconductor layer 140 through a mask, and pattern the gate insulating layer 120 by using the etch barrier pattern 160 as a mask to form the first contact hole V1. Therefore, the present embodiment can integrate the mask of the conventional patterned oxide semiconductor material layer 140' and the mask of the patterned gate insulating layer 120 into the same mask, so as to reduce the number of masks used, thereby reducing the manufacturing cost.

Next, as shown in fig. 2F and 3D, after the photoresist pattern 180 is removed, a second metal layer M2 is formed on the etching stopper pattern 160, and a data line DL is defined. In the present embodiment, the data line DL is disposed on the etch barrier pattern 160 and conformally fills the first opening O1 and the first contact window V1. Therefore, the data line DL of the second metal layer M2 can be electrically connected to the shielding metal layer 112 of the first metal layer M1 through the first contact hole V1. As shown in fig. 1 and 3D, an etching stopper pattern 160 and an oxide semiconductor layer 140 are interposed between the data line DL and the shielding metal pattern 112. In addition, the data line DL partially overlaps the shielding metal pattern 112.

In the present embodiment, a distance K3 is formed between the edge of the data line DL and the edge of the oxide semiconductor layer 140. In detail, as shown in fig. 1 and 3D, the side 145 of the orthographic projection of the oxide semiconductor layer 140 on the substrate 100 is aligned with the side 112a of the shielding metal pattern 112, and is parallel to the side DLa of the orthographic projection of the data line DL on the substrate 100. The side DLa is an edge adjacent to the side 145 of the oxide semiconductor layer 140. The distance K3 between side edge 145 and side edge DLa is 0.5 to 1 micron. In other words, the orthographic projection of the oxide semiconductor 140 on the substrate 100 is protruded from the orthographic projection of the data line DL on the substrate 100, but the invention is not limited thereto.

With the above arrangement, the probability of generating parasitic capacitance between the data line DL and the shielding metal layer 112 can be further reduced. In addition, the data line DL can also increase the area for transmitting signals and reduce the risk of open circuit caused by wire disconnection by electrically connecting to the shielding metal layer 112, thereby increasing the performance and reliability of the semiconductor structure 10.

FIG. 4 is a cross-sectional view taken along section line D-D' of FIG. 1. Please refer to fig. 1, fig. 3D and fig. 4. The cross-sectional view of the data line DL shown in fig. 4 is similar to the cross-sectional view of the data line DL shown in fig. 3D, except that the data line DL shown in fig. 4 is not electrically connected to the shielding metal pattern 112. Specifically, the gate insulating layer 120, the oxide semiconductor layer 140, and the etch stopper pattern 160 are interposed between the data line DL and the shielding metal pattern 112. In addition, a distance K3 is formed between an orthogonal projection of the side DLa of the data line DL on the substrate 100 and an orthogonal projection of the side 145 of the oxide semiconductor layer 140 on the substrate 100, and the distance K3 is 0.5 μm to 1 μm. Under the above configuration, the gate insulating layer 120, the oxide semiconductor layer 140 and the etching stop pattern 160 may further reduce the probability of generating a parasitic capacitance between the data line DL and the shielding metal layer 112, thereby increasing the performance of the semiconductor structure 10.

In summary, the semiconductor structure and the method for fabricating the same according to the embodiments of the invention can directly dispose the etching barrier pattern having oxygen atoms on the oxide semiconductor layer and/or the oxide semiconductor pattern, so that the etching barrier pattern can provide oxygen atoms to the oxide semiconductor layer and/or the oxide semiconductor pattern, thereby improving the problem of oxygen vacancy. Therefore, the initial voltage of the oxide semiconductor pattern can be a positive value, so that the problem of leakage current can be solved, the electrical property of the oxide semiconductor pattern is improved, and the oxide semiconductor pattern has the characteristics of a semiconductor. Thus, the semiconductor structure of the present embodiment can directly perform the open circuit test and the short circuit test after completing the steps of forming the source, the drain and the signal line. Therefore, the method is suitable for conveniently carrying out detection and repair procedures without additionally carrying out opening procedures, and can reduce the risk of wire breakage so as to have excellent electrical property, further shorten the process time and reduce the cost.

Furthermore, the semiconductor structure and the manufacturing method thereof of the present invention can form the etching barrier pattern and the oxide semiconductor layer through one mask, and pattern the gate insulating layer by using the etching barrier pattern as the mask. Therefore, the present invention can integrate the mask of the existing patterned oxide semiconductor material layer and the mask of the patterned gate insulating layer into the same mask, so as to reduce the number of the used masks and further reduce the manufacturing cost.

In addition, the data line of the semiconductor structure can be electrically connected to the shielding metal layer to increase the area for transmitting signals, reduce the risk of open circuit caused by disconnection, and increase the performance and reliability of the semiconductor structure. In addition, a gate insulating layer, an oxide semiconductor layer and an etching blocking pattern can be clamped between the data line and the shielding metal pattern, so that the probability of generating parasitic capacitance between the data line and the shielding metal layer is further reduced, and the performance of the semiconductor structure is further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.