阅读说明：本技术 降低芯片塑性变形的扇出型封装结构及封装方法 (Fan-out type packaging structure and packaging method for reducing plastic deformation of chip ) 是由 蔡琨辰 钟必彰 杨斌 于 2019-09-12 设计创作，主要内容包括：本发明提供了一种降低芯片塑性变形的扇出型封装结构及封装方法,该封装方法包括以下步骤：S1、在载板上设置键合胶层,并将多个芯片粘接在所述键合胶层上；S2、在所述键合胶层上形成多个过渡层封装结构,每一所述过渡层封装结构将一所述芯片包裹在内；S3、在所述键合胶层上形成塑封层,所述塑封层将每一所述过渡层封装结构均包裹在内,从而在所述键合胶层上形成芯片封装结构,所述过渡层封装结构的热膨胀系数小于所述塑封层的热膨胀系数；S4、去除所述载板以及键合胶层,并依次设置介电材料层、金属线路层。本发明可以避免由于芯片与塑封层之间的热膨胀系数的匹配问题导致的芯片的塑性变形,可以提高产品良率。(The invention provides a fan-out type packaging structure and a packaging method for reducing plastic deformation of a chip, wherein the packaging method comprises the following steps: s1, arranging a bonding adhesive layer on the carrier plate, and bonding a plurality of chips on the bonding adhesive layer; s2, forming a plurality of transition layer packaging structures on the bonding glue layer, wherein each transition layer packaging structure wraps one chip; s3, forming a plastic package layer on the bonding adhesive layer, wherein the plastic package layer wraps each transition layer package structure so as to form a chip package structure on the bonding adhesive layer, and the thermal expansion coefficient of the transition layer package structure is smaller than that of the plastic package layer; and S4, removing the carrier plate and the bonding glue layer, and sequentially arranging a dielectric material layer and a metal circuit layer. The invention can avoid the plastic deformation of the chip caused by the matching problem of the thermal expansion coefficient between the chip and the plastic packaging layer, and can improve the yield of products.)

1. A fan-out packaging method for reducing plastic deformation of a chip is characterized by comprising the following steps:

s1, arranging a bonding adhesive layer on the carrier plate, and bonding a plurality of chips on the bonding adhesive layer;

s2, forming a plurality of transition layer packaging structures on the bonding glue layer, wherein each transition layer packaging structure wraps one chip;

s3, forming a plastic package layer on the bonding adhesive layer, wherein the plastic package layer wraps each transition layer package structure so as to form a chip package structure on the bonding adhesive layer, and the thermal expansion coefficient of the transition layer package structure is smaller than that of the plastic package layer;

and S4, removing the carrier plate and the bonding glue layer, and sequentially arranging a dielectric material layer and a metal circuit layer.

2. The fan-out packaging method for reducing the plastic deformation of the chip according to claim 1, wherein in the step S1, one end of the chip, where the output/output interface is disposed, is bonded to the bonding glue layer;

and the step S4 includes:

removing the carrier plate and the bonding adhesive layer to leave the chip packaging structure;

arranging a dielectric material layer on one surface of the chip packaging junction close to the output/output interface;

and arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer is electrically connected with the output/output interface.

3. The fan-out packaging method for reducing the plastic deformation of the chip according to claim 1, wherein in the step S1, the end of the chip provided with the output/output interface faces away from the bonding glue layer;

and the step S4 includes:

thinning one surface of the chip packaging structure far away from the carrier plate to ensure that the thicknesses of the plastic packaging layer and the transition layer packaging structure are less than or equal to the thickness of the chip so as to expose one end of the chip, which is provided with an input/output interface;

arranging a dielectric material layer on one surface of the chip packaging structure subjected to thinning treatment;

and arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer is electrically connected with the output/output interface.

4. The fan-out packaging method for reducing plastic deformation of the chip according to claim 1, wherein the transition layer packaging structure is made of polyimide, cyanate ester type epoxy resin or liquid epoxy resin-based packaging material doped with inorganic substances to adjust the thermal expansion coefficient.

5. The fan-out packaging method for reducing plastic deformation of chips according to claim 4, wherein in the step S2, the transition layer packaging structure is formed by a dropping method.

6. The fan-out packaging method for reducing plastic deformation of the chip according to claim 1, wherein the plastic sealing layer is made of epoxy resin.

7. A fan-out package structure for reducing plastic deformation of a chip, comprising:

a layer of dielectric material;

the plurality of chips are distributed on the upper surface of the dielectric material layer in an array manner;

the transition layer packaging structures are arranged on the upper surface of the dielectric material layer, and each transition layer packaging structure wraps one chip;

the plastic packaging layer is arranged on the upper surface of the dielectric material layer and wraps each transition layer packaging structure, and the thermal expansion coefficient of the transition layer packaging structure is smaller than that of the plastic packaging layer;

and the metal circuit layer is arranged on the lower surface of the dielectric material layer and is electrically connected with the input/output port of the chip.

8. The fan-out package structure capable of reducing plastic deformation of a chip according to claim 7, wherein the transition layer package structure is made of polyimide, cyanate ester type epoxy resin or liquid epoxy resin based encapsulant doped with inorganic substances to adjust thermal expansion coefficient.

9. The fan-out package structure with reduced plastic deformation of a chip of claim 8, wherein the transition layer package structure is formed by a drop-casting method.

10. The fan-out package structure with reduced plastic deformation of chips of claim 7, wherein said molding layer is made of epoxy resin.

Technical Field

The invention relates to the field of chip packaging, in particular to a fan-out type packaging structure and a packaging method for reducing plastic deformation of a chip.

Background

Modern electronic information technology is rapidly developed, and electronic products are developed in the directions of miniaturization, portability and multiple functions. Electronic packaging materials and techniques have led to the ultimate realization of electronic devices as functional products. A variety of new packaging materials, techniques and processes have been developed. Electronic packaging is driving the development of information-oriented society along with electronic design and manufacturing.

In the chip packaging structure, due to the matching problem of the thermal expansion coefficient between the chip and the plastic packaging material, the stress of a packaging device is not balanced, so that the plastic deformation of the chip occurs, the smooth proceeding of the packaging process is ensured, and the product yield is low.

Disclosure of Invention

The invention aims to provide a fan-out type packaging structure and a packaging method for reducing the plastic deformation of a chip, which can avoid the plastic deformation of the chip caused by the matching problem of the thermal expansion coefficient between the chip and a plastic packaging layer and can improve the yield of products.

The invention provides a fan-out type packaging method for reducing plastic deformation of a chip, which comprises the following steps:

s1, arranging a bonding adhesive layer on the carrier plate, and bonding a plurality of chips on the bonding adhesive layer;

s2, forming a plurality of transition layer packaging structures on the bonding glue layer, wherein each transition layer packaging structure wraps one chip;

s3, forming a plastic package layer on the bonding adhesive layer, wherein the plastic package layer wraps each transition layer package structure so as to form a chip package structure on the bonding adhesive layer, and the thermal expansion coefficient of the transition layer package structure is smaller than that of the plastic package layer;

and S4, removing the carrier plate and the bonding glue layer, and sequentially arranging a dielectric material layer and a metal circuit layer.

In the fan-out packaging method for reducing the plastic deformation of the chip, in the step S1, one end of the chip, which is provided with the output/output interface, is bonded to the bonding adhesive layer;

and the step S4 includes:

removing the carrier plate and the bonding adhesive layer to leave the chip packaging structure;

arranging a dielectric material layer on one surface of the chip packaging junction close to the output/output interface;

and arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer is electrically connected with the output/output interface.

In the fan-out packaging method for reducing the plastic deformation of the chip, in the step S1, one end of the chip, which is provided with the output/output interface, faces away from the bonding adhesive layer;

and the step S4 includes:

thinning one surface of the chip packaging structure far away from the carrier plate to ensure that the thicknesses of the plastic packaging layer and the transition layer packaging structure are less than or equal to the thickness of the chip so as to expose one end of the chip, which is provided with an input/output interface;

arranging a dielectric material layer on one surface of the chip packaging structure subjected to thinning treatment;

and arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer is electrically connected with the output/output interface.

In the fan-out type packaging method for reducing the plastic deformation of the chip, the transition layer packaging structure adopts polyimide, cyanate ester type epoxy resin or liquid epoxy resin-based packaging material doped with inorganic matters to adjust the thermal expansion coefficient.

In the fan-out packaging method for reducing the plastic deformation of the chip, in the step S2, the transition layer packaging structure is formed by a dropping method.

In the fan-out type packaging method for reducing the plastic deformation of the chip, the plastic packaging layer adopts epoxy resin.

A fan-out package structure for reducing plastic deformation of a chip, comprising:

a layer of dielectric material;

the plurality of chips are distributed on the upper surface of the dielectric material layer in an array manner;

the transition layer packaging structures are arranged on the upper surface of the dielectric material layer, and each transition layer packaging structure wraps one chip;

the plastic packaging layer is arranged on the upper surface of the dielectric material layer and wraps each transition layer packaging structure, and the thermal expansion coefficient of the transition layer packaging structure is smaller than that of the plastic packaging layer;

and the metal circuit layer is arranged on the lower surface of the dielectric material layer and is electrically connected with the input/output port of the chip.

In the fan-out type packaging structure for reducing the plastic deformation of the chip, the transition layer packaging structure adopts polyimide, cyanate type epoxy resin or liquid epoxy resin-based packaging material doped with inorganic matters to adjust the thermal expansion coefficient.

In the fan-out type packaging structure for reducing the plastic deformation of the chip, the transition layer packaging structure is formed by a dripping method.

In the fan-out type packaging structure for reducing the plastic deformation of the chip, the plastic packaging layer is made of epoxy resin.

According to the invention, the transition layer packaging structure is wrapped outside the chip, and then packaging is carried out, so that the plastic deformation of the chip caused by the matching problem of the thermal expansion coefficient between the chip and the plastic packaging layer can be avoided, and the product yield can be improved.

Drawings

Fig. 1 is a flow chart of a fan-out packaging method for reducing plastic deformation of a chip in an embodiment of the invention.

Fig. 2-8 are detailed schematic diagrams of a fan-out packaging method for reducing plastic deformation of a chip in an embodiment of the invention.

Fig. 9 is a schematic structural diagram of a fan-out package structure for reducing plastic deformation of a chip according to an embodiment of the invention.

Fig. 10 is a schematic structural diagram of another fan-out package structure for reducing plastic deformation of a chip in an embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

Referring to fig. 1, fig. 1 is a flow chart illustrating a fan-out packaging method for reducing plastic deformation of a chip according to some embodiments of the present invention. The fan-out type packaging method for reducing the plastic deformation of the chip comprises the following steps:

and S1, arranging a bonding adhesive layer on the carrier plate, and bonding a plurality of chips on the bonding adhesive layer.

Referring to fig. 2, the carrier 101 may be a glass carrier, an organic carrier, a stainless steel carrier, an alloy carrier, a glass carrier, an FR2 carrier, an FR4 carrier, an FR5 carrier, or a BT carrier. The bonding glue layer 102 may be a blue film or other adhesive glue. The plurality of chips 103 are distributed in a matrix and are arranged at regular intervals.

And S2, forming a plurality of transition layer packaging structures on the bonding glue layer, wherein each transition layer packaging structure wraps one chip inside.

Referring to fig. 3, the transition layer package structure 104 is made of polyimide, cyanate ester type epoxy resin, or liquid epoxy resin based package material doped with inorganic substance to adjust the thermal expansion coefficient. The inorganic substance may be SiO 2. The transition layer packaging structure is formed by adopting a dripping method. The two adjacent transition layer packaging structures are not in contact with each other and are distributed at intervals.

And S3, forming a plastic package layer on the bonding adhesive layer, wherein the plastic package layer wraps each transition layer packaging structure, so that a chip packaging structure is formed on the bonding adhesive layer, and the thermal expansion coefficient of the transition layer packaging structure is smaller than that of the plastic package layer.

Referring to fig. 4, before the step S3 is executed, the transition layer package structure 104 is cured. The encapsulating layer 105 can be an encapsulating epoxy resin, for example, a bisphenol A type epoxy resin, a brominated epoxy resin, a novolak type epoxy resin, a bisphenol F type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a glycidyl amine type epoxy resin, a hydantoin type epoxy resin, an alicyclic epoxy resin, a trishydroxyphenylmethane type epoxy resin, a bis-bisphenol type or a bisphenol type epoxy resin or a mixture thereof, a bisphenol S type epoxy resin, a bisphenol A novolak type epoxy resin, a tetraphenylphenol alcohol (PhenylLOL) ethane type epoxy resin, a heterocyclic epoxy resin, a diglycidyl benzoate resin, a tetraglycidyl diphenol ethane resin, a naphthyl group-containing epoxy resin, a nitrogen-containing epoxy resin, an epoxy resin having a dicyclopentadiene skeleton, a glycidyl methacrylate copolymer type epoxy resin, Epoxy resins obtained by copolymerizing cyclohexylmaleimide with glycidyl methacrylate, CTBN-modified epoxy resins, and the like. Of course, these epoxy resins may be used alone or in combination of 2 or more.

And S4, removing the carrier plate and the bonding glue layer, and sequentially arranging a dielectric material layer and a metal circuit layer.

In this step, the bonding glue layer 102 may be removed by thermal detachment, mechanical detachment, or laser detachment to detach the carrier 101.

Referring to fig. 5 and fig. 6, in this embodiment, one end of the chip 103, where the output/output interface 1031 is disposed, is adhered to the bonding adhesive layer 102; therefore, the step S4 specifically includes: s41, removing the carrier plate and the bonding glue layer to leave the chip packaging structure; s42, arranging a dielectric material layer 106 on one surface of the chip packaging junction close to the output/output interface; and S43, arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer 107 is electrically connected with the output/output interface.

The dielectric material layer 106 is formed with a through hole, and the metal circuit layer 107 is electrically connected to the input/output interface 1031 of the chip 103 through the through hole.

Referring to fig. 7 and fig. 8, in other embodiments, the end of the chip 103 provided with the output/output interface 1031 faces away from the bonding adhesive layer 102; therefore, the step S4 specifically includes: s44, thinning one surface of the chip packaging structure, which is far away from the carrier plate, so that the thicknesses of the plastic packaging layer and the transition layer packaging structure are smaller than or equal to the thickness of the chip, and one end of the chip, which is provided with an input/output interface, is exposed; s45, arranging a dielectric material layer on one thinned surface of the chip packaging structure; and S46, arranging a metal circuit layer on the dielectric material layer, wherein the metal circuit layer is electrically connected with the output/output interface.

Referring to fig. 9, the present invention further provides a structure diagram of a fan-out package structure for reducing plastic deformation of a chip, where the fan-out package structure 100 for reducing plastic deformation of a chip includes: the chip package structure comprises a dielectric material layer 106, a plurality of chips 103, a plurality of transition layer package structures 104, a molding compound layer 105 and a metal circuit layer 107.

Wherein the dielectric material layer 106 is formed with a through hole. The plurality of chips 103 are distributed on the upper surface of the dielectric material layer 106 in an array; a plurality of transition layer package structures 104 are disposed on the upper surface of the dielectric material layer 106, and each transition layer package structure 104 encapsulates a chip 103; the molding compound layer 105 is disposed on the upper surface of the dielectric material layer 106 and wraps each of the transition layer package structures 104, and the thermal expansion coefficient of the transition layer package structure 104 is smaller than that of the molding compound layer 105. The metal circuit layer 107 is disposed on the lower surface of the dielectric material layer 106 and electrically connected to the input/output port 1031 of the chip 103.

It will be appreciated that in some embodiments, the metal trace layer 107 is further provided with an ink layer on which a conductive metal pad is also provided.

Specifically, the transition layer package structure 104 is made of polyimide, cyanate ester type epoxy resin, or liquid epoxy resin based encapsulant doped with inorganic substances to adjust the thermal expansion coefficient. The transition layer encapsulation structure 104 is formed by a dropping method.

The molding layer 105 is made of epoxy resin. For example, bisphenol A type epoxy resin, brominated epoxy resin, novolak type epoxy resin, bisphenol F type epoxy resin, hydrogenated bisphenol A type epoxy resin, glycidyl amine type epoxy resin, hydantoin type epoxy resin, alicyclic epoxy resin, trishydroxyphenylmethane type epoxy resin, bis-bisphenol type or bisphenol type epoxy resin or a mixture thereof, bisphenol S type epoxy resin, bisphenol A novolak type epoxy resin, tetraphenylphenol alcohol (phenylylol) ethane type epoxy resin, heterocyclic type epoxy resin, diglycidyl resin, tetraglycidyl benzoic acid dimethylolethane resin, epoxy resin containing naphthyl group, epoxy resin containing nitrogen, epoxy resin having dicyclopentadiene skeleton, glycidyl methacrylate copolymer type epoxy resin, copolymerized epoxy resin of cyclohexylmaleimide and glycidyl methacrylate, CTBN-modified epoxy resin, and the like. Of course, these epoxy resins may be used alone or in combination of 2 or more.

It is understood that, as shown in fig. 10, in some embodiments, the molding layer 105 and the transition layer package structure 104 are flush with an end surface of the chip at a side away from the dielectric material layer 106.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in multiple embodiments or examples of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.