Packaging method, panel assembly, wafer package and chip package
阅读说明:本技术 封装方法、面板组件、晶圆封装体以及芯片封装体 (Packaging method, panel assembly, wafer package and chip package ) 是由 周辉星 于 2019-09-26 设计创作,主要内容包括:本公开的实施例提供一种封装方法、面板组件、晶圆封装体以及芯片封装体。该半导体器件封装方法包括:提供至少一个晶圆,所述晶圆包括彼此相对的第一面和第二面以及连接所述第一面和所述第二面的侧面,所述第一面为活性面;在所述至少一个晶圆的侧面形成围绕所述晶圆的连接部,以使所述晶圆与所述连接部形成一面板组件,所述连接部包括与所述晶圆的第一面位于同一侧的第三面和与所述晶圆的第二面位于同一侧的第四面,所述第三面与所述第一面形成所述面板组件的待处理面;以及在所述晶圆的第一面上形成第一介电层。根据本公开实施例的封装方法可以提高晶圆的封装效率以及利用率。(Embodiments of the present disclosure provide a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method comprises the following steps: providing at least one wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the first surface is an active surface; forming a connecting part surrounding the wafer on the side surface of the at least one wafer so that the wafer and the connecting part form a panel assembly, wherein the connecting part comprises a third surface and a fourth surface, the third surface and the fourth surface are positioned on the same side of the first surface of the wafer and the second surface of the wafer, and the third surface and the first surface form a surface to be processed of the panel assembly; and forming a first dielectric layer on the first side of the wafer. According to the packaging method disclosed by the embodiment of the disclosure, the packaging efficiency and the utilization rate of the wafer can be improved.)
1. A semiconductor device packaging method, comprising:
providing at least one wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the first surface is an active surface;
forming a connecting part surrounding the wafer on the side surface of the at least one wafer so that the wafer and the connecting part form a panel assembly, wherein the connecting part comprises a third surface and a fourth surface, the third surface and the fourth surface are positioned on the same side of the first surface of the wafer and the second surface of the wafer, and the third surface and the first surface form a surface to be processed of the panel assembly; and
a first dielectric layer is formed on a first side of the wafer.
2. The method of claim 1, wherein a first dielectric layer is formed on the first side of the wafer prior to forming the connection.
3. The method of claim 1, wherein the first dielectric layer is formed on a surface to be processed of the panel assembly after the connection portion is formed.
4. The method of any of claims 1-3, further comprising: after forming a first dielectric layer on the first side of the wafer, forming a conductive layer on the to-be-processed side of the panel assembly to cover at least the first side of the wafer.
5. The method of claim 4, further comprising: before forming the conductive layer, forming a through hole in the first dielectric layer to expose a pad on the first surface of the wafer.
6. A method according to any of claims 1-3, wherein a plurality of wafers are provided and separated from each other in the panel assembly.
7. The method of claim 4, wherein forming a conductive layer on the side of the panel assembly to be processed to cover at least the first side of the wafer comprises: and forming an effective conductive layer on the first surface of the wafer and forming a dummy conductive layer on the third surface of the connecting part.
8. The method of claim 7, wherein the dummy conductive layer is formed at least within an annular region surrounding the wafer, and the annular region has a width greater than 5 mm.
9. The method of claim 4, wherein the conductive layer is formed using an electroplating process.
10. The method of any of claims 1-3, wherein forming the connection comprises: and forming a conductive piece which is exposed from the third surface of the connecting part, is positioned in the peripheral area of the panel assembly and is spaced from the wafer.
11. The method of any of claims 1-3, wherein forming the connection comprises:
placing the wafer on a carrier plate, wherein the first surface of the wafer faces the carrier plate;
forming a plastic package layer on the carrier plate and the wafer so that the side face and the second face of the wafer are wrapped by the plastic package layer; and
and separating the carrier plate to expose the surface to be processed of the panel assembly.
12. The method of any of claims 1-3, wherein forming the connection comprises:
placing the wafer on a carrier plate, wherein the second surface of the wafer faces the carrier plate, placing a cavity die with a through opening on the carrier plate so that the wafer is positioned in the opening, and forming a fixing material in a gap between the side wall of the opening and the side surface of the wafer so as to connect the wafer and the cavity die together.
13. The method of any of claims 1-3, wherein forming the connection comprises:
placing the wafer on a carrier plate, wherein the first surface faces the carrier plate, placing a cavity die with a through opening on the carrier plate so that the wafer is positioned in the opening, and forming a fixing material in a gap between the side wall of the opening and the side surface of the wafer so as to connect the wafer and the cavity die together;
and separating the carrier plate to expose the surface to be processed of the panel assembly.
14. The method of claim 12 or 13, wherein the material of the cavity mold comprises a conductive material.
15. The method of claim 4, further comprising: a second dielectric layer is formed on a side of the conductive layer remote from the panel assembly to cover at least a portion of the conductive layer.
16. The method of claim 1, further comprising: and forming a functional layer on the surface to be processed of the panel assembly after forming the first dielectric layer on the first surface of the wafer.
17. A panel assembly, comprising:
at least one wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the first surface is an active surface;
the connecting part is positioned on the side surface of the wafer and is connected to the wafer, the connecting part comprises a third surface and a fourth surface, the third surface and the fourth surface are positioned on the same side of the first surface of the wafer, and the third surface and the first surface form a surface to be processed of the panel assembly; and
and the first dielectric layer is at least positioned on the first surface of the wafer.
18. The panel assembly of claim 17, wherein a surface of the first dielectric layer is substantially planar with the third face of the connecting portion.
19. The panel assembly of claim 17, wherein the third surface of the connecting portion is substantially planar with the first surface of the wafer, and the first dielectric layer is on the surface of the panel assembly to be processed.
20. The panel assembly of claim 17, comprising a plurality of wafers spaced apart from one another.
21. The panel assembly of any of claims 17-20, further comprising: and the conducting layer is positioned on the surface to be processed and positioned on one side of the first dielectric layer, which is far away from the wafer.
22. The panel assembly of claim 21, wherein the first dielectric layer includes vias therein to expose pads on the first side of the wafer.
23. The panel assembly of claim 21, wherein the conductive layer comprises an active conductive layer on a first side of the wafer and a dummy conductive layer on a third side of the connection.
24. The panel assembly of claim 23, wherein the dummy conductive layer is formed at least within an annular area surrounding the wafer, and the annular area has a width greater than 5 mm.
25. The panel assembly of claim 17, further comprising an electrically conductive member exposed from a third face of the connecting portion in a peripheral region of the panel assembly and spaced from the wafer.
26. The panel assembly of claim 17, wherein the connection comprises a first portion at a side of the wafer and a second portion at a second side of the wafer, the first and second portions being integrally connected.
27. The panel assembly of claim 26, wherein the connecting portion comprises a molding layer.
28. The panel assembly of claim 17, wherein the connection comprises a cavity die having an opening therethrough, the wafer is positioned within the opening, and a gap between a sidewall of the opening and a side of the wafer is provided with a securing material to connect the wafer and the cavity die together.
29. The panel assembly of claim 28, wherein the material of the cavity mold comprises a conductive material.
30. The panel assembly of claim 21, further comprising: and the second dielectric layer is positioned on one side of the conductive layer, which is far away from the wafer, and covers at least one part of the conductive layer.
31. The panel assembly of claim 26, wherein a second portion of the connection at the second side of the wafer has a predetermined material and thickness to mitigate or eliminate warpage of the panel assembly.
32. A wafer package, comprising:
the wafer comprises a first surface, a second surface and a side surface, wherein the first surface and the second surface are opposite to each other, the side surface is connected with the first surface and the second surface, and the first surface is an active surface;
the plastic packaging layer is positioned on at least one of the side surface and the second surface of the wafer;
the first dielectric layer is located on the first surface of the wafer.
33. The wafer package of claim 32, further comprising: and the conducting layer is positioned on one side of the first dielectric layer far away from the wafer.
34. The wafer package of claim 33, further comprising: and the second dielectric layer is positioned on one side of the conductive layer, which is far away from the wafer, so as to cover at least part of the conductive layer.
35. The wafer package of claim 32, wherein the molding layer includes a portion on the second side of the wafer, and the portion of the molding layer on the second side of the wafer has a predetermined material and thickness to mitigate or eliminate warpage of the wafer package.
36. A semiconductor chip package, comprising:
a die including first and second faces opposite to each other and a side face connecting the first and second faces, the first face being an active face;
the plastic packaging layer is positioned on the second surface of the bare chip;
a first dielectric layer on the first side of the die.
37. The semiconductor chip package of claim 36, further comprising: a conductive layer on a side of the first dielectric layer remote from the die.
38. The semiconductor chip package of claim 37, wherein the first dielectric layer includes vias therein to expose pads on the first side of the die.
39. The semiconductor chip package of claim 36, further comprising: a second dielectric layer on a side of the conductive layer remote from the die to cover at least a portion of the conductive layer.
40. The semiconductor chip package of claim 36, wherein the molding layer has a predetermined material and thickness to mitigate or eliminate warpage of the semiconductor chip package.
Technical Field
Embodiments of the present disclosure relate to a semiconductor device packaging method, a panel assembly, a wafer package, and a semiconductor chip package.
Background
In recent years, as electronic devices are reduced in size and weight and demand for information processing increases, chips that are reduced in size and weight and have a high operation speed have become mainstream demands in the market. Chip Scale package (csp) is the most advanced form of integrated circuit package because of its small size and thin thickness, and because of its short channel, the heat generated by the chip can be conducted to the outside, its reliability for long-time operation is high, its circuit impedance is small, and its operation speed is fast. Therefore, the CSP packaged chip is rapidly gaining application in electronic devices.
Wafer level chip scale packaging (wafer CSP) is a process in which a conductive layer is formed on the active side of a single wafer (wafer) by processes such as photoresist stripping, photolithography, development, sputtering, plating, and film stripping. And forming a dielectric layer on the conductive layer, and dividing the wafer formed with the conductive layer and the dielectric layer into single chips to finish packaging.
Disclosure of Invention
There is provided a semiconductor device packaging method according to at least one embodiment of the present disclosure, including: providing at least one wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the first surface is an active surface; forming a connecting part surrounding the wafer on the side surface of the at least one wafer so that the wafer and the connecting part form a panel assembly, wherein the connecting part comprises a third surface and a fourth surface, the third surface and the fourth surface are positioned on the same side of the first surface of the wafer and the second surface of the wafer, and the third surface and the first surface form a surface to be processed of the panel assembly; and forming a first dielectric layer on the first side of the wafer.
In some examples, a first dielectric layer is formed on the first side of the wafer prior to forming the connection.
In some examples, the first dielectric layer is formed on the surface to be processed of the panel assembly after the connection portion is formed.
In some examples, the method further comprises: after forming a first dielectric layer on the first side of the wafer, forming a conductive layer on the to-be-processed side of the panel assembly to cover at least the first side of the wafer.
In some examples, the method further comprises: before forming the conductive layer, forming a through hole in the first dielectric layer to expose a pad on the first surface of the wafer.
In some examples, a plurality of wafers are provided and are spaced apart from one another in the panel assembly.
In some examples, forming a conductive layer on the side to be processed of the panel assembly to cover at least the first side of the wafer comprises: and forming an effective conductive layer on the first surface of the wafer and forming a dummy conductive layer on the third surface of the connecting part.
In some examples, the dummy conductive layer is formed at least in an annular region surrounding the wafer, and the annular region has a width greater than 5 mm.
In some examples, the conductive layer is formed using an electroplating process.
In some examples, forming the connection portion includes: and forming a conductive piece which is exposed from the third surface of the connecting part, is positioned in the peripheral area of the panel assembly and is spaced from the wafer.
In some examples, forming the connection portion includes: placing the wafer on a carrier plate, wherein the first surface of the wafer faces the carrier plate; forming a plastic package layer on the carrier plate and the wafer so that the side face and the second face of the wafer are wrapped by the plastic package layer; and separating the carrier plate to expose the surface to be processed of the panel assembly.
In some examples, forming the connection portion includes: placing the wafer on a carrier plate, wherein the second surface of the wafer faces the carrier plate, placing a cavity die with a through opening on the carrier plate so that the wafer is positioned in the opening, and forming a fixing material in a gap between the side wall of the opening and the side surface of the wafer so as to connect the wafer and the cavity die together.
In some examples, forming the connection portion includes: placing the wafer on a carrier plate, wherein the first surface faces the carrier plate, placing a cavity die with a through opening on the carrier plate so that the wafer is positioned in the opening, and forming a fixing material in a gap between the side wall of the opening and the side surface of the wafer so as to connect the wafer and the cavity die together; and separating the carrier plate to expose the surface to be processed of the panel assembly.
In some examples, the material of the cavity mold comprises a conductive material.
In some examples, the method further comprises: a second dielectric layer is formed on a side of the conductive layer remote from the panel assembly to cover at least a portion of the conductive layer.
In some examples, the method further comprises: and forming a functional layer on the surface to be processed of the panel assembly after forming the first dielectric layer on the first surface of the wafer.
According to at least one embodiment of the present disclosure, there is provided a panel assembly including: at least one wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other and a side surface connecting the first surface and the second surface, and the first surface is an active surface; the connecting part is positioned on the side surface of the wafer and is connected to the wafer, the connecting part comprises a third surface and a fourth surface, the third surface and the fourth surface are positioned on the same side of the first surface of the wafer, and the third surface and the first surface form a surface to be processed of the panel assembly; and the first dielectric layer is at least positioned on the first surface of the wafer.
In some examples, a surface of the first dielectric layer is substantially coplanar with the third face of the connection portion.
In some examples, the third surface of the connecting portion is substantially in the same plane as the first surface of the wafer, and the first dielectric layer is located on the surface to be processed of the panel assembly.
In some examples, the panel assembly includes a plurality of wafers disposed in spaced relation to one another.
In some examples, the panel assembly further comprises: and the conducting layer is positioned on the surface to be processed and positioned on one side of the first dielectric layer, which is far away from the wafer.
In some examples, the first dielectric layer includes vias therein to expose pads on the first side of the wafer.
In some examples, the conductive layer includes an active conductive layer on the first side of the wafer and a dummy conductive layer on the third side of the connection.
In some examples, the dummy conductive layer is formed at least in an annular region surrounding the wafer, and the annular region has a width greater than 5 mm.
In some examples, the panel assembly further includes an electrically conductive member exposed from a third face of the connecting portion, located in a peripheral region of the panel assembly and spaced apart from the wafer.
In some examples, the connection includes a first portion at a side of the wafer and a second portion at a second side of the wafer, the first portion and the second portion being integrally connected.
In some examples, the connection portion includes a molding layer.
In some examples, the connection portion includes a cavity die having an opening therethrough, the wafer is located within the opening, and a gap between a sidewall of the opening and a side surface of the wafer is provided with a fixing material to connect the wafer and the cavity die together.
In some examples, the material of the cavity mold comprises a conductive material.
In some examples, the panel assembly further comprises: and the second dielectric layer is positioned on one side of the conductive layer, which is far away from the wafer, and covers at least one part of the conductive layer.
In some examples, a second portion of the connection at the second side of the wafer has a predetermined material and thickness to mitigate or eliminate warpage of the panel assembly.
According to at least one embodiment of the present disclosure, there is provided a wafer package including: the wafer comprises a first surface, a second surface and a side surface, wherein the first surface and the second surface are opposite to each other, the side surface is connected with the first surface and the second surface, and the first surface is an active surface; the plastic packaging layer is positioned on at least one of the side surface and the second surface of the wafer; the first dielectric layer is located on the first surface of the wafer.
In some examples, the wafer package further includes: and the conducting layer is positioned on one side of the first dielectric layer far away from the wafer.
In some examples, the wafer package further includes: and the second dielectric layer is positioned on one side of the conductive layer, which is far away from the wafer, so as to cover at least part of the conductive layer.
In some examples, the molding layer includes a portion on the second side of the wafer, and the portion of the molding layer on the second side of the wafer has a predetermined material and thickness to mitigate or eliminate warpage of the wafer package.
There is provided in accordance with at least one embodiment of the present disclosure a semiconductor chip package including: a die including first and second faces opposite to each other and a side face connecting the first and second faces, the first face being an active face; the plastic packaging layer is positioned on the second surface of the bare chip; a first dielectric layer on the first side of the die.
In some examples, the semiconductor chip package further includes: a conductive layer on a side of the first dielectric layer remote from the die.
In some examples, the first dielectric layer includes vias therein to expose pads on the first side of the die.
In some examples, the semiconductor chip package further includes: a second dielectric layer on a side of the conductive layer remote from the die to cover at least a portion of the conductive layer.
In some examples, the molding layer has a predetermined material and thickness to mitigate or eliminate warpage of the semiconductor chip package.
According to the semiconductor device packaging method, the panel assembly, the wafer package and the semiconductor chip package of the present disclosure, it is possible to prevent a portion of a wafer from being clamped in a packaging process by forming the panel assembly, thereby preventing an invalid region from being formed on the wafer; in addition, a dummy conductive layer can be formed on the periphery of the wafer of the panel assembly, so that the formation of wafer invalid areas caused by uneven edge properties of the conductive layer is avoided; because a plurality of wafers can be integrated on the panel component, a plurality of wafers can be processed at the same time, and the packaging efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.
Fig. 1A is a schematic cross-sectional view of a semiconductor wafer used in a semiconductor device packaging method according to an embodiment of the present disclosure;
FIG. 1B is a schematic plan view of the semiconductor wafer shown in FIG. 1A;
fig. 2A is a schematic cross-sectional view of a panel assembly formed by a semiconductor packaging method according to an embodiment of the disclosure;
fig. 2B is a schematic plan view of a panel assembly formed by the semiconductor packaging method according to the embodiment of the disclosure;
FIG. 3A is a schematic cross-sectional view illustrating a dielectric layer formed on a wafer according to a semiconductor packaging method of the present disclosure;
FIG. 3B is a schematic cross-sectional view illustrating another exemplary dielectric layer formed on a wafer according to a semiconductor packaging method of the present disclosure;
fig. 3C is a schematic cross-sectional view illustrating the connection of the wafers with the dielectric layers formed thereon into a panel assembly according to the semiconductor packaging method of the embodiment of the disclosure;
fig. 4A is a schematic cross-sectional view illustrating a dielectric layer formed on a panel assembly before a conductive layer is formed in a semiconductor packaging method according to an embodiment of the disclosure;
fig. 4B is another schematic cross-sectional view illustrating a dielectric layer formed on the panel assembly before forming the conductive layer in the semiconductor packaging method according to the embodiment of the disclosure;
fig. 5A is a schematic plan view illustrating a structure of forming a conductive member in a connection part and a conductive layer on a surface to be processed of a panel assembly in a semiconductor device packaging method according to an embodiment of the present disclosure;
fig. 5B is a schematic cross-sectional structure diagram of a method of packaging a semiconductor device according to an embodiment of the present disclosure, in which a conductive member is formed in a connection portion and a conductive layer is formed on a surface to be processed of a panel assembly;
fig. 6A is a schematic cross-sectional structure diagram corresponding to a part of the processing steps (forming the connection portion) of the semiconductor packaging method according to the embodiment of the disclosure;
fig. 6B is a schematic plan view illustrating a portion of the processing steps (forming the connection portion) of the semiconductor packaging method according to the embodiment of the disclosure;
fig. 7 is a schematic cross-sectional structure diagram of a part of the process in the semiconductor packaging method according to an embodiment of the present disclosure;
fig. 8A is an enlarged schematic partial cross-sectional view after a seed layer is formed on a surface to be processed of a panel assembly in a semiconductor packaging method according to an embodiment of the disclosure;
fig. 8B is a schematic cross-sectional structure diagram after a conductive layer is formed on a surface to be processed of a panel assembly in the semiconductor packaging method according to the embodiment of the present disclosure;
fig. 9A is a schematic cross-sectional view illustrating a dielectric layer formed on a panel assembly on which a conductive layer is formed in a semiconductor packaging method according to an embodiment of the present disclosure;
fig. 9B is another schematic cross-sectional view illustrating a dielectric layer formed on the panel assembly with the conductive layer formed thereon according to the semiconductor packaging method of the embodiment of the present disclosure;
fig. 9C is a schematic cross-sectional view illustrating a dielectric layer formed on a wafer on which a conductive layer is formed according to a semiconductor packaging method of the present disclosure;
fig. 9D is a schematic cross-sectional view illustrating a dielectric layer formed on a wafer with a conductive layer formed thereon according to an embodiment of the present disclosure;
fig. 10 is a schematic cross-sectional view illustrating a semiconductor packaging method according to an embodiment of the present disclosure after solder is formed on the dielectric layer;
FIGS. 11A-11B are schematic cross-sectional views illustrating another exemplary method for forming a panel assembly according to the semiconductor package method of the present disclosure;
12A-12C are schematic cross-sectional views illustrating another method for forming a panel assembly according to the semiconductor package method of the present disclosure;
FIG. 13 is a cross-sectional structural view of a panel assembly according to an embodiment of the present disclosure;
14A-14C are cross-sectional views of wafer packages according to embodiments of the present disclosure;
fig. 15A-15D are schematic cross-sectional views of semiconductor chip packages according to embodiments of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In the wafer level chip size packaging process in the related art, since each process step is performed by using a single wafer, the chip packaging production efficiency is low, and the packaging cost is high. On the other hand, in the process of forming a conductive layer of a wafer level chip scale package (wafer CSP), it is necessary to form a conductive layer by immersing a wafer in a processing liquid in a processing bath of a conductive layer forming apparatus after clamping the periphery of the wafer with a conductive jig of the conductive layer forming apparatus. However, this process requires that a region for clamping by the conductive clamp be left at the periphery of the wafer, which includes an electrical connection region corresponding to the electrical connection contact and a sealing region corresponding to the sealing member. Therefore, an area of at least 3mm of the periphery of the wafer is an inactive area, i.e., an area of the periphery of the wafer that cannot be used for packaging production chips. The presence of such inactive areas greatly increases the price of the package due to the high price of the wafer. On the other hand, the current density in the forming process of the conducting layer is not uniformly distributed on the surface of the wafer, so that the conducting layer formed in the peripheral area of the wafer is thicker, the conducting layer formed in the inner area of the wafer is thinner, and the parameters of the same batch of packaged products are unstable. The above three drawbacks of wafer level chip scale packaging limit the applications of wafer level CSPs.
Embodiments of the present disclosure provide a method of packaging a semiconductor device. In the packaging method, a connecting part is formed on the periphery of at least one wafer to form a panel assembly. The surface of the connecting part of the panel component, which is positioned on the same side with the active surface of the wafer, and the active surface of the wafer form a surface to be processed. Packaging processing is carried out on the surface to be processed of the panel assembly, so that the clamping area can fall on the connecting part on the periphery of the wafer, and an invalid area is prevented from being formed in the peripheral area of the wafer. In addition, the region where the conductive layer is formed can be expanded to a partial region on the connection portion of the wafer periphery, so that the properties of the conductive layer formed on the wafer can be made uniform. In addition, under the condition that the panel assembly comprises a plurality of wafers, the wafers can be packaged simultaneously, so that the packaging efficiency is greatly improved. Further technical effects of the present disclosure will be described in detail with reference to the following embodiments.
Fig. 1A is a schematic cross-sectional view of a semiconductor wafer used in a semiconductor device packaging method according to an embodiment of the present disclosure; fig. 1B is a schematic plan view of the semiconductor wafer. A semiconductor wafer is a semiconductor device structure, which is also called a semiconductor chip (wafer), formed after a circuit structure is formed on a semiconductor substrate through a semiconductor process. The present disclosure is not particularly limited to the type and size of the semiconductor wafer. For example, as shown in fig. 1A, a
In a semiconductor device packaging method according to an embodiment of the present disclosure, as shown in fig. 2A, a
As shown in fig. 2A, in some examples, the
In some examples, as shown in fig. 2A, the
Fig. 2B is a schematic plan view of the cross-sectional structure of fig. 2A, and in particular, fig. 2A corresponds to the cross-sectional structure taken at line AA' of fig. 2B. As shown in fig. 2B, the resulting
As shown in fig. 2B, the plurality of
The planar shape of the panel assembly shown in fig. 2B is substantially rectangular. However, embodiments according to the present disclosure are not limited thereto. The planar shape of the panel assembly may be arbitrarily adjusted depending on the number of semiconductor wafers to be integrated, the arrangement, the equipment for performing the plating process, and the like.
According to the semiconductor package device packaging method of the embodiment of the disclosure, after the panel assembly is formed, a conductive layer may be formed on the surface to be processed of the panel assembly to cover at least the active surface of the wafer. For example, the conductive layer may be electrically connected to a pad on the wafer through a via in the insulating protection layer on the wafer. For example, the conductive layer may include conductive traces and conductive pillars. After the conductive layer is formed, a dielectric layer may also be formed over the conductive layer, which may serve to protect the conductive layer and insulate the various conductive traces and conductive posts. The formation of the conductive and dielectric layers will be described in more detail later. In addition, a composite structure formed of a conductive layer and a dielectric layer may be repeatedly stacked on a wafer, which is not particularly limited according to an embodiment of the present disclosure.
According to some embodiments of the present disclosure, as shown in fig. 3A and 3B, a
In some other embodiments according to the present disclosure, the dielectric layer may be formed after the
For example, the following materials and processes may be used to form the
According to the semiconductor device packaging method of some embodiments of the present disclosure, the step of forming the connection part may further include forming a conductive member. For example, the conductive member and the wafer are spaced apart from each other and exposed from the front surface of the connection portion. For example, the conductive member is formed at a peripheral region of the panel assembly.
Fig. 5A and 5B are schematic views illustrating the formation of conductive members in connection parts and the formation of a conductive layer on a surface to be processed of a panel assembly in a semiconductor device packaging method according to some embodiments of the present disclosure, and fig. 5B is a cross-sectional view taken along line BB' in fig. 5A (in addition, fig. 5B additionally illustrates a plated
As shown in fig. 5A and 5B, the step of forming the connection portion includes forming a
For example, according to the semiconductor device packaging method of the embodiment of the present disclosure, the conductive layer may be formed by an electroplating process. Steps of forming a conductive layer according to some examples of the present disclosure are described below in conjunction with fig. 5B. As shown in fig. 5B, a
As shown in fig. 5B, the
Although the
Although the conductive layer is formed by an electroplating process in the above embodiments, embodiments according to the present disclosure are not limited thereto, and the
In the structures shown in fig. 5A and 5B, the conductive layer is described as being formed on the active side of the wafer and in an
The technical solution and the corresponding technical effect of the present disclosure will be further described below with reference to some embodiments of the present disclosure. As can be seen from the above description, the
Fig. 6A is a cross-sectional view corresponding to a partial step process (forming a connection portion) of a semiconductor packaging method according to some embodiments of the present disclosure; fig. 6B is a schematic plan view illustrating a partial step process (forming a connection portion) of the semiconductor packaging method according to the embodiment of the disclosure. Fig. 6A is a sectional view taken at line CC' of fig. 6B. Although the cross-sectional view of fig. 6A shows the
In some examples of the present disclosure, as shown in fig. 6A, the
In some examples, as shown in fig. 6A and 6B, before the
In some examples, as shown in fig. 6A and 6B, a
After the
For example, the
For example, the
As shown in fig. 6A, the
For example, in the case of forming the
In some examples, as shown in fig. 6A, an
As shown in fig. 7, after a
After the panel assembly is formed, a conductive layer or the like may be formed on a surface to be processed of the panel assembly. In some examples, the packaging process includes the steps of forming a seed layer, conductive traces, conductive pillars, a dielectric layer, and solder. These packaging process steps are illustratively described below.
Fig. 8A is an enlarged partial cross-sectional view of a
For example, the process of forming the
In some examples according to the present disclosure, after forming the
In some examples according to the present disclosure, as shown in fig. 9B, after the
Fig. 9A and 9B illustrate a step of forming a
The step of thinning the
Although not shown, the
In some examples of the disclosure, the wafer is separated to form individual wafer structures, for example, after forming the
For example, the material of the
As shown in fig. 10, on the wafer on which the
The above embodiments describe the process of forming the conductive layer on the panel assembly, and forming the solder on the wafer after forming the conductive layer. Although the
In addition, it should be noted that although the
The above embodiments have been described by taking the example of the
Fig. 11A and 11B are schematic cross-sectional structures of forming a panel assembly according to another embodiment of the present disclosure. As shown in fig. 11A, the
As can be seen from fig. 11A and 11B, the
Fig. 12A-12C are schematic cross-sectional structures forming a panel assembly according to another embodiment of the present disclosure. As shown in fig. 12A, the
As can be seen from fig. 12A-12C, in this embodiment, the
For example, the material of the cavity mold 205' may be, for example, a conductive material. In this case, the step of forming the conductive member in the embodiment corresponding to fig. 5A and 5B or fig. 6A and 6B described above may be omitted. In one example, the material of the cavity mold may be formed from FR4 material. The FR4 material is, for example, a resin fiberboard having a copper layer on its surface, and thus, it is electrically conductive.
For example, a scheme of forming the connection portion using the cavity mold 201' having the opening is different from the above-described scheme of encapsulating the wafer by the mold layer, which has no portion provided on the back surface of the wafer. Therefore, the thickness of the cavity mold 201' can be approximately the same as the thickness of the wafer to form a relatively flat surface to be processed on the panel assembly.
It should be noted that the panel assembly formed as shown in the embodiment of fig. 11A-12C may employ various steps and processes described above with respect to the embodiment of fig. 8A-10 in subsequent processing. For example, the steps of forming the
Also, it should be noted that although the embodiment of fig. 11A-12C is described with reference to the
After forming the solder, the semiconductor packaging process according to embodiments of the present disclosure may further include dividing the wafer into individual chip packages. For example, as shown in fig. 15A and 15B, after the wafer is divided, individual chip packages may be formed. Fig. 15A and 15B show the die packages singulated with connections formed on the sides and back of the wafer, for example, these structures may correspond to the panel assembly fabrication process of fig. 6A-9B. In this case, the back surface of the chip package may also leave a portion where the connection portion is formed on the back surface of the wafer, which forms the back
The above description has been made with respect to the semiconductor device packaging method according to some embodiments of the present disclosure, however, the steps, structures, materials, or the like of the above-described respective embodiments may be combined with or substituted for each other without conflict. It should be noted that forming a layer on a surface is not limited to forming the layer directly on the surface, but may also include interposing another layer between the surface and the layer.
Embodiments according to the present disclosure also provide a panel assembly and a semiconductor chip package. For example, the panel assembly is the panel assembly formed in the semiconductor device packaging method according to the above-described embodiment and the semiconductor chip package formed after package dicing, and therefore, the description in the above-described embodiments of the semiconductor device packaging method is applicable to both the panel assembly and the semiconductor package.
For example, as shown in fig. 2A, the
For example, as shown in fig. 2A, the
For example, as shown in fig. 8B, the panel assembly may further include a
For example, as shown in fig. 6A, the
For example, as shown in fig. 11B or 12C, the
For example, as shown in fig. 8B, 11B, or 12C, the panel assembly further includes a
For example, as shown in fig. 5A and 5B, the panel assembly may further include a
For example, as shown in fig. 11B and 12C, the material of the cavity mold includes a conductive material, and thus, the cavity mold itself can be used as an electrical contact point in an electroplating process, eliminating a separate step of fabricating a conductive member. For example, the material of the cavity mold includes FR4 material.
For example, as shown in FIG. 3C, in the panel assembly, a
For example, as shown in fig. 4A and 4B, the panel assembly includes a
For example, as shown in fig. 13, the panel assembly further includes a conductive layer (e.g., which may include
It should be noted that, for materials, structures, technical effects, and the like that are not mentioned in the description of the panel assembly, reference may be made to the above embodiments of the semiconductor device packaging method, and details are not described herein.
Embodiments according to the present disclosure also provide a wafer package separated from the panel assembly. Fig. 14A-14C are schematic cross-sectional views of several exemplary wafer packages according to embodiments of the present disclosure. As shown in fig. 14A, the
It should be noted that the wafer package according to the embodiment of the present disclosure is, for example, a structure separated from the display panel, and during the process of separating the wafer, a portion of the connection portion located on the side surface and/or the second surface of the wafer is retained. Therefore, for materials, structures, technical effects, and the like that are not mentioned in the description of the wafer package, reference may be made to the above-mentioned embodiments of the panel assembly, and further description is omitted here.
There is also provided, in accordance with an embodiment of the present disclosure, a semiconductor chip package. As shown in fig. 15A, the semiconductor chip package includes a
In addition, as shown in fig. 15A, in the semiconductor chip package, a conductive layer 600 (e.g., including
For example, as shown in fig. 15B, in the semiconductor chip package, a
In addition, fig. 15C and 15D are diagrams corresponding to the semiconductor chip package formed under the condition that the connection portion is not formed on the back surface of the wafer in the manufacturing process of the panel assembly, and the description is omitted here.
It should be noted that, for materials, structures, technical effects, and the like that are not mentioned in the description of the semiconductor chip package, reference may be made to the embodiments of the semiconductor device packaging method, the panel assembly, and the wafer package, and no further description is given here.
The above description is intended to be illustrative of the present invention and not to limit the scope of the invention, which is defined by the claims appended hereto.
The present application claims the priority of the provisional patent application serial No. 10201902686R for singapore filed on 26/3/2019, the priority of the provisional patent application serial No. 10201903126W filed on 8/4/2019, the priority of the provisional patent application serial No. 10201905866P filed on 25/6/2019, the priority of the provisional patent application serial No. 10201908063W filed on 4/9/2019, and the chinese patent application serial No. 201910390416.1 filed on 10/5/2019, the disclosures of which are incorporated herein by reference in their entirety as part of the present application.
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