阅读说明：本技术 高速放大器 (High speed amplifier ) 是由 A·M·A·阿里 H·迪恩克 于 2014-08-28 设计创作，主要内容包括：本发明涉及高速放大器。一种电路可以包括与输出直接连接的一个以上的晶体管,以及电感网络。所述电感网络可以连接到至少一个晶体管的源极节点,以补偿输出的电容。因此,电路的响应时间可以减小,并且可以提高电路的非主导频率响应极点频率。(The present invention relates to a high speed amplifier. A circuit may include more than one transistor directly connected to an output, and an inductive network. The inductive network may be connected to a source node of the at least one transistor to compensate for capacitance of the output. Thus, the response time of the circuit may be reduced and the non-dominant frequency response pole frequency of the circuit may be increased.)

1. A circuit, comprising:

one or more transistors directly connected to the output node at a drain node thereof;

an inductive network connected to a source node of the at least one transistor; and

a driver connected to a drain node of the at least one transistor,

wherein an inductance L of the inductive network is based on a transconductance gm of the circuit and a capacitance C at the output node, and the inductive network compensates for the capacitance of the output node,

wherein the inductance L is according to L ═ kC/gm²Where k is a constant.

2. The circuit of claim 1, wherein the one or more transistors are connected in series with each other to form an amplifier.

3. The circuit of claim 1, wherein the inductive network comprises an inductor.

4. The circuit of claim 1, wherein the inductive network comprises an inductor connected at a first terminal to the at least one transistor and at a second terminal to a DC voltage.

5. The circuit of claim 1, wherein the inductive network comprises an inductor comprising a metal layer and a substrate.

6. The circuit of claim 1, wherein the inductive network comprises an inductor having a capacitance value between 100 and 350 picohenries.

7. The circuit of claim 1, wherein the inductive network comprises an inductor having a handle shape or a spiral shape.

8. A circuit, comprising:

one or more transistors directly connected to the output node at a drain node thereof;

an inductive network connected to a source node of the at least one transistor; and

a driver connected to a drain node of the at least one transistor,

wherein an inductance L of the inductive network is based on a transconductance gm of the circuit and a capacitance C at the output node, and the inductive network increases a response time of the circuit to an AC input signal,

wherein the inductance L is according to L ═ kC/gm²Where k is a constant.

9. The circuit of claim 8, wherein the one or more transistors are connected in series with each other to form an amplifier.

10. The circuit of claim 8, wherein the inductive network comprises an inductor.

11. The circuit of claim 8, wherein the inductive network comprises an inductor connected at a first terminal to the at least one transistor and at a second terminal to the DC voltage.

12. The circuit of claim 8, wherein the inductive network comprises an inductor comprising a metal layer and a substrate.

13. The circuit of claim 8, wherein the inductive network comprises an inductor having a capacitance value between 100 and 350 picohenries.

14. The circuit of claim 8, wherein the inductive network comprises an inductor having a handle shape or a spiral shape.

15. A circuit, comprising:

one or more transistors directly connected to the output node at a drain node thereof;

an inductive network connected to a source node of the at least one transistor; and

a driver connected to a drain node of the at least one transistor,

wherein an inductance L of the inductive network is based on a transconductance gm of the circuit and a capacitance C at the output node, and the inductive network increases a frequency of a non-dominant frequency response pole of an AC input signal of the circuit,

wherein the inductance L is according to L ═ kC/gm²Where k is a constant.

16. The circuit of claim 15, wherein the one or more transistors are connected in series with each other to form an amplifier.

17. The circuit of claim 15, wherein the inductive network comprises an inductor.

18. The circuit of claim 15, wherein the inductive network comprises an inductor connected at a first terminal to the at least one transistor and at a second terminal to a DC voltage.

19. The circuit of claim 15, wherein the inductive network comprises an inductor comprising a metal layer and a substrate.

20. The circuit of claim 15, wherein the inductive network comprises an inductor having a capacitance value between 100 and 350 picohenries.

Background

In an amplifier, there may be a non-dominant frequency pole whose frequency value is proportional to gm/C, where gm is the transconductance of the output stage and C is the total capacitance at the output node (e.g., C may include the capacitance of the load at the output node, the capacitance of the output node itself, and parasitic capacitances).

For high speed applications, the non-dominant pole needs to be pushed out to high frequencies. A low non-dominant pole frequency can lead to poor phase margin (under-damped behavior) and low bandwidth. To increase the frequency of the non-dominant pole, the amplifier may be designed to have an increased current at the output stage of the amplifier to increase the gm of the output stage. However, this results in increased power consumption. In addition, since gm/C is inherently limited by the fabrication process, the increased current is not sufficient to increase the frequency of the non-dominant pole of the output stage.

Therefore, there is a need for an amplifier with increased or improved non-dominant pole frequency and with improved bandwidth and settling time without increasing the current of the output stage.

Drawings

Fig. 1 shows a circuit according to an embodiment of the present disclosure.

Fig. 2 shows a cross-sectional view of a transistor in a circuit according to an embodiment of the present disclosure.

Fig. 3 shows a circuit according to an embodiment of the present disclosure.

Fig. 4 shows a cross-sectional view of a transistor in a circuit according to an embodiment of the present disclosure.

Fig. 5 shows a circuit according to an embodiment of the present disclosure.

Fig. 6 shows a circuit according to an embodiment of the present disclosure.

Detailed Description

According to the embodiment shown in fig. 1, circuit 100 may include a transistor 110, and an inductive network 120. The transistor 110 may output on an output node to drive a load 140. An inductive network 120 may be connected to the source node of transistor 110 to compensate for the capacitance of the output node.

In fig. 1, the circuit 100 may be an amplifier circuit. The transistor 110 may be a PMOS (P-type metal oxide silicon) transistor. The transistor 110 may have a gate connected to an input AC signal to be amplified. Driver 130 may be a current driver connected in series with transistor 110 between power supplies VDD and GND to produce an output node that drives load 140.

Alternatively, the transistor 110 may be a current drive transistor configured to bias a current through the amplifier circuit 100. In this case, the driver 130 may receive an input signal to be amplified.

In the above configuration, transistor 110 may be connected to VDD at its source pole, to the output node at its drain node, and to power supply VDD in series with inductive network 120. Transistor 110 may have its source node connected to inductive network 120 such that inductive network 120 compensates for capacitance associated with the output node and transistor 110.

By connecting inductive network 120 in series with transistor 110 at the source node of transistor 110, circuit 100 employs, for example, inductive network 120 in series with transistor 110. The inductance of inductive network 120 may effectively "turn off" the capacitance at the output node (e.g., including the load capacitance, parasitic capacitance of the output node of circuit 100) and push out the effective non-dominant pole effective frequency of circuit 100 or create a complex pole with better regulation performance. The optimal value of the inductive network 120 depends on the gm2 of the circuit 100 in the circuit branch (which may include the transistor 110 and other devices) and the total capacitance (C2) at the output node of the circuit 100. The inductance value of inductive-network 120 may be determined according to the following equation: l k C2/gm2²Where k is a constant. The inductor (L), capacitor (C2), and effective resistance (1/gm2) in circuit 100 may form a parallel (RLC) resonant circuit because each of the inductor (L), capacitor (C2), and effective resistance (1/gm2) is effectively connected in parallel in transistor 110. Thus, by using inductive network 120, the response of circuit 100 can be made faster and the non-dominant frequency response pole frequency of circuit 100 can be increased.

According to simulations, to achieve a similar response without using inductive network 120, the power requirement through circuit 100 increases by approximately 60%. In other words, inductive network 120 may reduce power consumption in circuit 100 by approximately 40% to achieve the same response time.

Fig. 2 shows an idealized cross-sectional view of transistor 110.

The transistor 110 may be a PMOS with a gate 202, the gate 202 having a gate oxide layer 204, a P-doped source region 206, a P-doped drain region 208, an N-doped potential well region 210, and a P-type substrate 212

Depending on the implementation in circuit 100, transistor 110 may have its P-doped source region 208 connected to inductive network 120. Various taps, such as diffusions or metal taps, may be implemented in the above-described portion of transistor 110 to connect to inductive network 120. In addition, inductive network 120 is implemented using metal strips formed on a substrate, the geometry and metal properties of the metal strips and substrate defining a particular desired inductance value. Inductive network 120 may include a handle-shaped inductor or a spiral-shaped inductor. The inductance value of inductive network 120 may be between 100 and 350 picohenries. Additional elements may be included in inductive network 120.

According to the embodiment shown in fig. 3, circuit 300 may include a transistor 310 and an inductive network 320. Transistor 310 may output on an output node to drive load 440. An inductive network 320 may be connected to the source node of transistor 310 to compensate for the capacitance of the output node.

In fig. 3, the circuit 300 may be an amplifier circuit. The transistor 310 may be an NMOS (N-type metal oxide silicon) transistor. The transistor 310 may have a gate connected to an input AC signal to be amplified. Driver 330 may be a current driver connected in series with transistor 310 between power supplies VDD and GND to produce an output node that drives load 340.

Alternatively, the transistor 310 may be a current-driven transistor configured to bias a current through the amplifier circuit 300. In this case, the driver 330 may receive an input signal to be amplified.

In the above configuration, transistor 310 may be connected to GND on its source node, to the output node on its drain node, and to power GND in series with inductive network 320. Transistor 110 may have its source node connected to inductive network 120 such that inductive network 120 compensates for the capacitance associated with the output node and transistor 110.

Fig. 4 shows an idealized cross-sectional view of transistor 310.

The transistor 310 may be an NMOS with a gate 402, the gate 502 having a gate oxide layer 404, an N-doped source region 406, an N-doped drain region 408, a P-doped potential well region 410, a deep N-doped potential well region 418, a P-type substrate 412.

According to an embodiment implemented in circuit 300, transistor 310 may have its N-doped source region 408 connected to an inductive network 320. Various taps, such as diffusions or metal taps, may be implemented in the above-described portion of transistor 310 to connect with inductive network 320. The inductive network 320 may be implemented using metal strips formed on a substrate, the geometry and metal properties of the metal strips and substrate defining the particular desired inductance value. The inductive network 320 may include a hand-held inductor or a spiral inductor. The inductance value of inductive network 320 may be between 100 and 350 picohenries. Additional elements may be included in inductive network 320.

Fig. 5 shows a circuit 500 according to an embodiment.

Circuit 500 may include a plurality of transistors 510.1-510.5 and a plurality of inductive networks 520.1-520.2 configured similarly to circuits 100 and 300 of fig. 1 and 3. The circuit 500 may be configured as a differential pair amplifier driving a differential output connected to a load 540. The circuit 500 may be configured as a differential pair amplifier, where each differential branch may be configured as a cascode amplifier.

Transistors 510.1-510.4 may be connected to the differential output node at their respective drain nodes, and transistor 510.5 may be a bias transistor. According to an embodiment, only transistors 510.1-510.2, which are directly connected to the output node at their drain or source nodes, need to be connected to the respective inductive networks 520.1-520.2. The inductive networks 520.1-520.2 may be implemented on the same circuit element or chip as the transistors 110.1-510.4 or on a separate circuit element or chip. Optionally, the circuit 500 may have an inductor connected between the transistor 510.5 and GND.

Transistors 510.1 and 510.2 may be PMOS transistors similar to transistor 110 shown in fig. 1 and 2, and transistors 510.3 and 510.4 may be NMOS transistors similar to transistor 310 in fig. 3 and 4.

Fig. 6 shows a circuit 600 according to an embodiment.

Circuit 600 may include a plurality of transistors 610.1-610.10 and a plurality of inductive networks 620.1-620.8 configured in a similar manner as circuits 100 and 300 of fig. 1 and 3. The circuit 600 may be configured as a two-stage differential pair amplifier driving a differential output connected to a load 640. Circuit 600 may be configured as a two-stage differential pair amplifier, where each differential branch may be configured as a cascode amplifier.

Transistors 610.1-610.8 may be connected with the differential output node at their respective drain nodes, and transistors 610.9 and 610.10 may be bias transistors. According to an embodiment, only transistors 610.1-2 and 610.5-610.6, which are directly connected to the output node at their drain or source nodes, need to be connected to the respective inductive networks 620.1-620.4. The inductive networks 620.1-620.4 may be implemented on the same circuit element or chip as transistors 610.1-610.8 or on a separate circuit element or chip. Alternatively, the circuit 600 may have an inductor connected between the transistor 610.9 and GND and an inductor between the transistor 610.10 and GND.

Transistors 610.1-610.2 and 610.5-610.6 may be PMOS transistors similar to transistor 110 of fig. 1 and 2, and transistors 610.3-610.4 and 610.7-610.8 may be NMOS transistors similar to transistor 310 in fig. 3 and 4.

It should be understood that the disclosure is not limited to the above-described embodiments, and that any number of embodiments and implementations in which conflicting designations exist may be resolved.

While the present disclosure has been described with reference to a number of exemplary embodiments, it is understood that the words which have been used are words of description and illustration, rather than words of limitation. Changes may be made, within the purview of the appended claims, as presently stated and as amended, without departing from the scope and spirit of the present disclosure in its aspects. Although the present disclosure has been described with reference to particular means, materials and embodiments, the present disclosure is not intended to be limited to the particulars disclosed; rather, the present disclosure extends to all functionally equivalent structures, methods and uses, such as are within the scope of the appended claims.

Although this application describes specific embodiments as code segments that can be implemented in a computer-readable medium, it should be appreciated that dedicated hardware implementations, such as application specific integrated circuits, programmable logic arrays and other hardware devices, can be constructed to implement one or more of the embodiments described herein. Applications that may include the embodiments set forth herein may broadly include a variety of electronic and computer systems. Accordingly, the present application may encompass software, firmware, and hardware implementations, or a combination thereof.

This specification describes components and functions that may be implemented in particular embodiments with reference to particular standards and protocols, to which the present disclosure is not limited. These standards are periodically replaced by faster or more efficient equivalent standards having substantially the same functionality. Accordingly, replacement standards and protocols having the same or similar functions are considered equivalents thereof.

The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. The illustrations are not intended to serve as a complete description of all of the elements and features of apparatus and systems that might make use of the structures or methods described herein. Many other embodiments will be apparent to those of skill in the art upon reviewing the present disclosure. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. Additionally, the illustrations are merely representational and may not be drawn to scale. Some proportions within the illustrations may be exaggerated, while other proportions may be minimized. The disclosure and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

One or more embodiments of the present disclosure may be referred to herein, individually and/or collectively, by the term "disclosure" merely for convenience and without intending to voluntarily limit the scope of this application to any particular disclosure or inventive concept. Moreover, although specific embodiments have been illustrated and described herein, it should be appreciated that any subsequent arrangement designed to achieve the same or similar purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described, will be apparent to those of skill in the art upon reviewing the description.

Moreover, in the foregoing detailed description, various features may be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter may be directed to less than all of the features of any of the disclosed embodiments. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as defining separately claimed claim subject matter.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.