阅读说明：本技术 一种快速锁定的延迟链锁相环 (quick-locking delay chain phase-locked loop ) 是由 朱樟明 张玮 马瑞 刘马良 王夏宇 胡进 于 2019-08-16 设计创作，主要内容包括：本发明公开了一种快速锁定的延迟链锁相环,包括压控延迟链、加速锁定控制模块、鉴相器、电荷泵以及环路滤波器；其中,所述压控延迟链连接时钟输入端；所述加速锁定控制模块连接所述压控延迟链；所述鉴相器连接所述压控延迟链的输出端和所述加速锁定控制模块的输出端；所述电荷泵连接所述鉴相器的输出端和所述加速锁定控制模块的输出端；所述环路滤波器连接所述电荷泵的输出端和所述压控延迟链的输入端。本发明提供的延迟链锁相环可以使系统快速、稳定、准确的进入锁定状态。(The invention discloses a fast-locking delay chain phase-locked loop, which comprises a voltage-controlled delay chain, an acceleration locking control module, a phase discriminator, a charge pump and a loop filter, wherein the voltage-controlled delay chain is connected with the phase discriminator; the voltage-controlled delay chain is connected with a clock input end; the acceleration locking control module is connected with the voltage-controlled delay chain; the phase discriminator is connected with the output end of the voltage-controlled delay chain and the output end of the acceleration locking control module; the charge pump is connected with the output end of the phase discriminator and the output end of the acceleration locking control module; the loop filter is connected with the output end of the charge pump and the input end of the voltage-controlled delay chain. The delay chain phase-locked loop provided by the invention can enable the system to quickly, stably and accurately enter a locking state.)

1. A fast locking delay chain phase locked loop, comprising:

The voltage-controlled delay chain is connected with the clock input end and is used for delaying the input signal and outputting a clock signal;

the locking acceleration control module is connected with the voltage-controlled delay chain and used for generating a control signal QCL according to the clock signal;

The phase discriminator is connected with the output end of the voltage-controlled delay chain and the output end of the accelerated locking control module and is used for controlling the on and off of the phase discriminator according to the control signal QCL and generating a phase difference signal;

the charge pump is connected with the output end of the phase discriminator and the output end of the acceleration locking control module and is used for controlling the charge pump to be switched on and off according to the control signal QCL and outputting a current signal;

and the loop filter is connected with the output end of the charge pump and the input end of the voltage-controlled delay chain and is used for receiving and processing the current signal and outputting a delay control signal VCTR to the voltage-controlled delay chain.

2. The delay chain phase locked loop of claim 1, wherein the clock signal comprises a first clock signal, a second clock signal, and a third clock signal.

3. the delay chain phase-locked loop of claim 2, wherein the accelerated lock control module comprises a logic unit, a delay unit, a signal acquisition unit, and a signal output unit; wherein the content of the first and second substances,

The logic unit is connected to the signal acquisition unit and is used for performing logic operation on the first clock signal and the second clock signal and outputting an operation result to the signal acquisition unit;

The delay unit is connected to the signal acquisition unit and used for delaying the third clock signal and outputting an operation result to the signal acquisition unit;

the signal acquisition unit is connected with the signal output unit.

4. the delay chain phase locked loop of claim 3, wherein the logic cell comprises a NAND circuit, a first NOT circuit, a first NOR circuit, a second NOR circuit, and a second NOT circuit; wherein the content of the first and second substances,

The input end of the NAND gate circuit is connected with the output end of the voltage-controlled delay chain and is used for receiving the first clock signal and the second clock signal, and the output end of the NAND gate circuit is connected with the input end of the first NOT gate circuit;

the input end of the first NOR gate circuit is connected with the output end of the voltage-controlled delay chain and is used for receiving the first clock signal and the second clock signal;

The input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit and the output end of the first NOR gate circuit, and the output end of the second NOR gate circuit is connected with the input end of the second NOR gate circuit;

And the output end of the second NOT gate circuit is connected with the signal acquisition unit.

5. The delay chain phase-locked loop of claim 4, wherein the delay unit comprises a third NOT gate circuit, a fourth NOT gate circuit, a fifth NOT gate circuit and a sixth NOT gate circuit connected in series in sequence, an input terminal of the third NOT gate circuit is connected to an output terminal of the voltage-controlled delay chain for receiving the third clock signal, and an output terminal of the sixth NOT gate circuit is connected to the signal acquisition unit.

6. The delay chain phase-locked loop of claim 5, wherein the signal acquisition unit comprises a first D flip-flop and an inverter, and a data input terminal of the first D flip-flop is connected to an output terminal of the second NOT gate circuit; the clock input end of the first D flip-flop is connected with the output end of the sixth NOT gate circuit; the reset end of the first D trigger is connected with a reset signal end; and the output Q end of the first D trigger is connected with the signal output unit through an inverter.

7. The delay chain phase-locked loop of claim 3, wherein the signal output unit comprises a second D flip-flop, a data input terminal of the second D flip-flop is connected to a VDD voltage terminal, a clock input terminal of the second D flip-flop is connected to the output terminal of the signal acquisition unit, and an output Q terminal of the second D flip-flop is used as the output terminal of the accelerated lock control module to output the control signal QCL.

Technical Field

The invention belongs to the technical field of laser radar optical signal receiver systems, and particularly relates to a fast-locking delay chain phase-locked loop.

background

the laser radar is a radar system that detects a characteristic amount such as a position and a velocity of a target by emitting a laser beam. With the development of technology, the application range of laser radar is becoming wider and wider, such as navigation and collision avoidance of automobiles or spacecrafts, three-dimensional space profile scanning, weather detection, geological detection, and the like. The laser radar utilizes a laser transmitter to emit laser to irradiate on a detected object, laser echo reflected by a target object is received by an avalanche photodiode working in a linear mode and converted into a current signal, a front-end analog receiver linearly converts pulse current generated by the avalanche photodiode into a voltage signal, a time-to-digital conversion circuit is utilized to obtain flight time information of the pulse, or an analog-to-digital converter acquires amplitude of echo pulse, and finally the amplitude is provided for a subsequent digital signal processor to be further processed. In the time-to-digital conversion circuit, the delay chain phase-locked loop has wide application prospect.

In the time-to-digital conversion circuit, the delay chain phase-locked loop has wide application prospect. While placing higher demands on the speed and stability of its locking. Referring to fig. 1, fig. 1 is a schematic diagram of a conventional delay chain phase-locked loop structure; the conventional delay chain phase-locked loop has a slow locking speed, and the delay time of the delay chain is completely determined by the voltage-controlled voltage, but the delay time is very sensitive to the change of the voltage-controlled voltage, i.e., the change of the voltage-controlled voltage is very small, which causes the delay time to be greatly increased or reduced, so that the conventional delay chain phase-locked loop is easy to enter a wrong locking state due to the change of the control voltage.

disclosure of Invention

to solve the above problems in the prior art, the present invention provides a fast locking delay chain phase locked loop. The technical problem to be solved by the invention is realized by the following technical scheme:

A fast locking delay chain phase locked loop comprising:

the voltage-controlled delay chain is connected with the clock input end and is used for delaying the input signal and outputting a clock signal;

The locking acceleration control module is connected with the voltage-controlled delay chain and used for generating a control signal QCL according to the clock signal;

The phase discriminator is connected with the output end of the voltage-controlled delay chain and the output end of the accelerated locking control module and is used for controlling the on and off of the phase discriminator according to the control signal QCL and generating a phase difference signal;

The charge pump is connected with the output end of the phase discriminator and the output end of the acceleration locking control module and is used for controlling the charge pump to be switched on and off according to the control signal QCL and outputting a current signal;

And the loop filter is connected with the output end of the charge pump and the input end of the voltage-controlled delay chain and is used for receiving and processing the current signal and outputting a delay control signal VCTR to the voltage-controlled delay chain.

In one embodiment of the present invention, the clock signals include a first clock signal, a second clock signal, and a third clock signal.

In one embodiment of the present invention, the acceleration locking control module includes a logic unit, a delay unit, a signal acquisition unit and a signal output unit; wherein the content of the first and second substances,

the logic unit is connected to the signal acquisition unit and is used for performing logic operation on the first clock signal and the second clock signal and outputting an operation result to the signal acquisition unit;

The delay unit is connected to the signal acquisition unit and used for delaying the third clock signal and outputting an operation result to the signal acquisition unit;

the signal acquisition unit is connected with the signal output unit.

In one embodiment of the invention, the logic unit comprises a NAND gate circuit, a first NOT gate circuit, a second NOT gate circuit and a second NOT gate circuit; wherein the content of the first and second substances,

the input end of the NAND gate circuit is connected with the output end of the voltage-controlled delay chain and is used for receiving the first clock signal and the second clock signal, and the output end of the NAND gate circuit is connected with the input end of the first NOT gate circuit;

the input end of the first NOR gate circuit is connected with the output end of the voltage-controlled delay chain and is used for receiving the first clock signal and the second clock signal;

the input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit and the output end of the first NOR gate circuit, and the output end of the second NOR gate circuit is connected with the input end of the second NOR gate circuit;

And the output end of the second NOT gate circuit is connected with the signal acquisition unit.

in an embodiment of the present invention, the delay unit includes a third not gate circuit, a fourth not gate circuit, a fifth not gate circuit, and a sixth not gate circuit, which are sequentially connected in series, an input terminal of the third not gate circuit is connected to an output terminal of the voltage-controlled delay chain and is configured to receive the third clock signal, and an output terminal of the sixth not gate circuit is connected to the signal acquisition unit.

In one embodiment of the present invention, the signal acquisition unit includes a first D flip-flop and an inverter, and a data input terminal of the first D flip-flop is connected to an output terminal of the second not gate circuit; the clock input end of the first D flip-flop is connected with the output end of the sixth NOT gate circuit; the reset end of the first D trigger is connected with a reset signal end; and the output Q end of the first D trigger is connected with the signal output unit through an inverter.

In an embodiment of the present invention, the signal output unit includes a second D flip-flop, a data input end of the second D flip-flop is connected to the VDD voltage terminal, a clock input end of the second D flip-flop is connected to the output end of the signal acquisition unit, and an output Q terminal of the second D flip-flop is used as the output end of the accelerated lock control module to output the control signal QCL.

the invention has the beneficial effects that:

1. The invention adopts the acceleration locking control module, greatly shortens the time for the system to enter the locking state and improves the locking speed of the system;

2. the control signal of the acceleration locking control module is completely generated from the interior of the phase-locked loop, thereby avoiding the uncertainty of external control, increasing the locking stability and avoiding the system from entering into a wrong locking state;

3. the invention adopts the improved phase discriminator and the charge pump, can controllably shut off part of functions when accelerating the locking state, reduces dynamic power consumption, avoids unnecessary charging and discharging of a loop filter capacitor, avoids logic competition risk caused by control signal jumping, and ensures that the system stably enters the locking state.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

drawings

FIG. 1 is a schematic diagram of a conventional delay chain phase-locked loop structure provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a fast-locking delay chain phase-locked loop according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of different stable points of a phase-locked loop of a delay chain according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a topology of a fast lock control module according to an embodiment of the present invention;

FIG. 5 is a timing diagram of input and output signals of the fast lock control module according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an improved structure of a phase detector and a charge pump according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.