阅读说明：本技术 电源电压生成部以及包括其的显示装置 (Power supply voltage generating unit and display device including the same ) 是由 南亮旭 南亨来 于 2021-04-01 设计创作，主要内容包括：提供一种电源电压生成部以及包括其的显示装置。显示装置包括显示部、栅极驱动部、数据驱动部以及电源电压生成部。所述显示部显示图像。所述栅极驱动部向所述显示部提供栅极信号。所述数据驱动部向所述显示部提供数据电压。所述电源电压生成部向所述显示部、所述栅极驱动部以及所述数据驱动部中的至少一个输出电源电压。所述电源电压生成部包括：电荷泵,生成具有自动设定的净空余量且根据目标电压可变的电荷泵电压；以及调节器,基于所述电荷泵电压生成所述电源电压。(Provided are a power supply voltage generation unit and a display device including the same. The display device includes a display section, a gate driving section, a data driving section, and a power supply voltage generating section. The display unit displays an image. The gate driving part supplies a gate signal to the display part. The data driving part supplies a data voltage to the display part. The power supply voltage generating unit outputs a power supply voltage to at least one of the display unit, the gate driving unit, and the data driving unit. The power supply voltage generation unit includes: a charge pump generating a charge pump voltage having a headroom margin automatically set and variable according to a target voltage; and a regulator that generates the power supply voltage based on the charge pump voltage.)

1. A power supply voltage generating section comprising:

a charge pump generating a charge pump voltage having a headroom margin automatically set and variable according to a target voltage; and

a regulator to generate a supply voltage based on the charge pump voltage.

2. The power supply voltage generation section according to claim 1,

if the absolute value of the target voltage increases, the absolute value of the charge pump voltage increases.

3. The power supply voltage generation section according to claim 1,

the headroom is variable depending on the output load.

4. The power supply voltage generation section according to claim 3,

if the output load increases, the absolute value of the headroom increases,

if the output load increases, the absolute value of the charge pump voltage increases.

5. The power supply voltage generation section according to claim 1,

the charge pump includes:

an operator generating a reference charge pump voltage variable according to the target voltage;

a comparator that compares a feedback voltage of the charge pump voltage with the reference charge pump voltage;

a flip-flop outputting a control signal based on a clock signal and an output signal of the comparator; and

and the switch controller generates a switch control signal based on the output signal of the trigger.

6. The power supply voltage generation section according to claim 5,

the charge pump further comprises:

a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier that receive the switch control signal;

a first switch connected to the first amplifier;

a second switch connected to the second amplifier;

a third switch connected to the third amplifier; and

a fourth switch connected to the fourth amplifier,

the first switch, the fourth switch, the second switch, and the third switch are sequentially connected in series.

7. The power supply voltage generation section according to claim 6,

the charge pump further comprises:

a first capacitor including a first electrode connected to the first switch and the fourth switch and a second electrode connected to the second switch and the third switch; and

a second capacitor including a first electrode connected to the third switch and a second electrode connected to ground.

8. The power supply voltage generation section according to claim 6,

the charge pump further comprises: a level shifter configured between the switch controller and the first to fourth amplifiers.

9. The power supply voltage generation section according to claim 6,

if the absolute value of the feedback voltage is less than the reference charge pump voltage, the output of the comparator has a first level,

the output of the comparator has a second level if the absolute value of the feedback voltage is greater than or equal to the reference charge pump voltage.

10. A display device, comprising:

a display unit that displays an image;

a gate driving part supplying a gate signal to the display part;

a data driving part supplying a data voltage to the display part; and

a power supply voltage generating unit that outputs a power supply voltage to at least one of the display unit, the gate driving unit, and the data driving unit,

the power supply voltage generation unit includes:

a charge pump generating a charge pump voltage having a headroom margin automatically set and variable according to a target voltage; and

a regulator to generate the supply voltage based on the charge pump voltage.

Technical Field

The present invention relates to a power supply voltage generating unit, a display device including the same, and a power supply voltage generating method using the same, and more particularly, to a power supply voltage generating unit that generates a charge pump voltage that has a headroom (head room margin) automatically set and is variable according to a target voltage, a display device including the same, and a power supply voltage generating method using the same.

Background

Generally, a display device includes a display panel and a display panel driving section. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of light emitting lines, and a plurality of pixels. The display panel driving part includes a gate driving part supplying a gate signal to the plurality of gate lines, a data driving part supplying a data voltage to the plurality of data lines, a light emission driving part supplying a light emission signal to the plurality of light emission lines, a power voltage generating part generating a power voltage, and a driving control part controlling the gate driving part, the data driving part, and the light emission driving part.

The power supply voltage generating section may include a charge pump circuit that generates a charge pump voltage for generating the power supply voltage. The charge pump circuit generates several fixed charge pump voltages, and thus there is a problem in that headroom is not optimized and power consumption is large.

Disclosure of Invention

The invention provides a power supply voltage generating part for generating a charge pump voltage which has a clearance margin automatically set and is variable according to a target voltage to reduce power consumption of a display device.

Another object of the present invention is to provide a display device including the power supply voltage generating unit.

Another object of the present invention is to provide a power supply voltage generating method using the power supply voltage generating unit.

The power supply voltage generating unit according to an embodiment of the present invention includes a charge pump and a regulator. The charge pump generates a charge pump voltage having an automatically set headroom and variable according to a target voltage. The regulator generates a supply voltage based on the charge pump voltage.

In an embodiment of the present invention, if the absolute value of the target voltage increases, the absolute value of the charge pump voltage may increase.

In an embodiment of the present invention, the headroom may be variable according to the output load.

In an embodiment of the present invention, if the output load increases, the absolute value of the headroom may increase. The absolute value of the charge pump voltage may be increased if the output load is increased.

In an embodiment of the present invention, the charge pump may include: an operator generating a reference charge pump voltage variable according to the target voltage; a comparator that compares a feedback voltage of the charge pump voltage with the reference charge pump voltage; a flip-flop outputting a control signal based on a clock signal and an output signal of the comparator; and a switch controller generating a switch control signal based on an output signal of the flip-flop.

In an embodiment of the present invention, the charge pump further includes: a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier that receive the switch control signal; a first switch connected to the first amplifier; a second switch connected to the second amplifier; a third switch connected to the third amplifier; and a fourth switch connected to the fourth amplifier. The first switch, the fourth switch, the second switch, and the third switch may be sequentially connected in series.

In an embodiment of the present invention, the charge pump further includes: a first capacitor including a first electrode connected to the first switch and the fourth switch and a second electrode connected to the second switch and the third switch; and a second capacitor including a first electrode connected to the third switch and a second electrode connected to ground.

In an embodiment of the present invention, when the switch control signal has a first level, the first switch and the second switch may be turned on, and the third switch and the fourth switch may be turned off. The third switch and the fourth switch may be turned on and the first switch and the second switch may be turned off when the switch control signal has a second level.

In an embodiment of the present invention, the first capacitor may be charged when the switch control signal has the first level. The voltage charged to the first capacitor may be output to the regulator through the third switch when the switch control signal has the second level.

In an embodiment of the present invention, the charge pump further includes: a level shifter configured between the switch controller and the first to fourth amplifiers.

In an embodiment of the present invention, if the absolute value of the feedback voltage is smaller than the reference charge pump voltage, the output of the comparator has a first level, and if the absolute value of the feedback voltage is greater than or equal to the reference charge pump voltage, the output of the comparator has a second level.

In an embodiment of the present invention, the regulator may include: a fifth amplifier; and a fifth switch connected to an output node of the fifth amplifier. A control node of the fifth switch may be connected to the output node of the fifth amplifier, the charge pump voltage may be applied to an input node of the fifth switch, and the output node of the fifth switch may output the power supply voltage.

In an embodiment of the present invention, the regulator further includes: a first resistor including a first terminal connected to the output node of the fifth switch and a second terminal connected to a first input node of the fifth amplifier; a second resistor including a first end connected to the second end of the first resistor and a second end connected to ground; and a stabilization capacitor including a first electrode connected to the output node of the fifth switch and a second electrode connected to the ground.

A display device according to an embodiment for achieving the other object of the present invention includes a display unit, a gate driving unit, a data driving unit, and a power supply voltage generating unit. The display unit displays an image. The gate driving part supplies a gate signal to the display part. The data driving part supplies a data voltage to the display part. The power supply voltage generating unit outputs a power supply voltage to at least one of the display unit, the gate driving unit, and the data driving unit. The power supply voltage generation unit includes: a charge pump generating a charge pump voltage having a headroom margin automatically set and variable according to a target voltage; and a regulator that generates the power supply voltage based on the charge pump voltage.

In an embodiment of the present invention, the power supply voltage may be an initialization voltage output to a pixel of the display portion.

In an embodiment of the present invention, the power supply voltage may be a gate low voltage which is output to the gate driving part and defines a low level of the gate signal.

In an embodiment of the present invention, the power supply voltage generating unit may further include: a second charge pump generating a second charge pump voltage having a second headroom automatically set and variable according to a second target voltage; and a second regulator generating a second supply voltage based on the second charge pump voltage.

In an embodiment of the present invention, the power supply voltage may be an initialization voltage output to a pixel of the display portion. The second power supply voltage may be a gate low voltage that is output to the gate driving part and defines a low level of the gate signal.

In an embodiment of the present invention, the headroom may be variable according to the output load.

An embodiment of the present invention for achieving the other objects of the present invention relates to a power supply voltage generation method including: generating a charge pump voltage having a headroom automatically set and variable according to a target voltage; and generating a power supply voltage based on the charge pump voltage. The headroom may be variable depending on the output load.

(effect of the invention)

According to the power supply voltage generating section, the display device including the same, and the power supply voltage generating method using the same as described above, the charge pump generates the charge pump voltage having the headroom automatically set and variable according to the target voltage, and therefore the headroom of the charge pump voltage can be optimized. Therefore, power consumption of the display device can be reduced.

In addition, the power supply voltage generating section may adjust a headroom of the charge pump voltage according to a size of an output load, and thus the headroom of the charge pump voltage may be further optimized. Therefore, the power consumption of the display device can be further reduced.

Drawings

Fig. 1 is a block diagram showing a display device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing a pixel of the display panel of fig. 1.

Fig. 3 is a timing chart showing input signals applied to the pixel of fig. 2.

Fig. 4 is a block diagram showing the power supply voltage generating unit of fig. 1.

Fig. 5 is a circuit diagram showing the first charge pump of fig. 4.

Fig. 6 is a timing diagram showing input signals, node signals, and output signals of the first charge pump of fig. 5.

Fig. 7 is a timing diagram showing input signals and output signals of the flip-flop of fig. 5 and output signals of the first charge pump of fig. 5.

Fig. 8 is a table showing registers used for setting the arithmetic unit of fig. 5.

Fig. 9 is a circuit diagram showing the first regulator of fig. 4.

Fig. 10 is a table showing power consumption of the comparative example and power consumption of the present example.

Fig. 11 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the target voltage.

Fig. 12 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the output load.

Description of the symbols:

100: a display panel; 200: a drive control unit; 300: a gate driving section; 400: a gamma reference voltage generating section; 500: a data driving section; 600: a light emission driving section; 700: a power supply voltage generating unit; 710: a first charge pump; 711: an arithmetic unit; 712: a switch controller; 713: a level shifter; 720: a first regulator; 730: a second charge pump; 740: a second regulator.

Detailed Description

The present invention will be described in more detail below with reference to the accompanying drawings.

Fig. 1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to fig. 1, the display device includes a display panel 100 and a display panel driving part. The display panel driving part includes a driving control part 200, a gate driving part 300, a gamma reference voltage generating part 400, a data driving part 500, and a light emission driving part 600. The display panel driving part further includes a power voltage generating part 700.

The display panel 100 includes a display portion for displaying an image and a peripheral portion disposed adjacent to the display portion.

The display panel 100 includes a plurality of gate lines GWL, GIL, GBL, a plurality of data lines DL, a plurality of light emitting lines EL, and a plurality of pixels electrically connected to the gate lines GWL, GIL, GBL, the data lines DL, and the light emitting lines EL, respectively. The gate lines GWL, GIL, GBL extend in a first direction D1, the data line DL extends in a second direction D2 crossing the first direction D1, and the light emitting line EL extends in the first direction D1.

The drive control section 200 receives input image data IMG and an input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may comprise white image data. The input image data IMG may include magenta (magenta) image data, yellow (yellow) image data, and cyan (cyan) image data. The input control signals CONT may include a master clock signal and a data strobe signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The driving control part 200 may generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a DATA signal DATA based on the input image DATA IMG and the input control signal CONT.

The driving control part 200 generates the first control signal CONT1 for controlling the operation of the gate driving part 300 based on the input control signal CONT and outputs it to the gate driving part 300. The first control signals CONT1 may include a vertical start signal and a gate clock signal.

The driving control part 200 generates the second control signal CONT2 for controlling the operation of the data driving part 500 based on the input control signal CONT and outputs it to the data driving part 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

The driving control part 200 generates a DATA signal DATA based on the input image DATA IMG. The driving control part 200 outputs the DATA signal DATA to the DATA driving part 500.

The driving control part 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generating part 400 based on the input control signal CONT and outputs it to the gamma reference voltage generating part 400.

The driving control section 200 generates the fourth control signal CONT4 for controlling the operation of the light emission driving section 600 based on the input control signal CONT and outputs it to the light emission driving section 600.

The gate driving unit 300 generates gate signals for driving the gate lines GWL, GIL, and GBL in response to the first control signal CONT1 input from the driving control unit 200. The gate driving unit 300 may output the gate signal to the gate lines GWL, GIL, and GBL. For example, the gate driving part 300 may be integrated at a peripheral portion of the display panel 100. For example, the gate driving part 300 may be mounted on a peripheral portion of the display panel 100.

The gamma reference voltage generating part 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 input from the driving control part 200. The gamma reference voltage generating part 400 supplies the gamma reference voltage VGREF to the data driving part 500. The gamma reference voltages VGREF have values corresponding to the respective DATA signals DATA.

For example, the gamma reference voltage generating part 400 may be disposed within the driving control part 200 or may be disposed within the data driving part 500.

The DATA driving part 500 receives the second control signal CONT2 and the input of the DATA signal DATA from the driving control part 200, and receives the input of the gamma reference voltage VGREF from the gamma reference voltage generating part 400. The DATA driving part 500 converts the DATA signal DATA into a DATA voltage of an analog form using the gamma reference voltage VGREF. The data driving part 500 outputs the data voltage to the data line DL.

The light emission driving part 600 generates a light emission signal for driving the light emission line EL in response to the fourth control signal CONT4 input from the driving control part 200. The light emission driving part 600 may output the light emission signal to the light emission line EL. For example, the light emission driving part 600 may be integrated at a peripheral portion of the display panel 100. For example, the light emission driving part 600 may be mounted on a peripheral portion of the display panel 100. In fig. 1, the case where the gate driving part 300 is disposed on a first side of the display panel 100 and the light emission driving part 600 is disposed on a second side opposite to the first side of the display panel 100 is illustrated, but the present invention is not limited thereto. The gate driving part 300 and the light emission driving part 600 may be disposed on the same side with respect to the display panel 100. For example, the gate driving part 300 and the light emission driving part 600 may be integrated in a peripheral portion that is the same side with respect to the display part of the display panel 100.

The power supply voltage generating part 700 may supply a power supply voltage to at least one of the display panel 100, the driving control part 200, the gate driving part 300, the gamma reference voltage generating part 400, the data driving part 500, and the light emission driving part 600.

For example, the power supply voltage generating part 700 may output an initialization voltage VINT to the pixels of the display panel 100. For example, the power supply voltage generating part 700 may output a high power supply voltage ELVDD and a low power supply voltage ELVSS to the pixels of the display panel 100. In this embodiment, the display device may be an organic light emitting display device including an organic light emitting element. However, the present invention is not limited to the organic light emitting display device.

For example, the power supply voltage generating part 700 may generate a gate high voltage VGH and a gate low voltage VGL used to generate the gate signal and output them to the gate driving part 300.

For example, the power supply voltage generating part 700 may generate an analog high voltage determining the level of the data voltage and output the analog high voltage to the data driving part 500.

Fig. 2 is a circuit diagram showing a pixel of the display panel 100 of fig. 1. Fig. 3 is a timing chart showing input signals applied to the pixel of fig. 2.

Referring to fig. 1 to 3, the display panel 100 includes a plurality of pixels each including an organic light emitting element OLED.

The pixel inputs a data writing gate signal GW, a data initializing gate signal GI, an organic light emitting element initializing gate signal GB, a data voltage VDATA, and the light emitting signal EM, and causes the organic light emitting element OLED to emit light according to the level of the data voltage VDATA, thereby displaying the image.

At least one pixel among the plurality of pixels may include first to seventh thin film transistors T1 to T7, a storage capacitor CST, and the organic light emitting element OLED.

The first thin film transistor T1 includes a control electrode connected to the first pixel node N1, an input electrode connected to the second pixel node N2, and an output electrode connected to the third pixel node N3.

For example, the first thin film transistor T1 may be a P-type thin film transistor. The control electrode of the first thin film transistor T1 may be a gate electrode, the input electrode of the first thin film transistor T1 may be a source electrode, and the output electrode of the first thin film transistor T1 may be a drain electrode.

The second thin film transistor T2 includes a control electrode to which the data write gate signal GW is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second pixel node N2.

The third thin film transistor T3 includes a control electrode to which the data write gate signal GW is applied, an input electrode connected to the first pixel node N1, and an output electrode connected to the third pixel node N3.

The fourth thin film transistor T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the first pixel node N1.

The fifth thin film transistor T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which a high power supply voltage ELVDD is applied, and an output electrode connected to the second pixel node N2.

The sixth thin film transistor T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third pixel node N3, and an output electrode connected to an anode of the organic light emitting element OLED.

The seventh thin film transistor T7 includes a control electrode to which the organic light emitting element initializing gate signal GB is applied, an input electrode to which the initializing voltage VINT is applied, and an output electrode connected to the anode of the organic light emitting element OLED.

For example, the first to seventh thin film transistors T1 to T7 may be P-type thin film transistors. The control electrodes of the first to seventh thin film transistors T1 to T7 may be gate electrodes, the input electrodes of the first to seventh thin film transistors T1 to T7 may be source electrodes, and the output electrodes of the first to seventh thin film transistors T1 to T7 may be drain electrodes.

In contrast, the first to seventh thin film transistors T1 to T7 may be N-type thin film transistors.

The storage capacitor CST includes a first electrode to which the high power supply voltage ELVDD is applied and a second electrode connected to the first pixel node N1.

The organic light emitting element OLED includes the anode and a cathode to which a low power supply voltage ELVSS is applied.

Referring to fig. 3, in a first interval DU1, the first pixel node N1 and the storage capacitor CST are initialized by the data initialization gate signal GI. In the second interval DU2, the data voltage VDATA compensated for the threshold voltage | VTH | is written to the first pixel node N1 by the data write gate signal GW compensating for the threshold voltage | VTH | of the first thin film transistor T1. In the third interval DU3, the anode of the organic light emitting element OLED is initialized by the organic light emitting element initialization gate signal GB. In the fourth interval DU4, the organic light emitting element OLED emits light by the light emission signal EM, and the display panel 100 displays an image. That is, the emission signal EM [ N ] may be high level in the first interval DU1 to the third interval DU 3.

In the first interval DU1, the data initialization gate signal GI may have an active level. For example, the active level of the data initialization gate signal GI may be a low level. When the data initialization gate signal GI has the active level, the fourth thin film transistor T4 is turned on, and the initialization voltage VINT may be applied to the first pixel node N1. The data initialization gate signal GI [ N ] of the current driving stage may be a SCAN signal SCAN [ N-1] of the previous driving stage.

In the second interval DU2, the data write gate signal GW may have an active level. For example, the active level of the data write gate signal GW may be a low level. When the data write gate signal GW has the active level, the second thin film transistor T2 and the third thin film transistor T3 are turned on. In addition, the first thin film transistor T1 is also turned on by the initialization voltage VINT. The data write gate signal GW [ N ] of the current driving stage may be a SCAN signal SCAN [ N ] of the current driving stage.

A voltage, which is subtracted from the data voltage VDATA by the threshold voltage | VTH | of the first thin film transistor T1, is set at the first pixel node N1 along a path formed by the first thin film transistor T1 to the third thin film transistor T3 being turned on.

In the third interval DU3, the organic light emitting element initialization gate signal GB may have an active level. For example, the active level of the organic light emitting element initialization gate signal GB may be a low level. When the organic light emitting element initializing gate signal GB has the active level, the seventh thin film transistor T7 is turned on, and the initializing voltage VINT may be applied to the anode of the organic light emitting element OLED. The organic light emitting element initializing gate signal GB [ N ] of the current driving stage may be a SCAN signal SCAN [ N +1] of the next driving stage.

In this embodiment, the case where the effective interval of the organic light emitting element initialization gate signal GB is different from the effective interval of the data write gate signal GW is exemplified, but the effective interval of the organic light emitting element initialization gate signal GB may coincide with the effective interval of the data write gate signal GW. For example, the organic light emitting element initializing gate signal GB [ N ] of the current driving stage may be the SCAN signal SCAN [ N ] of the current driving stage. In this case, the control electrode of the seventh thin film transistor T7 may be connected to the control electrode of the second thin film transistor T2.

In the fourth interval DU4, the emission signal EM may have an active level. For example, the active level of the emission signal EM may be a low level. When the emission signal EM has the active level, the fifth and sixth thin film transistors T5 and T6 are turned on. In addition, the first thin film transistor T1 is also turned on by the data voltage VDATA.

A driving current may sequentially flow through the fifth thin film transistor T5, the first thin film transistor T1, and the sixth thin film transistor T6, thereby driving the organic light emitting element OLED. The magnitude of the driving current may be determined according to the level of the data voltage VDATA. The luminance of the organic light emitting element OLED may be determined according to the intensity of the driving current.

Fig. 4 is a block diagram illustrating the power supply voltage generating unit 700 of fig. 1.

According to fig. 1 to 4, the power supply voltage generating part 700 may include: a first charge pump 710 generating a first charge pump voltage VCP1 having a first headroom automatically set and variable according to a first target voltage; and a first regulator 720 that generates a first supply voltage (e.g., VINT) based on the first charge pump voltage VCP 1.

The first charge pump 710 may generate the first charge pump voltage VCP1 based on a charge pump supply voltage PAVDD.

For example, the first power supply voltage VINT may be the initialization voltage VINT output to the pixels of the display panel 100. The initialization voltage VINT may be applied to an input electrode of the fourth thin film transistor T4 of fig. 2.

In this embodiment, if the absolute value of the first target voltage (target value of VINT) increases, the absolute value of the first charge pump voltage VCP1 may increase. For example, if the first headroom is 0.3V and the first target voltage is-3.5V, the first charge pump voltage VCP1 may be set to-3.8V, which is 0.3V subtracted from-3.5V. For example, if the first headroom is 0.3V and the first target voltage is-3.7V, the first charge pump voltage VCP1 may be set to-4.0V, which is 0.3V subtracted from-3.7V.

In addition, the first headroom may be variable according to an output load of the first power supply voltage VINT. If the output load of the first power supply voltage VINT increases, the absolute value of the first headroom may increase. For example, if the first headroom relative to the first output load is 0.3V and the first target voltage is-3.5V, the first charge pump voltage VCP1 may be set to-3.8V, which is 0.3V subtracted from-3.5V. For example, in the case where the output load is a second output load larger than the first output load, the first headroom may be set to 0.4V instead of 0.3V. Therefore, if the first headroom relative to the second output load is 0.4V and the first target voltage is-3.5V, the first charge pump voltage VCP1 may be set to-3.9V, which is 0.4V subtracted from-3.5V. As described above, if the output load increases, the absolute value of the first charge pump voltage VCP1 increases.

The power supply voltage generating part 700 may further include: a second charge pump 730 generating a second charge pump voltage VCP2 having a second headroom automatically set and variable according to a second target voltage; and a second regulator 740 generating a second power supply voltage (e.g., VGL) based on the second charge pump voltage VCP 2.

The second charge pump 730 may generate the second charge pump voltage VCP2 based on the charge pump supply voltage PAVDD.

As described above, if the absolute value of the second target voltage (the target value of VGL) increases, the absolute value of the second charge pump voltage VCP2 increases. For example, if the second headroom is 0.3V and the second target voltage is-8.8V, the second charge pump voltage VCP2 may be set to-9.1V, which is 0.3V subtracted from-8.8V. For example, if the second headroom is 0.3V and the second target voltage is-9.0V, the second charge pump voltage VCP2 may be set to-9.3V, which is 0.3V subtracted from-9.0V.

In addition, the second headroom may be variable according to an output load of the second power supply voltage VGL. If the output load of the second power voltage VGL increases, the absolute value of the second headroom is increased.

In fig. 5 to 8, the structure and operation of the first charge pump 710 are explained in detail. In fig. 5 to 8, the first charge pump 710 is illustrated, and the second charge pump 730 may have the same structure as the first charge pump 710 and may operate in the same manner.

In fig. 9, the structure and operation of the first regulator 720 are explained in detail. In fig. 9, the first regulator 720 is illustrated, and the second regulator 740 may have the same structure and may operate in the same manner as the first regulator 720.

Fig. 5 is a circuit diagram illustrating the first charge pump 710 of fig. 4. Fig. 6 is a timing diagram illustrating input signals, node signals, and output signals of the first charge pump 710 of fig. 5. Fig. 7 is a timing diagram showing input signals and output signals of the flip-flop FF of fig. 5 and output signals of the first charge pump 710 of fig. 5.

Referring to fig. 1 to 7, the first charge pump 710 may include: an operator 711 that generates a reference charge pump voltage variable according to the target voltage; a comparator A5 that compares a feedback voltage of the first charge pump voltage VCP1 with the reference charge pump voltage; a flip-flop FF outputting a control signal based on a clock signal CLK and an output signal of the comparator a 5; and a switch controller 712 generating a switch control signal SWS based on an output signal of the flip-flop FF.

The feedback voltage of the first charge pump voltage VCP1 may be input to the comparator a5 through a feedback resistor string FRS connected to an output node of the first charge pump voltage VCP 1.

The output of the comparator a5 (D of fig. 7) may have a first level if the absolute value of the feedback voltage is less than the reference charge pump voltage. Conversely, if the absolute value of the feedback voltage is greater than or equal to the reference charge pump voltage, the output of the comparator a5 (D of fig. 7) may have a second level. Here, the first level may be a high level, and the second level may be a low level.

The first charge pump 710 may further include: a first amplifier a1, a second amplifier a2, a third amplifier A3, and a fourth amplifier a4 that receive the switch control signal SWS; a first switch S1 connected to the first amplifier a 1; a second switch S2 connected to the second amplifier a 2; a third switch S3 connected to the third amplifier A3; and a fourth switch S4 connected to the fourth amplifier a 4.

The output signals of the first amplifier a1 and the second amplifier a2 may be inverted.

The first switch S1, the fourth switch S4, the second switch S2, and the third switch S3 may be sequentially connected in series.

The first charge pump 710 may further include: a first capacitor C1 including a first electrode connected to the first switch S1 and the fourth switch S4 (i.e., node SWN of fig. 5) and a second electrode connected to the second switch S2 and the third switch S3 (i.e., node CPN of fig. 5); and a second capacitor C2 including a first electrode connected to the third switch S3 and a second electrode connected to ground. The first capacitor C1 may be a charging capacitor and the second capacitor C2 may be a stabilizing capacitor for the charge pump voltage.

The first switch S1 and the second switch S2 may be turned on and the third switch S3 and the fourth switch S4 may be turned off when the switch control signal SWS has a first level SWSH, the third switch S3 and the fourth switch S4 may be turned on and the first switch S1 and the second switch S2 may be turned off when the switch control signal SWS has a second level SWSL. Here, the first level SWSH may be a high level, and the second level SWSL may be a low level.

When the switch control signal SWS has the first level SWSH, the first capacitor C1 is charged. When the switch control signal SWS has the second level SWSL, the voltage charged to the first capacitor C1 may be output to the first regulator 720 through the third switch S3. In fig. 5, the flow of current when the switch control signal SWS has the first level SWSH and the flow of current when the switch control signal SWS has the second level SWSL are shown by dotted lines.

Referring to fig. 6, when the switch control signal SWS has the first level SWSH (PE2), the first capacitor C1 IS charged, the current IC1 of the first capacitor C1 IS represented as a negative sign, and the second switch S2 IS turned on (i.e., the case where IS2 IS positive in fig. 6). When the switch control signal SWS has the second level SWSL (PE1, PE3), the first capacitor C1 IS discharged, the current IC1 of the first capacitor C1 IS represented as a positive sign, and the first switch S1 and the third switch S3 are turned on (i.e., the case of IS3 being positive in fig. 6).

The first charge pump voltage VCP1 maintains a certain target level while the switch control signal SWS alternately has the first level SWSH and the second level SWSL.

In fig. 7, if the level of the absolute value of the first charge pump voltage VCP1 is less than the absolute value of the target voltage VTAR, the output D of the first comparator a5 has a high level. When the output D of the first comparator a5 is high, the flip-flop FF outputs a clock signal CLK as an output signal Q. The symbol GND in fig. 7 indicates the ground level (the same applies to the other figures).

The output D of the first comparator a5 has a low level if the level of the absolute value of the first charge pump voltage VCP1 is greater than or equal to the absolute value of the target voltage VTAR. When the output D of the first comparator a5 is low, the flip-flop FF outputs a low level as an output signal Q.

The switch controller 712 generates the switch control signal SWS based on an output signal of the flip-flop FF.

The first charge pump 710 may further include a level shifter 713 disposed between the switch controller 712 and the first to fourth amplifiers a 1-a 4. The level shifter 713 increases the level of the switch control signal SWS to be output to the first to fourth amplifiers a1 to a 4.

Fig. 8 shows an example of setting the register of the arithmetic unit 711. The operator 711 of the first charge pump 710 may generate a reference charge pump voltage based on a register storing a headroom margin HM-VCP1 corresponding to the first charge pump voltage VCP1 and the output loads ILOAD1 through ilodn. Similarly, the operator of the second charge pump 730 may generate the reference charge pump voltage based on a register storing a headroom margin HM-VCP2 corresponding to the second charge pump voltage VCP2 and the output loads ILOAD1 to ilodn. In addition, in the register, the active/inactive HM-VCP1-EN of the headroom adjustment function of the first charge pump 710 and the active/inactive HM-VCP2-EN of the headroom adjustment function of the second charge pump 730 can be set.

Fig. 9 is a circuit diagram showing the first regulator 720 of fig. 4.

According to fig. 1 to 9, the first regulator 720 may include a fifth amplifier AMP and a fifth switch SWT connected to an output node of the fifth amplifier AMP. A control node of the fifth switch SWT may be connected to the output node of the fifth amplifier AMP, an input node of the fifth switch SWT may be applied with the first charge pump voltage VCP1, and an output node of the fifth switch SWT may output the first power supply voltage VINT.

The first adjustor 720 may further include: a first resistor R1 including a first terminal connected to the output node of the fifth switch SWT and a second terminal connected to a first input node of the fifth amplifier AMP; a second resistor R2 including a first end connected to the second end of the first resistor R1 and a second end connected to ground; and a stabilization capacitor CINT including a first electrode connected to the output node of the fifth switch SWT and a second electrode connected to the ground.

The target voltage VREF1 of the first power voltage VINT may be input to the second input node of the fifth amplifier AMP.

Fig. 10 is a table showing power consumption of the comparative example and power consumption of the present example.

Referring to fig. 1 to 10, the power supply voltage generating part according to the comparative example does not adjust the headroom based on the target voltage, and thus exhibits relatively high power consumption (10.5mW, 20.5mW, 31 mW). In the comparative example, the first charge pump voltage VCP1 for generating the initialization voltage (i.e., the first power supply voltage) VINT of-3.5V may be fixed to-7.8V (-PAVDD). The headroom of the first charge pump voltage VCP1 used to generate the initialization voltage VINT may be 4.3V. The power consumption may be calculated by multiplying the headroom by the load current. In the comparative example, the second charge pump voltage VCP2 for generating the gate low voltage (i.e., the second power supply voltage) VGL of-8.8V may be fixed to-11.1V (-PAVDD-VIN). A headroom of the second charge pump voltage VCP2 for generating the gate low voltage VGL may be 2.3V.

In contrast, the power supply voltage generating section 700 according to the present embodiment adjusts the headroom based on the target voltage, and thus exhibits relatively low power consumption (1.5mW, 3 mW). In the present embodiment, the first charge pump voltage VCP1 for generating the initialization voltage VINT of-3.5V may be adjusted to-3.8V, which is minus a preset headroom margin of 0.3V from-3.5V. The headroom of the first charge pump voltage VCP1 for generating the initialization voltage VINT may be 0.3V. Therefore, the power consumption for generating the initialization voltage VINT has a significantly small value compared to the comparative example. In the present embodiment, the second charge pump voltage VCP2 for generating the gate low voltage VGL of-8.8V may be adjusted to-9.1V, which is minus a preset headroom margin of 0.3V from-8.8V. A headroom of the second charge pump voltage VCP2 for generating the gate low voltage VGL may be 0.3V. Therefore, power consumption for generating the gate low voltage VGL has a significantly small value compared to the comparative example. The difference in power consumption of the comparative example and the embodiment for generating the initialization voltage VINT and the difference in power consumption of the comparative example and the embodiment for generating the gate low voltage VGL may be 9mW and 19mW, respectively. Therefore, the difference in total power consumption of the comparative example and the embodiment may be 28 mW.

Fig. 11 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the target voltage. Fig. 12 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the output load.

As shown in fig. 11, in the case of the comparative example, even if the target voltage VREF1 is decreased, a FIXED first charge pump voltage VCP1(FIXED) is generated, and in contrast, in the case of the present embodiment, as the target voltage VREF1 is decreased, a first charge pump voltage VCP1(VAR) is generated, which is decreased accordingly. (As the absolute value of the target voltage VREF1 increases, the absolute value of the first charge pump voltage VCP1(VAR) increases.)

As shown in fig. 12, in the case of the comparative example, even if the current IINT based on the output load increases, a FIXED first charge pump voltage VCP1(FIXED) is generated, whereas in the case of the present embodiment, in a state where the target voltage VREF1 is FIXED, a first charge pump voltage VCP1(VAR) that decreases as the output load increases is generated. (as the output load increases, the absolute value of the first charge pump voltage VCP1(VAR) increases.)

According to the present embodiment, the charge pump generates the charge pump voltage having the headroom automatically set and variable according to the target voltage, and thus the headroom of the charge pump voltage can be optimized. Therefore, power consumption of the display device can be reduced.

In addition, since the power supply voltage generating section adjusts the headroom of the charge pump voltage in accordance with the magnitude of the output load, the headroom of the charge pump voltage can be further optimized. Therefore, the power consumption of the display device can be further reduced.

(availability in industry)

According to the power supply voltage generation unit, the display device, and the power supply voltage generation method according to the present invention described above, power consumption of the display device can be reduced.

While the present invention has been described with reference to the embodiments, it will be understood by those skilled in the art that various modifications and changes may be made without departing from the spirit and scope of the invention.