阅读说明：本技术 一种四管电压基准电路 (Four-tube voltage reference circuit ) 是由 王东俊 邓乐武 张雷 魏平 张凯 于 2019-08-22 设计创作，主要内容包括：本发明涉及一种四管电压基准电路,包括第一NMOS管MN1、第二NMOS管MN2、第一PMOS管MP1和第二PMOS管MP2：所述第一NMOS管MN1与第二NMOS管MN2的漏极连接后接有电源电压；所述第一NMOS管MN1的栅极和源极短接,所述第一PMOS管MP1的源极和衬底短接,所述第二PMOS管MP2的栅极和漏极短接；所述第一PMOS管MP1的栅漏短接并连接第一NMOS管MN1和第二NMOS管MN2的衬底；所述第二PMOS管MP2的源极和衬底短接,且两者短接后连接并作为基准电路的输出基准电压。通过超宽温度范围极低功耗的四管电压基准电路,解决了现有带隙基准电路在电源电压低于0.7V开启电压时不能工作的问题。(The invention relates to a four-tube voltage reference circuit, which comprises a first NMOS tube MN1, a second NMOS tube MN2, a first PMOS tube MP1 and a second PMOS tube MP 2: the drain electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and then connected with a power supply voltage; the grid electrode and the source electrode of the first NMOS transistor MN1 are in short circuit, the source electrode and the substrate of the first PMOS transistor MP1 are in short circuit, and the grid electrode and the drain electrode of the second PMOS transistor MP2 are in short circuit; the gate-drain short circuit of the first PMOS transistor MP1 is connected with the substrate of the first NMOS transistor MN1 and the second NMOS transistor MN 2; the source electrode and the substrate of the second PMOS pipe MP2 are in short circuit, and the source electrode and the substrate are connected after being in short circuit and are used as the output reference voltage of the reference circuit. The problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than 0.7V starting voltage is solved through the four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption.)

1. A four-transistor voltage reference circuit comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a first PMOS transistor (MP1) and a second PMOS transistor (MP2), and is characterized in that:

The drain electrodes of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are connected and then connected with a power supply voltage VDD;

The grid electrode and the source electrode of the first NMOS transistor (MN1) are in short circuit, the source electrode and the substrate of the first PMOS transistor (MP1) are in short circuit, the grid electrode and the drain electrode of the second PMOS transistor (MP2) are in short circuit, and the grid electrode and the drain electrode are connected after the short circuit and are used as the output voltage VCTAT of the reference circuit;

The grid-drain short circuit of the first PMOS tube (MP1) is connected with the substrates of the first NMOS tube (MN1) and the second NMOS tube (MN2), and the three are grounded after being connected;

the gate-source of the second NMOS transistor (MN2) is in short circuit, the source of the second PMOS transistor (MP2) is in short circuit with the substrate, and the source of the second NMOS transistor and the substrate are connected after being in short circuit and are used as the output reference voltage of the reference circuit.

2. A four-transistor voltage reference circuit as claimed in claim 1, wherein: the first NMOS tube (MN1) and the second NMOS tube (MN2) are both NMOS tubes with the threshold voltage less than or equal to 0.5V.

3. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the first PMOS tube (MP1) and the second PMOS tube (MP2) are NMOS tubes with the threshold voltage being more than or equal to 0.7V. .

4. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the first NMOS transistor (MN1), the second NMOS transistor (MN2), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) all work in a voltage threshold region.

5. A four-transistor voltage reference circuit as claimed in claim 1, wherein: the formula of the output voltage VCTAT is as follows:

Wherein m1 and m2 are sub-threshold slope factors of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively, VT is a thermal voltage, and μ 1 and μ 2 are electron mobilities of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; c0x1 are gate oxidation capacitance values of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively; VTH1, VTH2 are the threshold voltage of the first NMOS transistor MN1 and the first PMOS transistor MP1 respectively; (W/L) N1, (W/L) P1 are the width-to-length ratios of the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively.

6. a four-transistor voltage reference circuit as claimed in claim 1, wherein: the output reference voltage V_REFthe formula of (1) is as follows:

Wherein (W/L)_N2、(W/L)_P2The width-to-length ratios of the second NMOS transistor MN2 and the second PMOS transistor MP2 are respectively.

the formula is simplified as follows:

Technical Field

the invention belongs to the technical field of integrated circuits, and particularly relates to a four-tube voltage reference circuit.

Background

the voltage reference circuit is an indispensable part in electronic systems including aviation, aerospace and the like, and in some special use environments of aviation and aerospace, the voltage reference circuit is required to be capable of generating a reference voltage source which does not change along with temperature within an ultra-wide temperature range. Also, the power consumption of the voltage reference circuit is as low as possible in view of the requirement for a battery weight as low as possible in aerospace applications. The most widely used traditional bandgap reference circuit cannot work under the ultra-low power supply voltage due to the limitation of the starting voltage, and generally cannot work normally under the voltage lower than 0.7V, so that the power consumption is relatively high.

Disclosure of Invention

The invention aims to overcome the problems in the prior art, and provides a four-tube voltage reference circuit which can be used for a four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption, can work under a power supply voltage of 0.45V, and solves the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows.

The utility model provides a four-tube voltage reference circuit, includes first NMOS pipe, second NMOS pipe, first PMOS pipe and second PMOS pipe, its characterized in that:

the drain electrodes of the first NMOS tube and the second NMOS tube are connected and then connected with a power supply voltage VDD;

The grid electrode and the source electrode of the first NMOS tube are in short circuit, the source electrode and the substrate of the first PMOS tube are in short circuit, the grid electrode and the drain electrode of the second PMOS tube are in short circuit, and the grid electrode and the drain electrode are connected after the short circuit and are used as the output voltage VCTAT of the reference circuit;

the grid-drain short circuit of the first PMOS tube is connected with the substrates of the first NMOS tube and the second NMOS tube, and the grid-drain short circuit of the first PMOS tube, the first NMOS tube and the second NMOS tube are grounded after being connected;

and the source electrode and the substrate of the second PMOS tube are in short circuit, and are connected after being in short circuit and are used as the output reference voltage of the reference circuit.

The first NMOS tube and the second NMOS tube are both NMOS tubes with threshold voltage less than or equal to 0.5V.

The first PMOS tube and the second PMOS tube are NMOS tubes with threshold voltage more than or equal to 0.7V.

The first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube work in a voltage threshold value area.

The formula of the output voltage VCTAT is as follows:

Wherein m1 and m2 are sub-threshold slope factors of the first NMOS transistor and the first PMOS transistor respectively, VT is a thermal voltage, and mu 1 and mu 2 are electron mobilities of the first NMOS transistor and the first PMOS transistor respectively; c0x1 is the gate oxidation capacitance value of the first NMOS tube and the first PMOS tube respectively; VTH1, VTH2 are the threshold voltage of the first NMOS tube and the first PMOS tube respectively; (W/L) N1 and (W/L) P1 are the width-length ratios of the first NMOS transistor and the first PMOS transistor, respectively.

The output reference voltage V_REFthe formula of (1) is as follows:

Wherein (W/L)_N2、(W/L)_P2The width-length ratios of the second NMOS tube and the second PMOS tube are respectively.

The formula is simplified as follows:

the invention has the advantages.

1. The four-tube voltage reference circuit with an ultra-wide temperature range and extremely low power consumption can work under a power supply voltage of 0.45V, and the problem that the conventional band-gap reference circuit cannot work when the power supply voltage is lower than a 0.7V starting voltage is solved; and the power consumption does not exceed two nanowatts, is far lower than that of the traditional band-gap reference, and can realize the work in an ultra-wide temperature range of-55 ℃ to 150 ℃.

drawings

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a simulation diagram of the four-transistor voltage reference circuit of the present invention obtained by Hspice simulation.

The labels in the figure are: MN1, a first NMOS transistor, MN2, a second NMOS transistor, MP1, a first PMOS transistor, MP2 and a second PMOS transistor.

Detailed Description

The invention is further described below with reference to the accompanying drawings.