阅读说明：本技术 一种多晶硅表面织构化工艺 (Polycrystalline silicon surface texturing process ) 是由 樊选东 于 2020-04-29 设计创作，主要内容包括：本发明涉及一种多晶硅表面织构化工艺,采用二次腐蚀法制备高质量的多晶硅绒面,包括以下步骤：电化学预腐蚀多晶硅,电化学腐蚀溶液为体积分数为40％的氢氟酸与体积分数为99.7％的无水乙醇的混合液,体积比为1:2；将多晶硅片置于腐蚀溶液中,对P型多晶硅片进行电化学预腐蚀；预腐蚀的多晶硅片用去离子水反复洗净,氮气吹干；电化学工作站采用三电极体系,硅片为工作电极,钽片为辅助电极,参比电极采用饱和甘汞电极,通过盐桥与工作电极连接；S3：采用化学腐蚀法对预腐蚀后的多晶硅片进行二次处理,得到高性能的多晶硅绒面；预腐蚀多晶硅片在HF和H2O2体积比为4:1的腐蚀溶液中进行二次处理,然后用无水乙醇反复洗净多晶硅片,氮气保护。(The invention relates to a polycrystalline silicon surface texturing process, which adopts a secondary corrosion method to prepare a high-quality polycrystalline silicon suede and comprises the following steps: electrochemically pre-etching the polysilicon, wherein the electrochemical etching solution is a mixed solution of 40% by volume of hydrofluoric acid and 99.7% by volume of absolute ethyl alcohol, and the volume ratio is 1: 2; placing the polycrystalline silicon wafer in a corrosive solution, and carrying out electrochemical pre-corrosion on the P-type polycrystalline silicon wafer; repeatedly cleaning the pre-etched polysilicon chips by using deionized water, and drying by using nitrogen; the electrochemical workstation adopts a three-electrode system, a silicon wafer is used as a working electrode, a tantalum sheet is used as an auxiliary electrode, and the reference electrode adopts a saturated calomel electrode and is connected with the working electrode through a salt bridge; s3: carrying out secondary treatment on the pre-etched polycrystalline silicon wafer by adopting a chemical etching method to obtain a high-performance polycrystalline silicon suede; carrying out secondary treatment on the pre-etched polycrystalline silicon wafer in an etching solution with the volume ratio of HF to H2O2 being 4:1, then repeatedly washing the polycrystalline silicon wafer with absolute ethyl alcohol, and protecting with nitrogen.)

1. A polysilicon surface texturing process adopts a secondary etching method to prepare a high-quality polysilicon suede, and is characterized by comprising the following steps: s1: electrochemically pre-etching the polysilicon, wherein the electrochemical etching solution is a mixed solution of 40% by volume of hydrofluoric acid and 99.7% by volume of absolute ethyl alcohol, and the volume ratio is 1: 2; the absolute ethyl alcohol has the main function of reducing the surface tension of the solution, is beneficial to smooth escape of H2 generated in the corrosion process and does not adhere to the surface of a silicon wafer, ensures that electrochemical corrosion is smoothly carried out, and obtains a polycrystalline silicon suede with uniform corrosion; placing a polycrystalline silicon wafer in a corrosive solution, carrying out electrochemical pre-corrosion on a P-type polycrystalline silicon wafer, monitoring the E-t curve change rule in the polycrystalline silicon corrosion process on line, controlling the input current density by an Autolab PGSTAT30 electrochemical workstation, wherein the corrosion time is 300s, and monitoring the E-t curve change rule in the silicon wafer corrosion process on line;

s2: repeatedly cleaning the pre-etched polysilicon chips by using deionized water, and drying by using nitrogen; the electrochemical workstation adopts a three-electrode system, a silicon wafer is used as a working electrode, a tantalum sheet is used as an auxiliary electrode, and the reference electrode adopts a saturated calomel electrode and is connected with the working electrode through a salt bridge;

s3: carrying out secondary treatment on the pre-etched polycrystalline silicon wafer by adopting a chemical etching method to obtain a high-performance polycrystalline silicon suede; carrying out secondary treatment on the pre-etched polycrystalline silicon wafer in an etching solution with the volume ratio of HF to H2O2 being 4:1, removing loose structures on the surface of the polycrystalline silicon under different etching conditions, then repeatedly cleaning the polycrystalline silicon wafer by absolute ethyl alcohol, and protecting the polycrystalline silicon wafer by nitrogen.

2. The polysilicon surface texturing process of claim 1, wherein in step S1, P-type polysilicon wafer is subjected to electrochemical pre-etching with an etching time of 300S and current densities of 10, 15, 20, 25 and 30mA/cm 2.

Technical Field

The invention relates to the technical field of solar cells, in particular to a polycrystalline silicon surface texturing process.

Background

As is well known, solar energy is the most ideal energy source for solving the problems of environmental pollution and energy shortage. The crystalline silicon solar cell dominates the international photovoltaic market, wherein the proportion of the polycrystalline silicon solar cell in the photovoltaic market in recent years is over 50%, and the polycrystalline silicon solar cell becomes one of the most widely applied solar cells. Whether the polycrystalline silicon solar cell generates electricity to replace conventional energy or not is critical whether the cost can be reduced to be competitive with the conventional energy or not. One of the effective ways to reduce the cost of polysilicon solar cells is to improve the photoelectric conversion efficiency. At present, there are many methods for improving the photoelectric conversion efficiency of a polysilicon solar cell, wherein the surface texturing of polysilicon reduces the reflection loss of light on the surface of the solar cell, and is one of the important methods for improving the photoelectric conversion efficiency. The surface texture, namely the preparation of the textured surface, means that after certain surface treatment, the surface of the solar cell is in an uneven hole-shaped form, so that light is reflected and absorbed on the surface of the solar cell for many times, the surface reflection is reduced, the light absorption is increased, and the photoelectric conversion efficiency is improved. The aperture and the depth of the suede are important parameters for measuring the quality degree of the suede, and the size of the aperture and the depth of the hole is related to the reflectivity, the minority carrier lifetime and the resistivity of the suede. In order to prepare the suede with low reflectivity, high minority carrier lifetime and high resistivity, the method is of great importance for the research of the suede aperture and the hole depth of the polycrystalline silicon solar cell.

In order to obtain a high-performance polysilicon surface texture, improve the photoelectric conversion efficiency of a polysilicon solar cell and reduce the large-scale process production cost, researchers explore a plurality of polysilicon texture surface technologies, and at present, methods such as mechanical grooving, reactive ion corrosion, acid corrosion and the like are mainly used. The invention has the following patent: the surface texturing processing method of the diamond wire polycrystalline silicon wafer (application publication number: CN110649105A) discloses a processing method, which comprises the following steps: s1, uniformly performing sand blasting treatment on one side surface of the diamond wire polycrystalline silicon wafer to form a sunlight incidence surface on the side surface; s2: putting the diamond wire polycrystalline silicon wafer treated in the step S1 into an etching solution for etching treatment, wherein the etching solution comprises 4-10% of hydrofluoric acid, 30-50% of nitric acid, 0.01-0.05% of surfactant, 0.01-0.5% of corrosion inhibitor, 0.01-0.5% of stabilizer and the balance of deionized water; although the similar suede method reduces the reflection of light and improves the photoelectric conversion efficiency, some defects exist, such as mechanical grooving generally requires that the thickness of a silicon wafer is not less than 200 μm; reactive ion etching requires a relatively complicated process and expensive equipment; the acid corrosion is a pure chemical reaction, and the stability of the reaction is not easy to control.

Therefore, further improvements in the polysilicon surface texturing process are needed.

Disclosure of Invention

The invention aims to provide a polysilicon surface texturing process.

In order to achieve the aim of the invention, the invention provides a polycrystalline silicon surface texturing process, which adopts a secondary etching method to prepare a high-quality polycrystalline silicon suede and comprises the following steps: s1: electrochemically pre-etching the polysilicon, wherein the electrochemical etching solution is a mixed solution of 40% by volume of hydrofluoric acid and 99.7% by volume of absolute ethyl alcohol, and the volume ratio is 1: 2; the absolute ethyl alcohol has the main function of reducing the surface tension of the solution, is beneficial to smooth escape of H2 generated in the corrosion process and does not adhere to the surface of a silicon wafer, ensures that electrochemical corrosion is smoothly carried out, and obtains a polycrystalline silicon suede with uniform corrosion; placing a polycrystalline silicon wafer in a corrosive solution, carrying out electrochemical pre-corrosion on a P-type polycrystalline silicon wafer, monitoring the E-t curve change rule in the polycrystalline silicon corrosion process on line, controlling the input current density by an automatic ab PGSTAT30 electrochemical workstation, wherein the corrosion time is 300s, and monitoring the E-t curve change rule in the silicon wafer corrosion process on line;

s2: repeatedly cleaning the pre-etched polysilicon chips by using deionized water, and drying by using nitrogen; the electrochemical workstation adopts a three-electrode system, a silicon wafer is used as a working electrode, a tantalum sheet is used as an auxiliary electrode, and the reference electrode adopts a saturated calomel electrode and is connected with the working electrode through a salt bridge;

s3: carrying out secondary treatment on the pre-etched polycrystalline silicon wafer by adopting a chemical etching method to obtain a high-performance polycrystalline silicon suede; carrying out secondary treatment on the pre-etched polycrystalline silicon wafer in an etching solution with the volume ratio of HF to H2O2 being 4:1, removing loose structures on the surface of the polycrystalline silicon under different etching conditions, then repeatedly cleaning the polycrystalline silicon wafer by absolute ethyl alcohol, and protecting the polycrystalline silicon wafer by nitrogen.

Further, in the step S1, the P-type polysilicon wafer is subjected to electrochemical pre-etching, the etching time is 300S, and the current density is 10, 15, 20, 25 and 30mA/cm2, respectively.

Under the constant current density, the initial potential of the electrochemical corrosion polycrystalline silicon slice is smaller, because the surface resistance of the initial polycrystalline silicon slice is smaller, and no oxide is formed on the surface; along with the generation of the oxide on the surface of the polycrystalline silicon, the surface resistance of the silicon wafer is increased, and the potential is rapidly increased. Under constant current density, the etching process shows up-and-down oscillation of potential, because an external electric field provides a cavity as an oxide for the surface of the polycrystalline silicon, the oxide is generated on a working electrode, namely the surface of the polycrystalline silicon, the surface resistance of the silicon wafer rises, and the working potential rises. The oxide generated on the surface of the polycrystalline silicon reacts with hydrofluoric acid immediately, the surface resistance of the silicon wafer is reduced, and the working potential is reduced. In the electrochemical etching process, the surface resistance of the polysilicon is increased along with the generation of SiO2 and is reduced along with the dissolution of SiO2, namely, the potential oscillation up and down is caused by the simultaneous oxidation and dissolution processes of the surface of the polysilicon.

When the current density is increased, the amplitude of the E-t curve oscillation of the etching process is increased along with the increase of the current density, and when the current density is 25mA/cm2, the surface oxidation speed of the polycrystalline silicon is higher than the dissolution speed, so that the potential is continuously increased. The larger amplitude of potential oscillations is obtained when the current density is 30mA/cm2, because this current density provides more holes to the silicon surface facing the tantalum electrode, thereby increasing the oxidation rate of the wafer, and this phenomenon can be explained by the Foll current burst theory, which is believed to be non-uniform spatially and temporally in the fluorine ion-containing solution, in which the silicon electrode is active throughout the anode region, and can pass a large anodic current, and the cell at any particular location on the polysilicon working electrode surface can be stationary or can undergo a burst reaction, thereby resulting in an increase in potential. In addition, an external electric field repels electrons on the surface of the silicon, a Schottky barrier is formed on the surface, and a fluctuation current is caused due to the existence of tiny potential fluctuation, so that the potential is violently oscillated. When the current density is 25mA/cm2, the surface oxidation speed of the polycrystalline silicon is faster, the surface oxidation speed of the polycrystalline silicon is close to the dissolution speed, the potential is violently vibrated up and down, and the obtained polycrystalline silicon suede structure is ideal.

Compared with the prior art, the polycrystalline silicon surface texturing process has the following advantages:

the high-quality polycrystalline silicon suede is prepared by adopting a secondary corrosion method, the polycrystalline silicon suede with good light trapping effect and antireflection effect is obtained, and the light absorption rate of the suede and the photoelectric conversion efficiency of the polycrystalline silicon solar cell are improved.

Detailed Description

The present invention will be further described with reference to the following specific examples.

The invention discloses a polycrystalline silicon surface texturing process, which adopts a secondary corrosion method to prepare a high-quality polycrystalline silicon suede and comprises the following steps: and electrochemically pre-etching the polysilicon, wherein the electrochemical etching solution is a mixed solution of 40% by volume of hydrofluoric acid and 99.7% by volume of absolute ethyl alcohol, and the volume ratio is 1: 2. The absolute ethyl alcohol has the main function of reducing the surface tension of the solution, is beneficial to the smooth escape of H2 generated in the corrosion process and does not adhere to the surface of a silicon wafer, ensures that the electrochemical corrosion is carried out smoothly, and obtains a polysilicon suede with uniform corrosion. Placing a polycrystalline silicon wafer in an etching solution, carrying out electrochemical pre-etching on the P-type polycrystalline silicon wafer at the etching time of 300s and the current densities of 10, 15, 20, 25 and 30mA/cm2 respectively, monitoring the change rule of an E-t curve in the etching process of the polycrystalline silicon on line, controlling the input current density through an Autolab PGSTAT30 electrochemical workstation, and monitoring the change rule of the E-t curve in the etching process of the silicon wafer on line at the etching time of 300 s. And repeatedly cleaning the pre-etched polysilicon chips by using deionized water, and drying by using nitrogen. The electrochemical workstation adopts a three-electrode system, a silicon wafer is used as a working electrode, a tantalum sheet is used as an auxiliary electrode, and the reference electrode adopts a Saturated Calomel Electrode (SCE) and is connected with the working electrode through a salt bridge.

And carrying out secondary treatment on the pre-etched polycrystalline silicon wafer by adopting a chemical etching method to obtain a high-performance polycrystalline silicon suede. Carrying out secondary treatment on the pre-etched polycrystalline silicon wafer in an etching solution with the volume ratio of HF to H2O2 being 4:1, removing loose structures on the surface of the polycrystalline silicon under different etching conditions, then repeatedly cleaning the polycrystalline silicon wafer by absolute ethyl alcohol, and protecting the polycrystalline silicon wafer by nitrogen.

Under the constant current density, the initial potential of the electrochemical corrosion polycrystalline silicon slice is smaller, because the surface resistance of the initial polycrystalline silicon slice is smaller, and no oxide is formed on the surface; along with the generation of the oxide on the surface of the polycrystalline silicon, the surface resistance of the silicon wafer is increased, and the potential is rapidly increased. Under constant current density, the etching process shows up-and-down oscillation of potential, because an external electric field provides a cavity as an oxide for the surface of the polycrystalline silicon, the oxide is generated on a working electrode, namely the surface of the polycrystalline silicon, the surface resistance of the silicon wafer rises, and the working potential rises. The oxide generated on the surface of the polycrystalline silicon reacts with hydrofluoric acid immediately, the surface resistance of the silicon wafer is reduced, and the working potential is reduced. In the electrochemical etching process, the surface resistance of the polysilicon is increased along with the generation of SiO2 and is reduced along with the dissolution of SiO2, namely, the potential oscillation up and down is caused by the simultaneous oxidation and dissolution processes of the surface of the polysilicon.

When the current density is increased, the amplitude of the E-t curve oscillation of the etching process is increased along with the increase of the current density, and when the current density is 25mA/cm2, the surface oxidation speed of the polycrystalline silicon is higher than the dissolution speed, so that the potential is continuously increased. The larger amplitude of potential oscillations is obtained when the current density is 30mA/cm2, because this current density provides more holes to the silicon surface facing the tantalum electrode, thereby increasing the oxidation rate of the wafer, and this phenomenon can be explained by the Foll current burst theory, which is believed to be non-uniform spatially and temporally in the fluorine ion-containing solution, in which the silicon electrode is active throughout the anode region, and can pass a large anodic current, and the cell at any particular location on the polysilicon working electrode surface can be stationary or can undergo a burst reaction, thereby resulting in an increase in potential. In addition, an external electric field repels electrons on the surface of the silicon, a Schottky barrier is formed on the surface, and a fluctuation current is caused due to the existence of tiny potential fluctuation, so that the potential is violently oscillated. When the current density is 25mA/cm2, the surface oxidation speed of the polycrystalline silicon is faster, the surface oxidation speed of the polycrystalline silicon is close to the dissolution speed, the potential is violently vibrated up and down, and the obtained polycrystalline silicon suede structure is ideal.

The polycrystalline silicon is treated by adopting a secondary etching method, and the following characteristics are obtained:

1) the potential oscillation amplitude is increased along with the increase of current density in the corrosion process, the oxidation speed of the surface of the polycrystalline silicon is accelerated, and the surface resistance of the polycrystalline silicon is continuously increased. When the current density is 25mA/cm2, the dissolution rate of the polycrystalline silicon surface is close to the oxidation rate.

2) When the current density is 30mA/cm2, round holes begin to appear on the surface of the polycrystalline silicon, and along with the continuous increase of the current density, the number of the round holes on the surface of the polycrystalline silicon is obviously increased, and the depth of the corrosion pits is increased; when the current density is increased to 30mA/cm2, the depth and the size of the polysilicon etch pit are ideal.

3) After electrochemically etched polycrystalline silicon is subjected to ultrasonic corrosion for 60s in a chemical acid corrosion solution with the volume ratio of HF to H2O2 being 4:1, worm-like patterns appear on the surface of the polycrystalline silicon, the texture surface structure is ideal, the diameter of a corrosion pit reaches 2-4 mu m, the depth of the corrosion pit is 1.5-2 mu m, the optical trapping effect and the antireflection effect are good, and the method is suitable for manufacturing a polycrystalline silicon solar cell.

In the description herein, it will be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in an orientation or positional relationship indicated herein for convenience and simplicity of description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting to the present patent application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.

In this specification, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral combinations thereof; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable manner, unless otherwise specifically limited. The specific meanings of the above terms in the present specification can be understood by those of ordinary skill in the art as appropriate.

In this specification, unless explicitly stated or limited otherwise, a first feature may be "on" or "under" a second feature such that the first and second features are in direct contact, or the first and second features are in indirect contact via an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or obliquely above the second feature, or may simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.