阅读说明：本技术 复用dlts和hscv测量系统 (Multiplexing DLTS and HSCV measurement system ) 是由 罗伯特·杰弗里·贝利 于 2019-06-10 设计创作，主要内容包括：描述了能够进行复用DLTS和HSCV测量的技术和系统。(Techniques and systems are described that enable multiplexed DLTS and HSCV measurements.)

1. An apparatus, comprising:

A first input configured to be connected to a semiconductor device through an interface;

A first output configured to be connected to a semiconductor device through an interface;

a first circuit configured to generate a set of waveform cycles at the first output, each cycle having:

A first time portion having a first signal configured to fill a set of charge trapping defects in the semiconductor device with free carriers;

A second time portion having a second signal configured to cause a subset of free carriers to be ejected from the set of charge trapping defects based on a time constant;

The first subset of cycles corresponding to less than the entire set of waveform cycles further has:

Third and fourth signals during the second portion of time, the third and fourth signals configured such that corresponding amounts of free carriers that fill and/or exit from the set of charge trapping defects are in confinement, the third signal occurring earlier than the second signal, the fourth signal occurring later than the second signal; and

A second circuit configured to measure a first set of capacitive characteristics at the first input based in part on the third signal and a second set of capacitive characteristics at the first input based in part on the fourth signal to determine a change in depth distribution of charge in the semiconductor device at different times during the second portion of time.

2. The apparatus of claim 1, wherein the semiconductor device is a photovoltaic cell.

3. the device of claim 2, wherein the photovoltaic cell is a Copper Indium Gallium Selenide (CIGS) photovoltaic cell.

4. The apparatus of claim 1, wherein the duration of the third signal is selected such that a difference between a first sample value from the capacitance transients during the third signal and a second sample value from a second capacitance transient during a second time portion of the cycle not included in the first subset of cycles is below a threshold.

5. the apparatus of claim 4, wherein the threshold is approximately 3 pF.

6. The apparatus of claim 1, wherein the third signal has:

A duration of about 1 ms;

about 25 voltage steps;

And a voltage range of about-1V to about-0.2V.

7. The apparatus of claim 6, wherein the third signal and the fourth signal have the same duration, number of voltage steps, and voltage range.

8. The apparatus of claim 1, wherein a single cycle in the first subset of cycles follows a single cycle not in the first subset of cycles.

9. The apparatus of claim 1, wherein each cycle in the first subset of cycles comprises three voltage ramps to measure a capacitance characteristic at the first input to determine a change in a depth distribution of charge in the semiconductor device during the second time portion, the three voltage ramps comprising the third signal and the fourth signal.

10. The apparatus of claim 1, wherein the first subset of the set of charge trapping defects correspond to metastable defects that are responsive to at least one of an optical effect or a hysteresis effect.

Technical Field

the present invention relates to techniques and systems that enable multiplexed DLTS and HSCV measurements.

Background

In semiconductor materials, deviations from the lattice structure may correspond to physical defects. Certain types of these physical defects have an effect on the electrical properties of the semiconductor material, for example in the form of charge carrier traps which affect the mobility of charge carriers such as free electrons or electron holes. Some traps are called deep traps because the energy to release charge carriers from deep traps exceeds the characteristic thermal energy. Poor mobility of charge carriers affects the operation of transistors, light emitting diodes, photovoltaic cells, and the like. As one example, a failure mode of a metal semiconductor field effect transistor (MOSFET) involves Bias Temperature Instability (BTI), which occurs when a trap causes a shift in the operating threshold voltage of the transistor when the trap is filled with charge carriers. As another example, Copper Indium Gallium Selenide (CIGS) solar cells can have a class of defects with metastable behavior, e.g., in response to light or hysteresis effects, thereby complicating CIGS device characterization.

Deep Level Transient Spectroscopy (DLTS) is a capacitance-based device characterization method that is widely used in semiconductor and Photovoltaic (PV) applications to determine the number and type of charge trapping defects in the active area of solar or semiconductor devices. High speed cv (hscv) is another method for profiling charge distribution in semiconductor devices, sometimes with greater accuracy than DLTS systems. In HSCV, voltage sweeps occur over short time intervals so that charge trapping defects can neither trap free carriers nor release carriers they trap, thereby avoiding associated capacitance transients.

DLTS and HSCV are common semiconductor device characterization methods. Conventionally, however, they are performed sequentially, requiring separate analyses that may represent different device states. For example, in CIGS solar cells, due to their particular set of defective features, it is common for the DLTS measurement to change the state of the device such that the HSCV measurement yields different results before and after the DLTS. CIGS device variation during DLTS cannot be directly measured because the HSCV and DLTS methods are typically performed sequentially.

Disclosure of Invention

One aspect of the subject matter described herein relates to an apparatus comprising: a first input configured to be connected to a semiconductor device through an interface; a first output configured to be connected to a semiconductor device through an interface; a first circuit configured to generate a set of waveform cycles at a first output, each cycle having: a first time portion having a first signal configured to fill a set of charge trapping defects in a semiconductor device with free carriers; a second time portion having a second signal configured to cause a subset of free carriers to be ejected from the set of charge trapping defects based on a time constant; the first subset of cycles corresponding to less than the entire set of waveform cycles further has: third and fourth signals during a second portion of time, the third and fourth signals configured to place respective amounts of free carriers that fill and/or exit the set of charge trapping defects within limits, the third signal occurring earlier than the second signal and the fourth signal occurring later than the second signal. The apparatus also includes a second circuit configured to measure a first set of capacitive characteristics at the first input based in part on the third signal and a second set of capacitive characteristics at the first input based in part on the fourth signal to determine a change in the depth distribution of charge in the semiconductor device at different times during the second portion of time.

In some embodiments, the semiconductor device is a photovoltaic cell. In some embodiments, the photovoltaic cell is a Copper Indium Gallium Selenide (CIGS) photovoltaic cell. In some embodiments, the duration of the third signal is selected such that a difference between a first sample value and a second sample value is below a threshold, wherein the first sample value is from a capacitance transient during the third signal and the second sample value is from a second capacitance transient during a second time portion of the cycle that is not included in the first subset of cycles. In some embodiments, the threshold is about 3pF (picofarad). In some embodiments, the third signal has: a duration of about 1 ms; about 25 voltage steps; and a voltage range of about-1V to about-0.2V. In some embodiments, the third signal and the fourth signal have the same duration, number of voltage steps, and voltage range. In some embodiments, a single cycle in the first subset of cycles follows a single cycle that is not in the first subset of cycles. In some embodiments, each cycle in the first subset of cycles includes three voltage ramps for measuring a capacitance characteristic at the first input to determine a change in a depth distribution of charge in the semiconductor device during the second portion of time, the three voltage ramps including a third signal and a fourth signal. In some embodiments, the first subset of the set of charge trapping defects correspond to metastable defects that are responsive to at least one of an optical effect or a hysteresis effect. Implementations of the described technology may include hardware, methods or processes, or computer software on a computer-accessible medium.

Another aspect of the subject matter described herein relates to a method comprising: generating a set of waveform cycles at a first output configured to interface to a semiconductor device, each cycle having: a first time portion having a first signal configured to fill a set of charge trapping defects in the semiconductor device with free carriers; a second time portion having a second signal configured to cause a subset of free carriers to be ejected from the set of charge trapping defects based on a time constant; the first subset of cycles corresponding to less than the entire set of waveform cycles further has: a third signal and a fourth signal during a second portion of time, the third signal and the fourth signal configured such that respective amounts of free carriers that fill and/or exit the set of charge trapping defects are in confinement, the third signal occurring earlier than the second signal, the fourth signal occurring later than the second signal. The method also includes measuring, at a first input configured to interface to the semiconductor device, a first set of capacitance characteristics based in part on the third signal, and measuring, at the first input, a second set of capacitance characteristics based in part on the fourth signal to determine a change in the depth distribution of charge in the semiconductor device at a different time during a second portion of time.

In a particular embodiment, the semiconductor device is a photovoltaic cell. In particular embodiments, the photovoltaic cell is a Copper Indium Gallium Selenide (CIGS) photovoltaic cell. In a particular implementation, the duration of the third signal is selected such that a difference between a first sample value and a second sample value is below a threshold, wherein the first sample value is from a capacitance transient during the third signal and the second sample value is from a second capacitance transient during a second time portion of the cycle that is not included in the first subset of cycles. In a particular embodiment, the threshold is about 3 pF. In certain embodiments, the third signal has: a duration of about 1 ms; about 25 voltage steps; and a voltage range of about-1V to about-0.2V. In certain embodiments, the third signal and the fourth signal have the same duration, number of voltage steps, and voltage range. In a particular embodiment, a single cycle in the first subset of cycles follows a single cycle that is not in the first subset of cycles. In a particular embodiment, each cycle in the first subset of cycles includes three voltage ramps for measuring a capacitance characteristic at the first input to determine a change in a depth distribution of charge in the semiconductor device during the second time portion, the three voltage ramps including a third signal and a fourth signal. In a particular embodiment, the first subset of the set of charge trapping defects correspond to metastable defects that are responsive to at least one of an optical effect or a hysteresis effect.

Another aspect of the subject matter described herein relates to a computer program product comprising computer readable program code executed by one or more processors when retrieved from a non-transitory computer readable medium, the program code comprising instructions configured to cause: generating a set of waveform cycles at a first output configured to interface to a semiconductor device, each cycle having: a first time portion having a first signal configured to fill a set of charge trapping defects in the semiconductor device with free carriers; a second time portion having a second signal configured to cause a subset of free carriers to be ejected from the set of charge trapping defects based on a time constant; the first subset of cycles corresponding to less than the entire set of waveform cycles further has: a third signal and a fourth signal during a second portion of time, the third and fourth signals configured such that corresponding quantities of free carriers that fill and/or exit the set of charge trapping defects are in confinement, the third signal occurring earlier than the second signal and the fourth signal occurring later than the second signal. The method also includes measuring, at a first input configured to interface to the semiconductor device, a first set of capacitance characteristics based in part on the third signal, and measuring, at the first input, a second set of capacitance characteristics based in part on the fourth signal to determine a change in the depth distribution of charge in the semiconductor device at a different time during a second portion of time.

These and other aspects are described further below with reference to the figures.

Drawings

FIG. 1A shows a multiplexed DLTS and HSCV measurement system.

FIG. 1B illustrates an example flow diagram of a multiplexed DLTS and HSCV measurement system.

FIG. 1C shows an example of voltage applied to a DUT in a DLTS measurement system.

FIG. 2 shows an example of the voltage applied to a DUT in a HSCV measurement system.

FIG. 3 shows an example of multiplexing voltages applied to a DUT in a DLTS and HSCV measurement system.

FIG. 4 shows a further example of a change in a DUT in response to HSCV measurements.

FIG. 5 shows an example of a change in a DUT in response to HSCV measurements.

Fig. 6 shows an example of variations in DUTs in different configurations in response to HSCV measurements.

Detailed Description

this disclosure describes systems and techniques for multiplexing DLTS and HSCV measurement systems. For example, when CIGS solar cells were characterized using the DLTS method, the HSCV method was used to measure how CIGS changes during DLTS.

Deep Level Transient Spectroscopy (DLTS) is a capacitance-based device characterization method that can be used in semiconductor and PV applications to determine the number and type of charge trapping defects in the active area of solar or semiconductor devices. There are a number of methods for interpreting DLTS spectra to obtain the activation energies of complex active defects, their trapping cross-sections and their concentrations. DLTS can operate in a digital mode whereby the output of a fast capacitance meter is digitally sampled at a high rate during capacitive transients induced by varying the voltage applied to a Device Under Test (DUT), such as a CIGS solar cell. The capacitive transients result from an evolving trapped charge distribution in the device.

In DLTS, the temperature of the DUT can change, causing the capacitance transient time constant to change. The relationship between temperature and time constant can be analyzed to determine the kinetics of emission of trapped charges in the device. By varying the voltage applied to the DUT, the depth at which injected carriers enter the active region of the device can be controlled. By repeating the DLTS measurement at different voltage settings, the location of the charge trapping defects can be inferred by comparing the magnitude of the DLTS response among the different discrete voltage values. In this way, a concentration (e.g., depth of charge) profile can be generated. In some scenarios, the DLTS method involves repeated measurements to perform a temperature scan.

Capacitance-voltage (C-V) technology is an example of another method for profiling charge distribution in semiconductor devices. In CV techniques, the capacitance of the DUT over a range of applied voltages in a static device is recorded for a time ranging from a few seconds to a few minutes. From this capacitance-voltage relationship, the shallow dopant profile in the DUT can be calculated. In some cases, the interpretation of CV results is complicated by the presence of charge trapping defects that can cause capacitance transients and accumulate trapped charge in the active region.

The high speed CV (hscv) method eliminates some of the problems of conventional CV in some plants. In HSCV, the voltage sweep occurs within, for example, one millisecond. In some cases, for such time intervals, the charge trapping defects do not capture free carriers nor release their trapped carriers, so that there is no corresponding capacitance transient (e.g., the charge distribution is substantially frozen in place). The measured HSCV profile represents the total charge density (e.g., dopant plus ionized defects) based on direct interpretation and is used to diagnose varying charge distribution in the device and, in certain cases, can help reveal the source of the variation.

This disclosure describes systems and techniques for multiplexing DLTS and HSCV measurement systems. In certain embodiments, because the HSCV is able to diagnose varying charge distributions in the device, the HSCV measurements performed during DLTS measurements can accurately reveal the varying charge distributions of the capacitive transients that produced the DLTS for processing and analysis. The disclosed technology integrates DLTS and HSCV measurements simultaneously in measurements such as digital data acquisition platforms.

in one class of embodiments, the DLTS measurement is configured to employ a repeating pulse loop or waveform loop in which the capacitance transient can be continuously monitored and analyzed, each HSCV voltage sweep is configured to last, for example, approximately one millisecond, the HSCV voltage sweep is periodically inserted into a repeating DLTS pulse sequence, and the DLTS and HSCV signals can be independently processed.

It should be appreciated that the disclosed techniques are capable of providing DLTS measurements and a simultaneous series of temperature-dependent charge distributions in approximately the same amount of time as the DLTS measurements themselves. It should be noted that multiplexing the DLTS and HSCV measurements may enable observation of the changing charge and/or effective doping profile that occurs during the DLTS measurement (e.g., using HSCV to study the charge evolution during capacitive transients in the DLTS measurement). An analysis of the recorded capacitance values and an example of a voltage pulse sequence is illustrated by the figures discussed below.

The particular signs (e.g., positive, negative) of the voltage and capacitance values in the following figures are for example purposes, and the particular signs of the voltage or capacitance values may differ based on the measurement setup and/or the configuration of the DUT. It should also be understood that the specific values and units of voltages and capacitances in the following figures are for example purposes, and that the values may be expressed as relative changes (e.g., ratios, percentages, delta values, etc.), and/or the units may differ based on measurement settings and/or configuration of the DUT. It should also be understood that in some embodiments, a current source may be used instead of a voltage source.

FIG. 1A illustrates an example embodiment of a multiplexed DLTS and HSCV measurement system 150. The circuitry in signal source 151 used to generate the pulse cycles shown in fig. 1C-6 below may include one or more voltage and/or current sources for interfacing to one or more DUTs, such as semiconductor device 151, through output port 153, and can include, but is not limited to, a function generator, an arbitrary waveform generator, and the like. Circuitry in signal analyzer 155 for measuring waveforms and/or data points shown in fig. 1C-6 below may include one or more voltage, current, temperature, and/or capacitance sensors, testers, oscilloscopes, Data Acquisition (DAQ) devices, etc. for interfacing to one or more DUTs, such as semiconductor device 151, through input port 154. The configuration of the components of the multiplexed DLTS and HSCV measurement system 150 is described in further detail with respect to the discussion of FIGS. 1C through 6 below.

FIG. 1B illustrates an example process 160 for multiplexing DLTS and HSCV measurement systems. In one class of embodiments, the process includes generating a set of waveform cycles at a first output of a signal source configured to interface to a semiconductor device (e.g., semiconductor device 151 in fig. 1A). For example, at 161, the flow includes generating a first time portion (e.g., a pulse phase) having a first signal configured to fill a set of charge trapping defects in the semiconductor device with free carriers. At 162, the flow includes generating a second portion in time (e.g., a relaxation phase) having a second signal configured to cause a subset of free carriers to be ejected from the set of charge trapping defects based on a time constant.

in a subset of the cycles, the flow further includes generating a third signal (164) and a fourth signal (166) for a second portion of time (e.g., a relaxation phase), the third and fourth signals (e.g., different HSCV voltage ramps) configured such that a corresponding number of free carriers filling and/or exiting the set of charge trapping defects are in a constraint (e.g., the perturbation of the capacitive transient relaxation phase is limited to, for example, less than 3 pF). As described in further detail below with respect to the discussion of fig. 1C-6, the third signal occurs earlier than the second signal and the fourth signal occurs later than the second signal, enabling the evolution of the depth of charge distribution during a capacitance transient to be observed.

The flow also includes measuring a first set of capacitive characteristics based in part on the third signal at a first input (168) configured to interface to the semiconductor device and measuring a second set of capacitive characteristics based in part on the fourth signal at the first input (170). These different sets of capacitance characteristics are used at 172 for determining a change in the depth distribution of charge in the semiconductor device at different times during the second time portion relative to the respective third and fourth signals. The examples discussed below with respect to fig. 1C through 6 will be illustrative.

Fig. 1C shows a pair 100 of a voltage versus time 110 curve and a capacitance versus time 105 curve, depicting an example of the voltage applied to a DUT (e.g., a CIGS solar cell) in a DLTS measurement, and an example of the capacitance in the DUT in response to the applied voltage. The repetitive voltage profile applied to the device divides each cycle into two phases. At the "pulse" signal (e.g., stage 106), the DUT is biased to a voltage near, for example, zero. During this time (depicted in fig. 1C as about 10ms, as indicated by pulse width 102, pulse width 103), charge trapping defects in the active region of the device are filled with free carriers. During the "relaxation" signal (e.g., phase 107), the voltage is held at a reverse bias voltage, e.g., between about-0.5V to-2V, to cause free carriers to exit from the device active region.

in fig. 1C, the capacitance changes in two ways: during the pulse phase 106, as the voltage on the DUT increases (to values outside the indicated range in fig. 1C), the capacitance changes, and as the capacitance change (e.g., capacitance change 116) recovers in the relaxation phase 107 when reverse biased, the trapped carriers are emitted with a characteristic time constant at time interval 117, producing a typical exponential change in capacitance (e.g., capacitance transient 115). DLTS measurement systems use high speed acquisition of capacitance transients, for example from a fast capacitance meter, to analyze the capacitance transients during the relaxation phase.

In certain embodiments, repetitive pulsing and data acquisition are used to increase the signal-to-noise ratio as the temperature (and thus the capacitance transient time constant) continuously changes over time. For example, the measurement period of DLTS is 1 second as shown in fig. 1C, and in various embodiments, the temperature is slowly varied so that at least several (3 to 10) periods can be averaged at the same effective temperature. Background details of the DLTS method are described in LANG, D.V. "Deep-level transient spectroscopy: A new method to characteristics traces in semiconductors", Journal of Applied Physics, 45(7) ": 3023-3032, 1974, the entire disclosure of which is incorporated herein by reference for all purposes.

Fig. 2 shows a pair 200 of a voltage versus time 210 curve and a capacitance versus time 205 curve, depicting an example of a voltage applied to a DUT (e.g., a CIGS solar cell) in an HSCV measurement, and an example of a capacitance in the DUT in response to the applied voltage. In fig. 2, the voltage ramps up for more than 1ms (shown by time interval 225, time interval 255), beginning and ending at the boundary voltage (shown by voltage interval 235 starting at about-0.1V and ending at about-1.0V, with a corresponding overall capacitance change interval 265). In each voltage step (10 steps in the example shown in fig. 2), the capacitances may be averaged digitally, resulting in a series of C and V values (e.g., voltage value 220 is associated with capacitance value 250). It should be understood that the particular boundary voltage and the particular number of voltage steps during the HSCV voltage ramp are not limited to the example shown in FIG. 2. For example, a particular number of voltage steps (or voltage steps 230) is selected such that the dwell time for each voltage allows a stable capacitance value to be measured after each capacitance step (e.g., capacitance change 260), while limiting the total ramp time to no greater than about, for example, 1 ms. In one class of embodiments, about 25 voltage steps are used. It should be understood that the voltage profiles in fig. 2 are non-limiting examples, and that the dwell time for each voltage step may be non-uniform, the voltage steps may be repeated, or the voltage steps may not necessarily decrease or increase in sequence, etc. Background details of CV and HSCV methods are described in PAUL et al, "Fast CV method to all of deep levels in CIGS doping profiles (Fast C-V method to mitigate the effects of deep levels in CIGS doping profiles)" arXiv: 1706.09946[ physics, ins-det ], 2017 and BOESCH, Jr., Edwin H., "Development of Apparatus for Performing fast Capacitance-Voltage Measurements on MIS Structures", Harry Diamond Laboratories, Harry Mond research, report the number HDL-TM-76-33,1976, the entire disclosure of which is incorporated herein by reference for all purposes.

FIG. 3 illustrates an example of a method 300 for multiplexing DLTS and HSCV measurements. The voltage trace depicts several voltage pulse cycles (e.g., pulse cycle 305, pulse cycle 307) that represent the DLTS pulse cycle as previously discussed with respect to fig. 1C. In the example of fig. 3, based on the predetermined ratio, the DLTS pulse cycles alternate in a cycle that includes one or more applied HSCV voltage ramps (e.g., pulse cycle 306 and pulse cycle 308). Fig. 3 shows 1: a ratio of 1, corresponding to one HSCV pulse cycle followed by one DLTS pulse cycle. The ratio may vary, for example, the ratio is 1000: 1, each HSCV pulse cycle has 1000 DLTS pulse cycles. It should be understood that as referred to herein, one HSCV pulse cycle includes one or more HSCV measurements, as previously discussed with respect to fig. 2.

For a DLTS pulse cycle, the capacitance transients are acquired and analyzed according to the DLTS method as discussed with respect to fig. 1C. In the HSCV pulse cycle, one or more HSCV voltage ramps are overlapped during the relaxation phase at predetermined intervals, which may include an interval 320 between the start of the pulse cycle to the HSCV voltage ramp, an interval 321 between the HSCV voltage ramp, and/or an interval 322 between the HSCV voltage ramp and the end of the pulse cycle. Two are shown in fig. 3 for the HSCV pulse cycle 306 (e.g., voltage ramps 312a and 312b, with an enlarged view of voltage ramp 312a at the top of fig. 3), but it should be understood that the specific number of HSCV voltage ramps and the duration of the time intervals can vary from the example shown in fig. 3. In one class of embodiments, the voltage ramps within the HSCV pulse cycle, e.g., voltage ramp 312a and voltage ramp 312b, may be configured differently. Further, in some embodiments, the configuration of the voltage ramp across different HSCV pulse cycles may be different (e.g., including, but not limited to, voltage range 330, dwell time 331, voltage step 332, timing interval 334, etc.). For example, in FIG. 3, the number of HSCV pulse cycles in pulse cycle 308 may be different from the number in pulse cycle 306, the configuration of the HSCV voltage ramps 313a-b may be different from the voltage ramps 312a or 312b, and the timing interval 323-325 may be different from the corresponding timing interval 320-322.

During these HSCV pulse cycles, the DLTS analysis may be idle without processing data, instead each individual HSCV voltage ramp (e.g., voltage ramp 312a) can be used to acquire, store, and process the C-V data for that particular pulse cycle. In a particular embodiment, changes in different sets of C-V data corresponding to different HSCV voltage ramps provide a snapshot of the evolving charge distribution during a DLTS capacitance transient. For example, the evolving charge distribution during the capacitance transient 310 is observed using the C-V data for voltage ramp 312a and the C-V data for voltage ramp 312 b. Furthermore, differences in the evolving charge distribution of different capacitance transients, such as the difference between capacitance transient 310 and capacitance transient 311, can be observed. It should be appreciated that the evolving charge distribution is determined for a particular condition (e.g., temperature, etc.) of a particular DLTS pulse cycle, and the entire DLTS measurement process is performed simultaneously.

Fig. 4 depicts a series of traces representing the charge distribution that evolves during a capacitance transient. The traces correspond to three different times during the capacitive transient as shown by the legend entries of 5ms (milliseconds), 450ms, and 875 ms. As an example, trace 413 of capacitance versus voltage curve 410, which corresponds to performing an HSCV voltage ramp at 5ms, represents a voltage value versus capacitance pair (specifically, picofarads per square centimeter) of approximately-1 to 0V over a 25 (number of markers in trace 413) distinct voltage sweep range. It should be understood that the particular orientation of the x-axis in curve 410, from-1 to 0V (volts), may be for clarity purposes and does not necessarily indicate that the HSCV voltage ramp starts at-1V and pF and ends at 0V.

Fig. 4 shows traces 414 and 415 offset from trace 413, indicating that the capacitance versus voltage observed by the HSCV voltage ramp at 5ms is different than the capacitance versus voltage observed by the HSCV voltage ramp at 450ms (and 875 ms). This change in capacitance versus voltage on the three traces represents the charge distribution that evolves during the capacitance transient at three different times.

The evolving charge distribution can also be expressed as a plot 405 of charge (in units of N, units of electron charge e per cubic centimeter) versus spatial depth (in microns). The time series of traces 406, 407, and 408, corresponding to 5ms, 450ms, and 875ms, respectively, show that over time, there is a transition to a greater charge density (e.g., arrow 403 in the direction of increasing charge density) in a shallower region of the DUT (e.g., arrow 404 in the direction of decreasing depth) during the capacitive transient. Observing the evolving charge distribution can provide information about the characteristics of defects in the DUT. For example, some types of defects may trap and/or release charge carriers on a fast time scale that cannot be determined using the disclosed techniques, so observing the evolving charge distribution can indicate the presence of a particular type of defect.

It should be appreciated that the interval duration 334 of the HSCV voltage ramp is a duration relative to the duration of the DLTS pulse phase (e.g., pulse 301) such that the HSCV measurement has limited effect on the overall capacitance transient relative to a pulse cycle without HSCV measurement. For example, the duration of the HSCV voltage ramp is selected to be shorter than the timing threshold based on the shorter time required to fill the charge trapping defects during the pulse phase or the relaxation time constant during the relaxation phase. The HSCV voltage ramp may cause additional defective charging or relaxation if its duration exceeds a timing threshold.

FIG. 5 shows an example of HSCV measurements that produce a disturbance to the entire capacitance transient. Plot 505 depicts a DLTS pulse sequence without any HSCV voltage ramp, where trace 506 represents the voltage signal with an initial pulse phase followed by a relaxation phase, and trace 507 represents the corresponding capacitance in the DUT. Plot 515 depicts a DLTS pulse sequence having three HSCV voltage ramps (e.g., voltage ramps 518, 519, 520), where trace 516 represents a voltage signal having an initial pulse phase followed by a relaxation phase including voltage ramp 518-520. Trace 517 represents the corresponding capacitance in the DUT, and capacitance increments 521, 525, and 530 are perturbations in the capacitance transient relative to the capacitance transient shown in plot 505. It should be appreciated that the magnitude of the capacitive transient disturbance will increase as the timing duration of the voltage ramp 518 and 520 increases, and vice versa.

FIG. 6 shows an example plot 600 of capacitance transient disturbance amplitude for different durations of the HSCV voltage ramp for a DLTS pulse width of 100ms (as shown in FIG. 5). For example, for a voltage ramp duration of 0.1 seconds (100ms), as indicated by reference numeral 615, the observed capacitance increase ranges from as low as about 12pF to as high as about 15 picofarads, as indicated by the capacitance perturbation range 605. As an example, for a DLTS pulse width of 100ms, a capacitive transient disturbance (e.g., capacitance delta 521, 525, 530) of about 12pF to about 15pF can be generated per 100ms voltage ramp duration during a relaxation phase of about 900 ms.

Curve 600 shows that as the HSCV voltage ramp timing duration increases, the magnitude of the capacitive transient disturbance increases, and vice versa. For example, when the HSCV voltage ramp timing duration is reduced to 0.1ms, as shown at reference 620, the magnitude of the capacitive transient disturbance has a limited effect of a capacitive delta, capacitive disturbance range 610 of about 2.5 pF. As an example, for a DLTS pulse width of 100ms, a capacitive transient disturbance (e.g., capacitance increase 521, 525, 530) of about 2.5pF can be generated per 1ms voltage ramp duration during a relaxation phase of about 900 ms. It should be appreciated that curve 600 indicates that even a small HSCV voltage ramp timing duration (e.g., 0.1ms) causes a small step in capacitance (e.g., charge trapping occurs). However, the overall capacitance transient characteristics are preserved, and the HSCV measurements can provide information about the change in charge distribution from the beginning to the end of the capacitance transient.

The various embodiments described herein may be implemented using any of a variety of standard or proprietary discrete electronic devices or integrated semiconductor processes. Additionally, it should be noted that embodiments are understood that a wider range of semiconductor materials and fabrication processes may be employed, including, for example, CMOS, CIGS, GaAs, SiGe, and the like.

As described above, in some embodiments, the devices and methods can be used to characterize photovoltaic materials and cells. For example, in addition to CIGS cells, aspects of the present disclosure may be applied to cadmium telluride (Cd-Te) cells, amorphous silicon (a-Si) cells, microcrystalline silicon (Si) cells, crystalline silicon (c-Si) cells, and gallium arsenide (GaAs) multijunction cells.

The multiplexed DLTS and HSCV measurement systems as described herein may be presented (but are not limited to) in software (object code or machine code in a non-transitory computer readable medium), in different stages of compilation as one or more netlists (e.g., SPICE netlists), in a simulation language, in a hardware description language (e.g., Verilog, VHDL), through a set of semiconductor processing masks, and as a partially or fully implemented semiconductor device (e.g., ASIC). Some embodiments may be stand-alone integrated circuits, while other embodiments may be embedded as part of a larger system, module, data acquisition platform, or test and measurement setup (e.g., SULA, SEMETROL).

It will be understood by those skilled in the art that changes in form and details may be made to the above-described embodiments without departing from the scope of the disclosure. Additionally, although various advantages have been described with reference to some embodiments, the scope of the present disclosure should not be limited by reference to such advantages. Rather, the scope of the disclosure should be determined with reference to the appended claims.