阅读说明：本技术 模块化多位加法器及计算系统 (Modular multi-bit adder and computing system ) 是由 陈双文 张楠赓 吴敬杰 马晟厚 刘杰尧 于 2019-09-10 设计创作，主要内容包括：本发明提出了一种模块化多位加法器及计算系统,其中,所述模块化多位加法器包括：最低位输入模块,其输入端口包括最低位的加法输入,输出端口包括最低位的和输出及进位输出；中间位传递模块,其输入端口包括中间位的加法输入及进位输入,输出端口包括中间位的和输出及进位输出；以及最高位输出模块,其输入端口包括最高位的加法输入及进位输入,输出端口包括最高位的和输出。本发明多位加法器及计算系统使用最低位输入模块、中间位传递模块及最高位输出模块组合而成,突破了标准库提供的基本单元所能够达到的极限,进一步优化了加法器面积速度和功耗。(The invention provides a modularized multi-bit adder and a computing system, wherein the modularized multi-bit adder comprises: the input port of the least significant input module comprises an addition input of the least significant, and the output port comprises a sum output and a carry output of the least significant; the input port of the intermediate bit transmission module comprises an addition input and a carry input of the intermediate bit, and the output port of the intermediate bit transmission module comprises a sum output and a carry output of the intermediate bit; and the highest bit output module, its input port includes the addition input and carry input of the highest bit, the output port includes the sum output of the highest bit. The multi-bit adder and the computing system are formed by combining the lowest bit input module, the middle bit transmission module and the highest bit output module, break through the limit which can be reached by the basic unit provided by the standard library, and further optimize the area speed and the power consumption of the adder.)

1. A modular multi-bit adder, comprising:

the input port of the least significant input module comprises an addition input of the least significant, and the output port comprises a sum output and a carry output of the least significant;

the input port of the intermediate bit transmission module comprises an addition input and a carry input of the intermediate bit, and the output port of the intermediate bit transmission module comprises a sum output and a carry output of the intermediate bit; and

and the input port of the highest-order output module comprises the addition input and the carry input of the highest order, and the output port comprises the sum output of the highest order.

2. The modular multi-bit adder of claim 1, wherein the number of the least significant add inputs of the least significant input block, the number of the middle significant add inputs of the middle significant transfer block, and the number of the most significant add inputs of the most significant output block is variable.

3. The modular multi-bit adder of claim 1, wherein the lowest bit addition inputs of the lowest bit input block comprise two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the sum output of the lowest bit input block, the carry output of which is an inverted carry output COX, comprises S0, S1, S2, S3; wherein:

S0＝(A0∧B0)；

S1＝(A1∧B1)∧(((A0&B0)))；

S2＝(A2∧B2)∧(((A1&B1))|((A0&B0)&(A1|B1)))；

S3＝(A3∧B3)∧(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3)))。

4. the modular multi-bit adder of claim 1, wherein the summing inputs of the middle bits of the middle bit transfer module comprise two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the carry input of the intermediate bit transfer module is reverse carry input CIX; the sum output of the middle bits of the middle bit pass module comprises S0, S1, S2, S3; the carry output of the intermediate transfer module is a reverse carry output COX; wherein:

S0＝(A0∧B0)∧((！CIX))；

S1＝(A1∧B1)∧(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2∧B2)∧(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3∧B3)∧(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)(A3|B3)))。

5. the modular multi-bit adder of claim 1, wherein the adding inputs of the most significant bits of the most significant bit output module comprise two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the carry input of the highest bit output module is reverse carry input CIX; the sum output of the most significant bits of the most significant output module comprises S0, S1, S2, S3; wherein:

S0＝(A0∧B0)∧((！CIX))；

S1＝(A1∧B1)∧(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2∧B2)∧(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3∧B3)∧(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))。

6. the modular multi-bit adder according to claim 1, wherein the modular multi-bit adder is a 12-bit adder comprising a 4-bit lowest bit input module, a 4-bit middle bit transfer module, and a 4-bit highest bit output module, all connected in cascade; the carry-in terminal of the lowest order input module is connected with the carry-in terminal of the middle order transmission module, and the carry-in terminal of the middle order transmission module is connected with the carry-in terminal of the highest order output module.

7. The modular multi-bit adder according to claim 1, wherein the modular multi-bit adder is a 16-bit adder comprising a 4-bit lowest bit input module, an 8-bit middle bit transfer module, and a 4-bit highest bit output module, all of which are connected in cascade; the carry-in terminal of the lowest order input module is connected with the carry-in terminal of the middle order transmission module, and the carry-in terminal of the middle order transmission module is connected with the carry-in terminal of the highest order output module.

8. The modular multi-bit adder according to claim 1, wherein the modular multi-bit adder is a 16-bit adder comprising a 4-bit least significant input module, two 4-bit intermediate transfer modules and a 4-bit most significant output module connected in cascade; the carry-in terminal of the lowest bit input module is connected to the carry-in terminal of one of the two middle bit transmission modules, the carry-in terminal of one of the middle bit transmission modules is connected to the carry-in terminal of the other of the two middle bit transmission modules, and the carry-in terminal of the other of the middle bit transmission modules is connected to the carry-in terminal of the highest bit output module.

9. A computing system comprising a modular multi-bit adder according to any one of claims 1 to 8.

Technical Field

The invention belongs to the technical field of calculation, and particularly relates to a modular multi-bit adder and a calculation system.

Background

With the technological revolution and the industrial revolution in the field of global information technology, the development of computing technology is very rapid in recent years, and the adder is the basic guarantee of the development of computing technology.

The adder can be divided into various types according to different algorithms and structures, such as a serial carry adder with a simple algorithm, a carry look-ahead adder (also called a carry look-ahead adder) with higher performance, a carry selection adder, a parallel prefix adder and the like; for the high-performance adder, there are Kogge-Stone adder, Brent-Kung adder, Han-Carlson adder, and Sklansky adder according to the difference of carry chain. The serial carry adder needs one-stage carry, and carry delay is large. The carry look ahead adder can effectively reduce carry delay. To achieve faster speed, better power consumption, and better area, carry look ahead adders are widely used in design.

However, the algorithms of the existing high-performance adder are all modules based on the standard library, the power consumption speed and the area are limited by the basic modules of the standard library, and the gains brought by the algorithms reach the bottleneck due to the use of the standard library.

Disclosure of Invention

Technical problem to be solved

The present invention provides a modular multi-bit adder and a computing system to at least partially solve the above-mentioned technical problems.

(II) technical scheme

According to one aspect of the present invention, there is provided a modular multi-bit adder comprising:

the input port of the least significant input module comprises an addition input of the least significant, and the output port comprises a sum output and a carry output of the least significant;

the input port of the intermediate bit transmission module comprises an addition input and a carry input of the intermediate bit, and the output port of the intermediate bit transmission module comprises a sum output and a carry output of the intermediate bit; and

and the input port of the highest-order output module comprises the addition input and the carry input of the highest order, and the output port comprises the sum output of the highest order.

In some embodiments, the number of the least significant add inputs of the least significant input module, the number of the middle significant add inputs of the middle significant transfer module, and the number of the most significant add inputs of the most significant output module is variable.

In some embodiments, the least significant summing inputs of the least significant input blocks comprise two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the sum output of the lowest bit input block, the carry output of which is an inverted carry output COX, comprises S0, S1, S2, S3; wherein:

S0＝(A0^B0)；

S1＝(A1^B1)^(((A0&B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3)))。

in some embodiments, the additive inputs to the middle bits of the middle bit transfer module include two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the carry input of the intermediate bit transfer module is reverse carry input CIX; the sum output of the middle bits of the middle bit pass module comprises S0, S1, S2, S3; the carry output of the intermediate transfer module is a reverse carry output COX; wherein:

S0＝(A0^B0)^((！CIX))；

S1＝(A1^B1)^(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)(A3|B3)))。

in some embodiments, the summing inputs of the most significant bits of the most significant bit output module comprise two sets of inputs, a0, a1, a2, A3, B0, B1, B2, B3; the carry input of the highest bit output module is reverse carry input CIX; the sum output of the most significant bits of the most significant output module comprises S0, S1, S2, S3; wherein:

S0＝(A0^B0)^((！CIX))；

S1＝(A1^B1)^(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))。

in some embodiments, the modular multi-bit adder is a 12-bit adder comprising a 4-bit lowest bit input module, a 4-bit middle bit transfer module, and a 4-bit highest bit output module connected in cascade; the carry-in terminal of the lowest order input module is connected with the carry-in terminal of the middle order transmission module, and the carry-in terminal of the middle order transmission module is connected with the carry-in terminal of the highest order output module.

In some embodiments, the modular multi-bit adder is a 16-bit adder comprising a 4-bit lowest bit input module, an 8-bit middle bit transfer module, and a 4-bit highest bit output module connected in cascade; the carry-in terminal of the lowest order input module is connected with the carry-in terminal of the middle order transmission module, and the carry-in terminal of the middle order transmission module is connected with the carry-in terminal of the highest order output module.

In some embodiments, the modular multi-bit adder is a 16-bit adder comprising a 4-bit lowest order input module, two 4-bit intermediate order transfer modules, and a 4-bit highest order output module in cascade connection; the carry-in terminal of the lowest bit input module is connected to the carry-in terminal of one of the two middle bit transmission modules, the carry-in terminal of one of the middle bit transmission modules is connected to the carry-in terminal of the other of the two middle bit transmission modules, and the carry-in terminal of the other of the middle bit transmission modules is connected to the carry-in terminal of the highest bit output module.

According to another aspect of the invention, there is provided a computing system comprising a modular multi-bit adder as described.

(III) advantageous effects

It can be seen from the above technical solutions that the modular multi-bit adder and the computing system of the present invention have at least one of the following advantages:

(1) the invention provides a modular multi-bit adder which is formed by combining a lowest bit input module, a middle bit transmission module and a highest bit output module, breaks through the limit which can be reached by a basic unit provided by a standard library, and further optimizes the area speed and the power consumption of the adder.

(2) The invention is based on a modularized multi-bit adder, optimizes the overall performance area and the power consumption of the adder, and has the advantages that under the same speed requirement, the area of the adder is about 10 percent of the benefit, and the power consumption is reduced by about 5 percent.

Drawings

FIG. 1 is a block diagram of a lowest order input module according to the present invention.

Fig. 2 is a schematic structural diagram of a meta transfer module according to the present invention.

FIG. 3 is a diagram illustrating a structure of a highest order output module according to the present invention.

FIG. 4 is a diagram of a 12-bit adder according to an embodiment of the present invention.

FIG. 5 is a diagram of a two 12-bit adder according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

For the sake of understanding, the technical terms related to the present invention will be briefly described below.

A Full Adder (Full-Adder) is a combined circuit that adds two binary numbers by using a gate circuit and obtains a sum, and is called a one-bit Full Adder. A one-bit full adder can process the low-order carry and output the local addition carry. Cascading multiple one-bit full adders can result in a multi-bit full adder.

Carry Look Ahead Adder (Carry Look Ahead) is a parallel Adder designed by improving a common full Adder, and mainly improves the delay generated by mutual Carry when the common full adders are connected in series.

The invention provides a modular multi-bit adder, comprising: the input port of the least significant input module comprises an addition input of the least significant, and the output port comprises a sum output and a carry output of the least significant; the input port of the intermediate bit transmission module comprises an addition input and a carry input of the intermediate bit, and the output port of the intermediate bit transmission module comprises a sum output and a carry output of the intermediate bit; and the highest bit output module, its input port includes the addition input and carry input of the highest bit, the output port includes the sum output of the highest bit. The modular multi-bit adder is formed by combining fully-customized small functional modules, the limit which can be reached by a basic unit provided by a standard library is broken through, and the area speed and the power consumption of the adder are further optimized.

Specifically, the present invention provides three types of modules that respectively implement different functions. The three types of modules are described in detail below using a four bit width as an example.

As shown in fig. 1, the input port of the least significant input module includes an addition input (with a variable number of bits) of the least significant bits, and the output port includes a sum output of the least significant bits and a carry output of one bit. The invention takes four bits as an example: the least significant bit of the adder inputs include a0, a1, a2, A3, B0, B1, B2, B3, a and B represent two sets of inputs of the adder, respectively, the least significant bit of the adder outputs include S0, S1, S2, S3, and the one bit of the carry output is the inverted carry output COX (the inverted signal of the carry output CO used by the present invention for optimizing the circuit). The logic function is as follows:

S0＝(A0^B0)；

S1＝(A1^B1)^(((A0&B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3)))。

as shown in fig. 2, the input port of the intermediate bit transfer module includes an addition input (variable bit number) and a carry input (one bit) of the intermediate bit, and the output port includes a sum output and a carry output of the intermediate bit. The invention takes four bits as an example: the addition input of the intermediate bits comprises A0, A1, A2, A3, B0, B1, B2 and B3, A and B respectively represent two groups of input ends of the adder, the carry input is an inverted carry input end CIX, the sum output bits of the intermediate bits comprise S0, S1, S2 and S3, and the one-bit carry output is an inverted carry output COX. The logic function is as follows:

S0＝(A0^B0)^((！CIX))；

S1＝(A1^B1)^(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))；

COX＝！(((A3&B3))|((A2&B2)&(A3|B3))|((A1&B1)&(A2|B2)&(A3|B3))|((A0&B0)&(A1|B1)&(A2|B2)&(A3|B3))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)(A3|B3)))。

as shown in fig. 3, the most significant output module includes an input port including an addition input (with variable number of bits) and a carry input (with one bit) of the most significant bits, and an output port including a sum of the most significant bits and an output. The invention takes four bits as an example: the addition input of the highest bit comprises A0, A1, A2, A3, B0, B1, B2 and B3, A and B respectively represent two groups of input ends of the adder, the carry input is an inverted carry input end CIX, and the sum output bit of the highest bit comprises S0, S1, S2 and S3. The logic function is as follows:

S0＝(A0^B0)^((！CIX))；

S1＝(A1^B1)^(((A0&B0))|(！CIX&(A0|B0)))；

S2＝(A2^B2)^(((A1&B1))|((A0&B0)&(A1|B1))|(！CIX&(A0|B0)&(A1|B1)))；

S3＝(A3^B3)^(((A2&B2))|((A1&B1)&(A2|B2))|((A0&B0)&(A1|B1)&(A2|B2))|(！CIX&(A0|B0)&(A1|B1)&(A2|B2)))。

the invention utilizes the three types of modules to respectively design and optimize according to the requirements of area, speed and power consumption, and selects the bit number of the required module according to the bit width requirement of the total adder.