阅读说明：本技术 降低非易失性存储器中电荷损失的方法 (The method for reducing loss of charge in nonvolatile memory ) 是由 帕万·辛格 S·谢蒂 J·帕克 于 2018-02-21 设计创作，主要内容包括：一种存储器装置,具有并排设置在衬底上的至少两个非易失性存储器(NVM)单元和在衬底中设置在第一NVM单元和第二NVM单元之间的隔离结构。第一NVM单元和第二NVM单元共享包括连续结构的公共电荷俘获层,并且设置在隔离结构正上方的公共电荷俘获层的部分比设置在第一NVM单元和第二NVM单元内的公共电荷俘获层的部分包括更高的氧和/或氮浓度。(A kind of memory device, has that be arranged side by side on substrate at least two nonvolatile memories (NVM) unit and the isolation structure that is arranged between the first NVM cell and the second NVM cell in the substrate.The shared common electrical charge capture layer including continuous structure of first NVM cell and the second NVM cell, and it includes higher oxygen and/or nitrogen concentration that the part of the common electrical charge capture layer right above isolation structure, which is arranged in, than the part for the common electrical charge capture layer being arranged in the first NVM cell and the second NVM cell.)

1. a kind of memory device, including the first nonvolatile memory (NVM) unit and second on substrate is arranged side by side Nonvolatile memery unit and it is arranged between first NVM cell and second NVM cell in the substrate Isolation structure, wherein the shared common electrical charge including continuous structure of first NVM cell and second NVM cell is captured Layer, and the first part for being provided with the common electrical charge capture layer right above the isolation structure exists compared to setting The second part of the common electrical charge capture layer in first NVM cell and second NVM cell includes higher oxygen Concentration.

2. memory device according to claim 1, wherein the common electrical right above the isolation structure is arranged in The first part of lotus capture layer is compared to the public affairs being arranged in first NVM cell and second NVM cell The second part of electric charge capture layer includes higher nitrogen concentration altogether.

3. memory device according to claim 1, wherein the common electrical charge capture layer includes silicon nitride and nitrogen oxidation At least one of silicon.

4. memory device according to claim 1, wherein the first part of the common electrical charge capture layer includes At least one of silica and oxygen-enriched silicon oxynitride.

5. memory device according to claim 2, wherein the first part of the common electrical charge capture layer includes At least one of rich nitrogen silicon nitride and rich nitrogen silicon oxynitride.

6. memory device according to claim 1, wherein the isolation structure includes shallow trench isolation (STI), wherein The STI is in the extending direction perpendicular to the common electrical charge capture layer and is parallel to first NVM cell and described The side of the channel length of two NVM cells upwardly extends.

7. memory device according to claim 1, wherein the first part of the common electrical charge capture layer includes First width, and the isolation structure includes the second width, wherein second width is greater than first width, and its Described in first part be substantially provided in the isolation structure the second width upright projection in and in the upright projection Middle alignment.

8. memory device according to claim 1, wherein first NVM cell and second NVM cell include Silicon-oxide-nitride-oxide-silicon (SONOS) transistor npn npn.

9. memory device according to claim 1, in which:

The first part of the common electrical charge capture layer right above the isolation structure includes following first chemistry meter Amount:

Silicon within the scope of the approximate concentration of 40-50%,

Oxygen within the scope of the approximate concentration of 5-20%, and

Nitrogen is within the scope of the approximate concentration of 30-45%；And

It is arranged in described second of the common electrical charge capture layer in first NVM cell and second NVM cell Divide includes following second stoichiometry:

Silicon within the scope of the approximate concentration of 50-55%,

Oxygen is 0% approximate concentration, and

Nitrogen is within the scope of the approximate concentration of 45-50%.

10. memory device according to claim 1, in which:

The first part of the common electrical charge capture layer includes first resistor rate value, and the common electrical charge capture layer Each second part includes second resistance rate value, wherein the first resistor rate value is greater than the second resistance rate value.

11. memory device according to claim 2, in which:

The first part of the common electrical charge capture layer right above the isolation structure includes following first chemistry meter Amount:

Silicon within the scope of the approximate concentration of 30-45%,

Oxygen within the scope of the approximate concentration of 5-20%, and

Nitrogen is within the scope of the approximate concentration of 40-50%；And

It is arranged in described second of the common electrical charge capture layer in first NVM cell and second NVM cell Divide includes following second stoichiometry:

Silicon within the scope of the approximate concentration of 50-55%,

The approximate concentration that oxygen is 0%, and

Nitrogen is within the scope of the approximate concentration of 45-50%.

12. memory device according to claim 1, wherein first NVM cell and second NVM cell are total Enjoy the common storage gate electrode layer in same wordline.

13. memory device according to claim 1, wherein in first NVM cell and second NVM cell Each include divide grid memory cell.

14. a kind of nonvolatile memory (NVM) array, comprising:

The multiple memory cells being arranged in rows, wherein each memory cell includes memory transistor, wherein same The shared common electrical charge capture layer including continuous structure and flat shape of capable memory transistor；

In multiple shallow trench isolations (STI) that the side of the row perpendicular to the nvm array upwardly extends, wherein each STI will be same Two adjacent memory transistors of a line separate, and

The part of the common electrical charge capture layer right above each STI is provided with than being arranged in two adjacent memory crystalline substances The part of the common electrical charge capture layer in body pipe includes higher oxygen and nitrogen concentration.

15. nvm array according to claim 14, wherein the multiple memory cell includes dividing grid memory cell.

16. nvm array according to claim 14, wherein the multiple memory cell includes single-transistor or twin crystal Body pipe memory cell.

17. nvm array according to claim 14, wherein the multiple STI is being parallel to the multiple memory cell The side of channel length upwardly extend.

18. nvm array according to claim 14, wherein the common electrical charge capture right above each STI is arranged in The part of layer includes bigger compared to the part for the common electrical charge capture layer being arranged in two adjacent memory transistors Resistivity.

19. a kind of memory device, including first point of grid memory cell and second point of grid storage on substrate is arranged side by side Device unit and the shallow trench being arranged between first point of grid unit and second point of grid unit in the substrate every From (STI), wherein first point of grid unit and second point of grid unit share the common electrical charge capture layer of flat shape, Described in the first part of common electrical charge capture layer be arranged right above the STI, and the of the common electrical charge capture layer Two parts are arranged in right above the channel of first point of grid memory cell and second point of grid memory cell, wherein institute It states first part and the continuous structure of the common electrical charge capture layer is integrally formed in the second part, and is wherein described public The first part of electric charge capture layer includes higher nitrogen concentration than the second part.

20. memory device according to claim 19, wherein the first part of the common electrical charge capture layer wraps The first width is included, and the STI includes the second width, wherein second width is greater than first width, and wherein The first part is basically set in the upright projection of the second width of the STI, and right in the upright projection Together.

21. memory device according to claim 19, in which:

The first part of the common electrical charge capture layer right above the STI includes following first stoichiometry:

Silicon within the scope of the approximate concentration of 43-50%,

The approximate concentration that oxygen is 0%, and

Nitrogen is within the scope of the approximate concentration of 50-57%；And

It is arranged in described the second of first point of grid unit and the common electrical charge capture layer in second point of grid unit Part includes following second stoichiometry:

Silicon within the scope of the approximate concentration of 50-55%,

The approximate concentration that oxygen is 0%, and

Nitrogen is within the scope of the approximate concentration of 45-50%.

22. memory device according to claim 19, wherein first part's phase of the common electrical charge capture layer Than including higher resistivity in the second part.

Technical field

The disclosure relates generally to a kind of nonvolatile memory (NVM) equipment, more particularly, to reduction and minimize The method and embodiment of loss of charge in trapped-charge memory.

Background

Even if the memory for still retaining its data when operation power is unavailable is classified as nonvolatile memory.It is non-easy Lose property memory (NVM) example have nvSRAM, ferroelectric RAM (F-RAM), programmable read only memory (PROM), it is erasable can Program read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and trapped-charge memory and/or floating Flash memory in grating.Some memory arrays utilize the transistor and gate structure that may include electric charge capture layer.Electric charge capture layer can be by It is programmed for storing data based on being applied to memory array or being stored by the voltage of array received.This kind of memory can be used for The application of critical data must be stored after power-off or during operation when power interruptions.The manufacture of two dimension or planar flash memory equipment has been dropped To 10nm photoetching, and as each NV memory component becomes smaller and smaller and is physically increasingly closer to each other, scale Reduction have begun and lead to the problem of.In these NV memory components, their charge trapping gate since scale is smaller and Keep the charge of much less.As a result, any small defect in manufacturing process all may cause and be difficult to differentiate between NV memory component Logic/memory state, this mistake that may cause logic state are read.In addition, coordination electrode becomes so small and such Closely separate so that their influence, such as the influence in offset gate, may be diffused into more than one memory cell or On string, this may cause the unreliable of data and reads and writees.