阅读说明：本技术 信号生成电路及其方法、数字时间转换电路及其方法 (Signal generating circuit and its method, digit time conversion circuit and its method ) 是由 魏祥野 修黎明 于 2019-08-30 设计创作，主要内容包括：一种信号生成电路、信号生成方法、数字时间转换电路和数字时间转换方法。信号生成电路包括：第一生成电路,被配置为基于第一频率控制字和基准时间单位生成第一输出信号；第二生成电路,被配置为基于第二频率控制字和基准时间单位生成第二输出信号。第一频率控制字包括第一整数部分和第一小数部分,第二频率控制字包括第二整数部分和第二小数部分,第一整数部分等于第二整数部分,第一小数部分不为零,第二小数部分为零,第一输出信号的周期与第二输出信号的周期不相等。(A kind of signal generating circuit, signal creating method, digit time conversion circuit and digit time conversion method.Signal generating circuit includes: the first generative circuit, is configured as generating the first output signal based on first frequency control word and fiducial time unit；Second generative circuit is configured as generating the second output signal based on second frequency control word and fiducial time unit.First frequency control word includes the first integer part and the first fractional part, second frequency control word includes the second integer part and the second fractional part, first integer part is equal to the second integer part, first fractional part is not zero, second fractional part is zero, and the period of the first output signal and the period of the second output signal are unequal.)

1. a kind of signal generating circuit, comprising:

First generative circuit is configured as generating the first output signal based on first frequency control word and fiducial time unit；

Second generative circuit is configured as generating the second output letter based on second frequency control word and the fiducial time unit Number,

Wherein, the first frequency control word includes the first integer part and the first fractional part, the second frequency control word Including the second integer part and the second fractional part, first integer part be equal to second integer part, described first Fractional part is not zero, and second fractional part is zero, the period of first output signal and second output signal Period it is unequal.

2. signal generating circuit as described in claim 1, wherein the period of first output signal and second output Periodic inequality between the period of signal is related with the fiducial time unit and first fractional part.

3. signal generating circuit as described in claim 1, wherein first generative circuit includes the first digital control oscillation Device sub-circuit and the first conversion sub-circuit, the first numerically-controlled oscillator sub-circuit are configured as based on the first frequency Control word and the fiducial time unit generate first M signal, and first conversion sub-circuit is configured as described first M signal is converted to first output signal,

Wherein, second generative circuit includes the second numerically-controlled oscillator sub-circuit, second numerically-controlled oscillator Sub-circuit is configured as generating second output signal based on the second frequency control word and the fiducial time unit,

Wherein, the first M signal was generated in an interleaved manner by the first primitive period and the second primitive period, institute The average period for stating first M signal is indicated by following formula:

T_h=(1-r_h)·T_A+r_h·T_B,

Wherein, T_hIndicate the average period of the first M signal, r_hIndicate first fractional part, T_AIndicate described One primitive period, T_BIndicate second primitive period；

The period of second output signal is indicated by following formula:

T_l=T_A,

Wherein, T_lIndicate the period of second output signal.

4. signal generating circuit as claimed in claim 3, wherein first conversion sub-circuit is configured as filtering out described High fdrequency component in one M signal is to obtain first output signal.

5. signal generating circuit as claimed in claim 3, wherein first conversion sub-circuit includes the second phase discriminator, the Second Ring Road filter, the second voltage controlled oscillator and the second frequency divider,

Second voltage controlled oscillator is configured as generating the oscillator signal with the second predetermined oscillation frequency according to control variable,

Second frequency divider is configured as dividing to obtain fractional frequency signal the oscillator signal,

Second phase discriminator is configured as between the frequency of first M signal described in comparison and the frequency of the fractional frequency signal Difference, to export Differential variable,

Second loop filter is configured as filtering out the high fdrequency component in the Differential variable, to generate control described first The control variable of voltage controlled oscillator,

Second voltage controlled oscillator is additionally configured to the frequency of frequency and the fractional frequency signal when the first M signal When equal, generate and export first output signal.

6. signal generating circuit as claimed in claim 5, wherein the parameter of second loop filter is according to described first The least significant bit of the frequency of M signal and first fractional part determines.

7. signal generating circuit as claimed in claim 6, wherein the parameter of second loop filter includes described second The bandwidth of the bandwidth of loop filter, second loop filter determines according to the following formula:

Bwlp≤f_h·r_LSB,

Wherein, Bwlp indicates the bandwidth of second loop filter, f_hIndicate the average frequency of the first M signal, and And r_LSBIndicate the corresponding value of least significant bit of first fractional part.

8. signal generating circuit as claimed in claim 3, wherein the first numerically-controlled oscillator sub-circuit and described Two numerically-controlled oscillator sub-circuits include the direct periods synthesizer device of time average frequency.

9. it further include fiducial time unit generative circuit such as signal generating circuit of any of claims 1-8, it is described Fiducial time unit generative circuit is configurable to generate the fiducial time unit.

10. signal generating circuit as claimed in claim 9, wherein the fiducial time unit generative circuit includes comprising more The counter of a d type flip flop.

11. signal generating circuit as claimed in claim 9, wherein the fiducial time unit generative circuit includes:

First voltage controlled oscillator is configured as with the first predetermined oscillation hunting of frequency；

Phase-locked loop circuit is configured as the output frequency of first voltage controlled oscillator being locked as reference output frequency； With

K output end is configured as the output signal at K uniform phase interval of output, wherein and K is the positive integer greater than 1,

Wherein, the reference output frequency is expressed as f_Δ, the fiducial time unit is any the two of the K output end output Time span between a adjacent output signal, the fiducial time unit are expressed as Δ, and Δ=1/ (Kf Δ).

12. such as signal generating circuit of any of claims 1-8, further includes: control circuit,

Wherein, the control circuit is configured to determine that the first frequency control word and the second frequency control word, and defeated The first frequency control word exports the second frequency control word to the second generation electricity to first generative circuit out Road.

13. a kind of digit time conversion circuit, comprising:

Such as signal generating circuit of any of claims 1-12；And

Time generative circuit is configured as receiving digital signal, first output signal and second output signal；With And it is generated based on the digital signal, first output signal and second output signal corresponding with the digital signal First time pulse signal or the second time pulse signal,

Wherein, the first minimum interval between the rising edge and failing edge of the first time pulse signal and the benchmark Chronomere is related with first fractional part；Alternatively, second time pulse signal include the first subpulse signal and Second subpulse signal, between the rising edge of the first subpulse signal and the rising edge of the second subpulse signal second most Small time interval is related with the fiducial time unit and first fractional part.

14. digit time conversion circuit as claimed in claim 13, further includes phase detector circuit,

Wherein, the phase detector circuit is configured to determine that the phase of first output signal and second output signal is closed System indicates the phase and the indication signal of the phase alignment of second output signal of first output signal to generate,

The time generative circuit is configured as based on the digital signal, first output signal, the second output letter Number and the indication signal generate the first time pulse signal or second time pulse signal.

15. digit time conversion circuit as claimed in claim 14, wherein first generative circuit includes being configured as base The first numerically-controlled oscillator of first M signal is generated in the first frequency control word and the fiducial time unit It circuit and is configured as being converted to the first M signal into the first conversion sub-circuit of first output signal, described the Two generative circuits include being configured as generating the second output letter based on the second frequency control word and the fiducial time unit Number the second numerically-controlled oscillator sub-circuit,

First generative circuit is additionally configured to output and the first M signal when generating the first M signal The corresponding first rising edge control word of rising edge, the first failing edge corresponding with the failing edge of the first M signal Control word and the first fractional frequency control word corresponding with the switching of the period of the first M signal,

Second generative circuit is additionally configured to output and second output signal when generating second output signal The corresponding second rising edge control word of rising edge and under the failing edge corresponding second of second output signal It drops along control word, and

The phase detector circuit is configured as: based on the first rising edge control word, the second rising edge control word, described First failing edge control word, the second failing edge control word and the first fractional frequency control word generate the instruction letter Number.

16. digit time conversion circuit as claimed in claim 15, wherein the phase detector circuit is configured as: described First rising edge control word is equal to the second rising edge control word, the first failing edge control word is equal to second decline Under control word and the null situation of the first fractional frequency control word, the indication signal is generated.

17. the digit time conversion circuit as described in any one of claim 13-16, wherein between first minimum time Every or second minimum interval indicate are as follows:

DeltaT=nt_R,

Wherein, DeltaT indicates that first minimum interval or second minimum interval, n indicate the number letter Number bit wide, t_RIndicate the periodic inequality between the period of first output signal and the period of second output signal, and t_R It indicates are as follows:

t_R=r_hΔ,

Wherein, r_hIndicate first fractional part, Δ indicates the fiducial time unit.

18. a kind of signal creating method, comprising:

The first output signal is generated based on first frequency control word and fiducial time unit；And

The second output signal is generated based on second frequency control word and the fiducial time unit,

Wherein, the first frequency control word includes the first integer part and the first fractional part, the second frequency control word Including the second integer part and the second fractional part, first integer part be equal to second integer part, described first Fractional part is not zero, and second fractional part is zero, the period of first output signal and second output signal Period it is unequal.

19. signal creating method as claimed in claim 18, wherein period of first output signal and described second defeated The periodic inequality between the period of signal is related with the fiducial time unit and first fractional part out.

20. the signal creating method as described in claim 18 or 19, wherein it is described be based on first frequency control word and benchmark when Between unit generate the first output signal, comprising:

First M signal is generated based on the first frequency control word and the fiducial time unit；And

The first M signal is converted into first output signal,

Wherein, the first M signal was generated in an interleaved manner by the first primitive period and the second primitive period, institute The average period for stating first M signal is indicated by following formula:

T_h=(1-r_h)·T_A+r_h·T_B,

Wherein, T_hIndicate the average period of the first M signal, r_hIndicate first fractional part, T_AIndicate described One primitive period, T_BIndicate second primitive period.

21. signal creating method as claimed in claim 20, wherein it is defeated that the first M signal is converted to described first Signal includes: out

The high fdrequency component in the first M signal is filtered out to believe so that the first M signal is converted to first output Number.

22. a kind of digit time conversion method applied to the described in any item digit time conversion circuits of claim 13-17 Include:

Receive the digital signal, first output signal and second output signal；And

It is generated and the digital signal pair based on the digital signal, first output signal and second output signal The first time pulse signal or the second time pulse signal answered.

23. digit time conversion method as claimed in claim 22, further includes: determine first output signal and described The phase relation of two output signals is to generate the phase of the phase Yu second output signal that indicate first output signal The indication signal of alignment,

Wherein, it is generated and the number based on the digital signal, first output signal and second output signal The corresponding first time pulse signal of signal or the second time pulse signal include: based on the digital signal, described first defeated Signal, second output signal and the indication signal generate the first time pulse signal or second time out Pulse signal.

24. digit time conversion method as claimed in claim 23, wherein

Generating the first output signal based on first frequency control word and fiducial time unit includes: to be controlled based on the first frequency Word and the fiducial time unit generate first M signal and the first M signal are converted to first output Signal,

The digit time conversion method further include:

The first rising edge corresponding with the rising edge of the first M signal is obtained when generating the first M signal Control word, the first failing edge control word corresponding with the failing edge of the first M signal and with described first among The period of signal switches corresponding first fractional frequency control word；And

The second rising edge corresponding with the rising edge of second output signal is obtained when generating second output signal Control word and the second failing edge control word corresponding with the failing edge of second output signal,

Wherein it is determined that the phase relation of first output signal and second output signal is to generate the indication signal packet It includes: based on the first rising edge control word, the second rising edge control word, the first failing edge control word, described the Two failing edge control words and the first fractional frequency control word generate the indication signal.

25. digit time conversion method as claimed in claim 24, wherein based on the first rising edge control word, described Second rising edge control word, the first failing edge control word, the second failing edge control word and first fractional frequency It includes: to be equal to the second rising edge control word, institute in the first rising edge control word that control word, which generates the indication signal, It is null equal to the second failing edge control word and the first fractional frequency control word to state the first failing edge control word In the case of, generate the indication signal.

Technical field

Embodiment of the disclosure is related to a kind of signal generating circuit, signal creating method, digit time conversion circuit sum number Word time conversion method.

Background technique

With the fast development of Internet of Things and universal, such as sensor (sensor), MEMS (Micro- Electro-Mechanical System, MEMS) and integrated circuit (Integrated Circuit, IC) etc. Department of Electronics System using more and more extensive.

The time of chip in electronic system can refer to clock signal period.Currently, clock signal period is generally nanosecond Magnitude.For example, if a clock signal period is 20 nanoseconds (ns), according to the precision for the counter that the clock signal obtains It can be 20ns, that is, the resolution ratio of counter cannot be below 20ns.However, this resolution ratio or precision are in scientific research, military affairs It is difficult to meet application request using fields such as, consumer electronics.In addition, due to the time cycle it is small to a certain extent (for example, Picosecond magnitude) when, the parameters such as shake, phase noise of signal will be difficult to control, to can not cannot be guaranteed the integrality of signal. Therefore, it is difficult to further increase frequency and reduce the time cycle.

Summary of the invention

An at least embodiment for the disclosure provides a kind of signal generating circuit.Signal generating circuit includes: the first generation electricity Road is configured as generating the first output signal based on first frequency control word and fiducial time unit；Second generative circuit is matched It is set to and the second output signal is generated based on second frequency control word and fiducial time unit.First frequency control word includes first whole Number part and the first fractional part, second frequency control word include the second integer part and the second fractional part, the first integer portion Point it is equal to the second integer part, the first fractional part is not zero, and the second fractional part is zero, the period of the first output signal and the The period of two output signals is unequal.

For example, in some instances, the periodic inequality between the period of the first output signal and the period of the second output signal It is related with fiducial time unit and the first fractional part.

For example, in some instances, the first generative circuit includes the first numerically-controlled oscillator sub-circuit and the first conversion Sub-circuit, the first numerically-controlled oscillator sub-circuit are configured as generating the based on first frequency control word and fiducial time unit One M signal, the first conversion sub-circuit are configured as being converted to first M signal into the first output signal.Second generates electricity Road includes the second numerically-controlled oscillator sub-circuit, and the second numerically-controlled oscillator sub-circuit is configured as based on second frequency control Word processed and fiducial time unit generate the second output signal.First M signal is by the first primitive period and the second original week What the phase generated in an interleaved manner, the average period of first M signal is indicated by following formula:

T_h=(1-r_h)·T_A+r_h·T_B,

Wherein, T_hIndicate the average period of first M signal, r_hIndicate the first fractional part, T_AIndicated for the first original week Phase, T_BIndicated for the second primitive period.

For example, in some instances, the first conversion sub-circuit is configured as filtering out the high fdrequency component in first M signal To obtain the first output signal.

For example, in some instances, the first conversion sub-circuit includes the second phase discriminator, the second loop filter, the second pressure Control oscillator and the second frequency divider.Second voltage controlled oscillator, which is configured as being generated according to control variable, has the second predetermined oscillation frequency The oscillator signal of rate.Second frequency divider is configured as dividing to obtain fractional frequency signal oscillator signal.Second phase discriminator quilt It is configured to compare the difference between the frequency of first M signal and the frequency of fractional frequency signal, to export Differential variable.Second ring Path filter is configured as filtering out the high fdrequency component in Differential variable, to generate the control variable of the first voltage controlled oscillator of control. Second voltage controlled oscillator is additionally configured to generate and export when the frequency of first M signal is equal with the frequency of fractional frequency signal First output signal.

For example, in some instances, the parameter of the second loop filter is small according to the frequency of first M signal and first The least significant bit of number part determines.

For example, in some instances, the parameter of the second loop filter includes the bandwidth of the second loop filter, the second ring The bandwidth of path filter determines according to the following formula:

Bwlp≤f_h·r_LSB,

Wherein, Bwlp indicates the bandwidth of the second loop filter, f_hIndicate the average frequency of first M signal, and r_LSBIndicate the corresponding value of the least significant bit of the first fractional part.

For example, in some instances, the first numerically-controlled oscillator sub-circuit and the second numerically-controlled oscillator sub-circuit Including the direct periods synthesizer device of time average frequency.

For example, in some instances, signal generating circuit further includes fiducial time unit generative circuit, fiducial time unit Generative circuit is configurable to generate fiducial time unit.

For example, in some instances, fiducial time unit generative circuit includes multiple d type flip flops.

For example, in some instances, fiducial time unit generative circuit includes: the first voltage controlled oscillator, be configured as with First predetermined oscillation hunting of frequency；Phase-locked loop circuit is configured as the output frequency of the first voltage controlled oscillator being locked as Reference output frequency；With K output end, it is configured as the output signal at K uniform phase interval of output, wherein K is greater than 1 Positive integer.Reference output frequency is expressed as f_Δ, fiducial time unit is that any two of the K output end output are adjacent Time span between output signal, fiducial time unit are expressed as Δ, and Δ=1/ (Kf_Δ)。

For example, in some instances, signal generating circuit further include: control circuit.Control circuit is configured to determine that One frequency control word and second frequency control word, and first frequency control word is exported to the first generative circuit, export second frequency Control word is to the second generative circuit.

An at least embodiment for the disclosure also provides a kind of digit time conversion circuit.Digit time conversion circuit includes: Any one in signal generating circuit described above；And time generative circuit, it is configured as receiving digital signal, first Output signal and the second output signal；And based on digital signal, the first output signal and the second output signal generate with The corresponding first time pulse signal of digital signal or the second time pulse signal.The rising edge of first time pulse signal is under First minimum interval of the drop between is related with fiducial time unit and the first fractional part；Alternatively, the second time pulse Signal includes the first subpulse signal and the second subpulse signal, the rising edge of the first subpulse signal and the second subpulse signal Rising edge between the second minimum interval it is related with fiducial time unit and the first fractional part.

For example, in some instances, digit time conversion circuit further includes phase detector circuit.Phase detector circuit is configured as The phase relation of the first output signal and the second output signal is determined to generate the phase of the first output signal of instruction and second defeated The indication signal of the phase alignment of signal out.Time generative circuit is configured as based on digital signal, the first output signal, second Output signal and indication signal generate first time pulse signal or the second time pulse signal.

For example, in some instances, the first generative circuit includes when being configured as based on first frequency control word and benchmark Between unit generate first M signal the first numerically-controlled oscillator sub-circuit and be configured as converting first M signal For the first conversion sub-circuit of the first output signal, the second generative circuit includes being configured as based on second frequency control word and base Quasi- chronomere generates the second numerically-controlled oscillator sub-circuit of the second output signal.First generative circuit is additionally configured to When generating first M signal in output the first rising edge control word corresponding with the rising edge of first M signal and first Between signal the corresponding first failing edge control word of failing edge and corresponding with the switching of the period of first M signal One fractional frequency control word.Second generative circuit is additionally configured to output and the second output signal when generating the second output signal The corresponding second rising edge control word of rising edge and the second failing edge corresponding with the failing edge of the second output signal Control word.Phase detector circuit is configured as: being based on the first rising edge control word, the second rising edge control word, the first failing edge control Word, the second failing edge control word and the first fractional frequency control word processed generate indication signal.

For example, in some instances, phase detector circuit is configured as: being equal to the second rising edge in the first rising edge control word Control word, the first failing edge control word are equal to the second failing edge control word and the first null feelings of fractional frequency control word Under condition, indication signal is generated.

For example, in some instances, the first minimum interval or the second minimum interval indicate are as follows:

DeltaT=nt_R,

Wherein, DeltaT indicates that the first minimum interval or the second minimum interval, n indicate the position of digital signal Width, t_RIndicate the periodic inequality between the period of the first output signal and the period of the second output signal, and t_RIt indicates are as follows:

t_R=r_hΔ,

Wherein, r_hIndicate the first fractional part, Δ indicates fiducial time unit.

An at least embodiment for the disclosure also provides a kind of signal creating method.Signal creating method includes: based on first Frequency control word and fiducial time unit generate the first output signal；And it is based on second frequency control word and fiducial time unit Generate the second output signal.First frequency control word includes the first integer part and the first fractional part, second frequency control word Including the second integer part and the second fractional part, the first integer part is equal to the second integer part, and the first fractional part is not Zero, the second fractional part is zero, and the period of the first output signal and the period of the second output signal are unequal.

For example, in some instances, the periodic inequality between the period of the first output signal and the period of the second output signal It is related with fiducial time unit and the first fractional part.

For example, in some instances, generating the first output signal, packet based on first frequency control word and fiducial time unit It includes: first M signal is generated based on first frequency control word and fiducial time unit；And first M signal is converted to First output signal.First M signal was generated in an interleaved manner by the first primitive period and the second primitive period, the The average period of one M signal is indicated by following formula:

T_h=(1-r_h)·T_A+r_h·T_B,

Wherein, T_hIndicate the average period of first M signal, r_hIndicate the first fractional part, T_AIndicated for the first original week Phase, T_BIndicated for the second primitive period.

For example, in some instances, it includes: to filter out to believe among first that first M signal, which is converted to the first output signal, High fdrequency component in number is to be converted to the first output signal for first M signal.

An at least embodiment for the disclosure also provides a kind of digit time applied to above-mentioned digit time conversion circuit Conversion method.Digit time conversion method includes: to receive digital signal, the first output signal and the second output signal；And First time pulse signal corresponding with digital signal is generated based on digital signal, the first output signal and the second output signal Or second time pulse signal.

For example, in some instances, digit time conversion method further include: determine the first output signal and the second output letter Number phase relation with generate instruction the first output signal phase and the second output signal phase alignment indication signal.Base In digital signal, the first output signal and the second output signal generate first time pulse signal corresponding with digital signal or Second time pulse signal includes: to generate the based on digital signal, the first output signal, the second output signal and indication signal One time pulse signal or the second time pulse signal.

For example, in some instances, generating the first output signal packet based on first frequency control word and fiducial time unit It includes: first M signal being generated based on first frequency control word and fiducial time unit and is converted to first M signal First output signal.Digit time conversion method further include: obtained when generating first M signal and first M signal The corresponding first rising edge control word of rising edge, the first failing edge corresponding with the failing edge of first M signal control Word and the first fractional frequency control word corresponding with the switching of the period of first M signal；And it is exported when generating second Obtained when signal corresponding with the rising edge of the second output signal the second rising edge control word and with the second output signal The corresponding second failing edge control word of failing edge.Determine the phase relation of the first output signal and the second output signal to generate Indication signal includes: based on the first rising edge control word, the second rising edge control word, the first failing edge control word, the second decline Indication signal is generated along control word and the first fractional frequency control word.

For example, in some instances, being based on the first rising edge control word, the second rising edge control word, the first failing edge control It includes: in the first rising edge control word that word, the second failing edge control word and the first fractional frequency control word processed, which generate indication signal, It is equal to the second failing edge control word and the first fractional frequency control equal to the second rising edge control word, the first failing edge control word In the null situation of word processed, indication signal is generated.

Detailed description of the invention

In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, letter will be made to the attached drawing of the embodiment of the present disclosure below Singly introduce.It is apparent that drawings discussed below merely relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.

Figure 1A shows the schematic block diagram of the signal generating circuit according to some embodiments of the present disclosure；

Figure 1B shows the schematic block diagram of the signal generating circuit according to some embodiments of the present disclosure；

Fig. 2 shows wrapping in first frequency control word and second frequency control word according to some embodiments of the present disclosure Include the block diagram of the signal generating circuit in the case where corresponding fractional part；

Fig. 3 shows the schematic illustration of the time average frequency according to some embodiments of the present disclosure；

Fig. 4 is shown according to some embodiments of the present disclosure in r_h=0.5 and r_lIn the case where=0.25 first in Between signal waveform and second M signal waveform figure；

Fig. 5 is shown according to some embodiments of the present disclosure in r_hThe wave of first M signal in the case where=0.5 The figure of the waveform of shape and the first output signal；

Fig. 6 shows the schematic diagram of the first output signal and the second output signal according to some embodiments of the present disclosure；

Fig. 7 shows reference signal and the fiducial time at the K uniform phase interval according to some embodiments of the present disclosure The schematic diagram of unit；

Fig. 8 shows a kind of schematic diagram of fiducial time unit generative circuit according to some embodiments of the present disclosure；

Fig. 9 shows the schematic diagram of another fiducial time unit generative circuit according to some embodiments of the present disclosure；

Figure 10 is shown according to some embodiments of the present disclosure based on the direct periods synthesizer circuit frame of time average frequency The circuit diagram of the direct periods synthesizer device of the time average frequency of structure；

Figure 11 shows the circuit diagram of the phaselocked loop according to some embodiments of the present disclosure；

Figure 12 shows the letter in the case where second frequency control word is integer according to some embodiments of the present disclosure The block diagram of number generative circuit；

Figure 13 A shows the block diagram of the digit time conversion circuit according to some embodiments of the present disclosure；

Figure 13 B shows the schematic diagram of the first time pulse signal according to some embodiments of the present disclosure；

Figure 13 C shows the schematic diagram of the second time pulse signal according to some embodiments of the present disclosure；

Figure 14 A shows the block diagram of the digit time conversion circuit according to some embodiments of the present disclosure；

Figure 14 B shows a kind of example of the phase detector circuit in Figure 14 A；

Figure 14 C shows another example of the phase detector circuit in Figure 14 A；

Figure 15 A shows the block diagram of the digit time conversion circuit according to some embodiments of the present disclosure；

Figure 15 B shows a kind of example of the phase detector circuit in Figure 15 A；

Figure 15 C shows another example of the phase detector circuit in Figure 15 A；

Figure 16 shows the flow chart of the signal creating method according to some embodiments of the present disclosure；And

Figure 17 shows the flow charts according to the digit time conversion methods of some embodiments of the present disclosure.

Specific embodiment

To keep the purposes, technical schemes and advantages of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure Attached drawing, the technical solution of the embodiment of the present disclosure is clearly and completely described.Obviously, described embodiment is this public affairs The a part of the embodiment opened, instead of all the embodiments.Based on described embodiment of the disclosure, ordinary skill Personnel's every other embodiment obtained under the premise of being not necessarily to creative work, belongs to the range of disclosure protection.

Here the scope of the present disclosure is not intended to limit and/or limited for describing implementation of the disclosure the term of example.Example Such as, unless otherwise defined, the technical term or scientific term that the disclosure uses, which are should be in fields of the present invention, has one As technical ability the ordinary meaning that is understood of personage.It should be understood that used in the disclosure " first ", " second " and similar Word be not offered as any sequence, quantity or importance, and be used only to distinguish different component parts.Unless context Clearly dictate otherwise, otherwise singular "one", the similar word such as " one " or "the" do not indicate that quantity limits yet, but Indicate that there are at least one.

It will be further appreciated that the similar word such as term " includes " or "comprising" means the member for occurring before the word Part or object, which are covered, appears in the element of the word presented hereinafter perhaps object and its equivalent and be not excluded for other elements or object Part." connection " either the similar word such as " coupling " is not limited to physics or mechanical connection, but may include electricity Property connection, it is either direct or indirectly."upper", "lower", "left", "right" etc. are only used for indicating relative positional relationship, After the absolute position for being described object changes, then the relative positional relationship may also correspondingly change.

Digit time conversion can refer to that the digital information by user's input is converted to the pulse signal of corresponding time span.Example Such as, if input Integer n, available time span is nT_RPulse, wherein T_RIt is the minimum resolution of pulse.Example Such as, number can be realized by the various methods of traditional delay method, variable slope mise-a-la-masse method, vernier method and edge interpolation method etc. Word time conversion.Traditional delay method can be realized by buffer.Since buffer is larger by such environmental effects, signal stabilization Property is bad, therefore traditional delay method cannot be guaranteed the accuracy and precision of time.The linearity of variable slope mise-a-la-masse method is poor, Wu Fabao Demonstrate,prove the accuracy of time.Vernier method is difficult to discriminate between the phase of pulse signal, while with the increase of test scope, required logic Device is in geometric growth.Edge interpolation method needs to be inserted into resistance in circuit, increases power consumption and area.

A kind of signal generating circuit, signal creating method, digit time conversion electricity are provided in accordance with an embodiment of the present disclosure Road and digit time conversion method.Various circuits according to an embodiment of the present disclosure and method (for example, signal generating circuit, Signal creating method, digit time conversion circuit and digit time conversion method) it realizes simply, while can reach high Time accuracy and accuracy.For example, by signal generating circuit according to an embodiment of the present disclosure or signal creating method, base The pulse signal of cycle differentiation minimum (for example, picosecond magnitude) can be obtained in the method for time average frequency.For example, passing through root According to the digit time conversion circuit or digit time conversion method of embodiment of the disclosure, it is enough temporal resolution can be obtained It is small, and the time interval pulse with superregulated property and accuracy.

Various circuits according to an embodiment of the present disclosure and method can be used for such as super large-scale integration function survey Try (VLSI Functional Tester), time generator (Timing Generator), chip pulse parameter test (IC Pulse Parametric Tester), phaselocked loop (PLL), sampling oscilloscope (Sampling Oscilloscope), automatic survey Try equipment (Automatic Test Equipment, ATE), direct digital synthesis technique (Direct Digital Frequency Synthesizer, DDFS), polar transmitter (Polar Transmitter), radar (Radar) etc. it is various Field.

In the following, embodiment of the disclosure will be described in detail with reference made to the accompanying drawings.It should be noted that identical in different attached drawings Appended drawing reference will be used to refer to the identical element that has described.

An at least embodiment for the disclosure provides a kind of signal generating circuit.Figure 1A to Figure 1B is shown according to the disclosure The block diagram of the signal generating circuit of some embodiments.

With reference to Figure 1A, the signal generating circuit 10 according to an at least embodiment for the disclosure may include the first generative circuit 101 and second generative circuit 102.First generative circuit 101 can be configured as based on first frequency control word F_hWhen with benchmark Between units of delta generate the first output signal S_h.Second generative circuit 102 can be configured as based on second frequency control word F_lAnd this Fiducial time units of delta generates the second output signal S_l.For example, the first output signal S_hPeriod and the second output signal S_lWeek Phase is unequal.

For example, the first output signal S_hPeriod and the second output signal S_lPeriod between time difference indicate time point Resolution, in some embodiments of the present disclosure, which can achieve femtosecond magnitude.

In some embodiments, the first output signal S_hPeriod and the second output signal S_lThe difference in period can be with Fiducial time units of delta, first frequency control word F_hWith second frequency control word F_lIt is related.For example, the first output signal S_hWeek Phase and the second output signal S_lPeriod between periodic inequality and fiducial time units of delta and the first fractional part and second it is small Decimal difference between number part is related.

In some embodiments, fiducial time units of delta can be any of the reference signal at K uniform phase interval Time span (for example, phase difference) between two adjacent reference signals, wherein K is the positive integer greater than 1.Therefore, benchmark Chronomere's Δ can correspond to the reference signal at K uniform phase interval.For example, the embodiment of the present disclosure some figures (for example, Shown in Figure 1A) by fiducial time units of delta be input to the first generative circuit 101 and the second generative circuit 102 can indicate by The reference signal at K uniform phase interval corresponding with fiducial time units of delta is input to the first generative circuit 101 and second Generative circuit 102.

In some embodiments, as shown in Figure 1B, signal generating circuit 10 can also include that fiducial time unit generates Circuit 103.For example, fiducial time unit generative circuit 103 can be configured as the benchmark letter for generating K uniform phase interval Number, wherein the time span between the adjacent reference signal of any two of the reference signal at K uniform phase interval (for example, Phase difference) it is benchmark chronomere Δ.For example, fiducial time unit generative circuit 103 can be by twisted ring counter (that is, about The inferior counter of writing brush (JohnsonCounter)) Lai Shixian.For example, fiducial time unit generative circuit 103 can be pressed by multistage Oscillator is controlled to realize.Fiducial time unit generative circuit according to an embodiment of the present disclosure will be described with reference to Fig. 8 and Fig. 9 later Some examples of 103 configuration.

In some embodiments, first frequency control word F_hIt may include the first integer part and the first fractional part, Second frequency control word F_lIt may include the second integer part and the second fractional part, the first integer part and the second integer part It is identical, and the first fractional part and the second fractional part are unequal.For example, first frequency control word F_hIt can be 8.25, and And second frequency control word F_lIt can be 8.125, i.e. the first integer part is 8, and the first fractional part is 0.25, the second integer portion It is divided into 8, the second fractional part is 0.125.

In some embodiments, first frequency control word F_hWith second frequency control word F_lOne of can be integer, That is the first fractional part or the second fractional part can be 0.For example, in some instances, the first fractional part is not Zero, the second fractional part is zero, for example, first frequency control word F_hIt can be 8.125, and second frequency control word F_lIt can be with It is 8, at this point, the first integer part is 8, the first fractional part is 0.125, and the second integer part is 8, and the second fractional part is 0.

In some embodiments, first frequency control word F_hWith second frequency control word F_lIt both is integer.Namely It says, the first fractional part and the second fractional part can all be 0.For example, first frequency control word F_hIt can be 9, and second Frequency control word F_lIt can be 8, at this point, the first integer part is 9, the first fractional part is 0, and the second integer part is 8, second Fractional part is 0.In this case, the first output signal S_hPeriod and the second output signal S_lPeriod between period Poor and between fiducial time units of delta and the first integer part and the second integer part difference is related.

In embodiment of the disclosure, frequency control word is (for example, first frequency control word F_hOr second frequency control word F_l) Fractional part and integer part can be that boundary number be determined with the decimal point of frequency control word.For example, being controlled for frequency Word F=I+r, wherein I is integer and r is the decimal more than or equal to zero and less than 1, then its integer part is I, fractional part For r.In embodiment of the disclosure, if the fractional part r of frequency control word is zero, i.e., frequency control word is integer, then may be used To think that the frequency control word does not have fractional part.

First frequency control word F will be described later_hWith second frequency control word F_lIt include corresponding fractional part (i.e. the One fractional part and the second fractional part are not the embodiment and second frequency control of signal generating circuit 10 in the case where 0) Word F processed_lThe embodiment of signal generating circuit 10 in the case where for integer (the second fractional part is 0).

In some embodiments, as shown in Figure 1B, signal generating circuit 10 can also include control circuit 104.Control Circuit 104 can be configured as determining first frequency control word F_hWith second frequency control word F_l, and export first frequency control word F_hTo the first generative circuit 101, second frequency control word F is exported_lTo the second generative circuit 102.For example, first frequency control word F_hWith second frequency control word F_lControl circuit 104 can be input to by input equipment by user.For example, first frequency controls Word F_hWith second frequency control word F_lIt can be stored in advance in storage equipment, and can be read by control circuit 104.For example, First frequency control word F_hWith second frequency control word F_lIt can also be automatically generated by control circuit 104.

Fig. 2 shows according to some embodiments of the present disclosure in first frequency control word F_hWith second frequency control word F_l Block diagram including the signal generating circuit in the case where corresponding fractional part.In the illustrated example shown in fig. 2, first frequency control Word F processed_hIt may include the first integer part and the first fractional part, second frequency control word F_lIt may include the second integer part With the second fractional part, the first integer part is identical with the second integer part, and the first fractional part and the second fractional part It is unequal.For example, the first fractional part and the second fractional part can be not equal to 0.

With reference to Fig. 2, in some instances, signal generating circuit 20 may include that the first generative circuit 201 and second generates Circuit 202.First generative circuit 201 may include the first numerically-controlled oscillator (Digitally Controlled Oscillator, DCO) sub-circuit 2011 and the first conversion sub-circuit 2012.Second generative circuit 202 may include the 2nd DCO Sub-circuit 2021 and the second conversion sub-circuit 2022.

For example, the first DCO sub-circuit 2011 can be configured as based on first frequency control word F_hWith fiducial time unit Δ generates first M signal S_h1, the first conversion sub-circuit 2012 can be configured as first M signal S_h1Be converted to One output signal S_h。

For example, the 2nd DCO sub-circuit 2021 can be configured as based on second frequency control word F_lWith fiducial time unit Δ generates second M signal S_l1, the second conversion sub-circuit 2022 can be configured as second M signal S_l1Be converted to Two output signal S_l。

The example embodiment of the first DCO sub-circuit 2011 and the first conversion sub-circuit 2012 is described below.

In some embodiments, the first DCO sub-circuit 2011 can be based on time average frequency (Time AverageFrequency, TAF) Lai Shixian.The principle of TAF technology is briefly described below in conjunction with Fig. 3.

Only have a kind of period different from traditional clock signal, the mode based on TAF technology can use two kinds or two Kind or more period with different length generate clock frequency.Below two different weeks time will be utilized with TAF technology Phase (period 1 T₁With second round T₂) pulse be illustrated for clock signal to synthesize.With reference to Fig. 3, when for benchmark Between units of delta and frequency control word F=I+r, wherein I be frequency control word F integer part, r be frequency control word F decimal Part can obtain two kinds of time cycles: period 1 T₁With second round T₂.Period 1 T₁With second round T₂It can divide It Tong Guo not formula (1) and formula (2) expression.

T₁=I Δ formula (1)

T₂=(I+1) Δ formula (2)

Utilize period 1 T₁With second round T₂, can be generated by staggered mode (different including two kinds of different cycles Frequency) clock signal.The average period of clock signal generated is T_TAF, as shown in formula (3).Clock letter generated Number average frequency be 1/T_TAF。

T_TAF=(1-r) T₁+r·T₂Formula (3)

From formula (3) as can be seen that the fractional part r of frequency control word F can control second round T₂Appearance probability. That is, the fractional part r of frequency control word F can control period 1 T₁With second round T₂Between switching frequency (it It is known as period switching afterwards).For example, clock signal generated can pass through T in the case where r=0.4₁T₁T₂T₁T₂Mode Loop cycle obtains, that is, T₁T₁T₂T₁T₂T₁T₁T₂T₁T₂T₁T₁T₂T₁T₂…….For example, in the case where r=0.5, it is generated Clock signal is to recycle to obtain by the pattern cycle of T1T2, that is, T₁T₂T₁T₂T₁T₂…….The wave of clock signal shown in Fig. 3 Shape corresponds to clock signal generated in the case where r=0.5.

In embodiment of the disclosure, in order to will the period used in the mode based on TAF technology with it is raw based on TAF technology At period of clock signal distinguished, two different cycle Ts used in the mode based on TAF technology₁And T₂It can be by Referred to as primitive period, the cycle T based on the clock signal that TAF technology generates_TAFAverage period can be referred to as.Correspondingly, it is based on The frequency 1/T for the clock signal that TAF technology generates_TAFAverage frequency can be referred to as.It is to be appreciated that in r=0, (i.e. frequency is controlled Word does not include fractional part) in the case where, although there is a kind of period based on the clock signal that TAF technology generates, give birth to At clock signal cycle T_TAFStill it is referred to as average period, to be consistent with above description.

A kind of specific example being generated clock frequency based on TAF technology is described below.For example, if to synthesize The frequency of 49.9MHz, traditional approach can only be constructed using a kind of pulse signal in period (for example, 20.04ns).Based on TAF Period 1 T can be used in technology₁(for example, 20ns) and second round T₂(for example, 20.1ns), passes through T₁T₁T₂T₁T₂Mould Formula (the fractional part r=0.4 corresponding to frequency control word F) loop cycle obtains frequency (the average period 20* of 49.9MHz 3/5+20.1*2/5=20.04ns).Furthermore it is possible to by using period 1 T₁(for example, 20ns) and second round T₂(example Such as, 20.08ns), pass through T₁T₂Mode (the fractional part r=0.5 corresponding to frequency control word F) loop cycle obtain The frequency (average period 20*1/2+20.08*1/2=20.04ns) of 49.9MHz.

The foregoing describe the basic principles of TAF technology.Based on TAF technology, the first DCO sub-circuit 2011 may be implemented.

In some embodiments, TAF technology, the first M signal S that the first DCO sub-circuit 2011 generates are based on_h1It is By the first primitive period (for example, corresponding to period 1 T recited above₁) and the second primitive period (for example, correspond to it is upper Second round T described in face₂) generate in an interleaved manner, that is to say, that first M signal S_h1It is by original with first What the pulse in period and pulse with the second primitive period generated in an interleaved manner.First M signal S generated_h1 One average period T_hIt can be indicated by formula (4).

T_h=(1-r_h)·T_A+r_h·T_BFormula (4)

In formula (4), T_hIndicate first M signal S_h1The first average period, r_hIndicate first frequency control word F_h One fractional part, T_A=I_hΔ indicates the first primitive period, T_B=(I_h+ 1) Δ indicates the second primitive period, I_hIndicate first Frequency control word F_hThe first integer part.

The foregoing describe the example embodiments of the first DCO sub-circuit 2011.It, can be with for the 2nd DCO sub-circuit 2021 It is realized using with the same or similar mode of the first DCO sub-circuit 2011, that is to say, that the 2nd DCO sub-circuit 2021 and One DCO sub-circuit 2011 can have same or like structure.It should be noted that can also use and the first DCO sub-circuit 2011 different modes realize the 2nd DCO sub-circuit 2021.

In some embodiments, the second M signal S that the 2nd DCO sub-circuit 2021 generates_l1It is original by first What period and the second primitive period generated in an interleaved manner, that is to say, that second M signal S_l1It is also by having the first original What the pulse in period beginning and the pulse with the second primitive period generated in an interleaved manner.With reference to formula (1) above and (2), by In first frequency control word F_hThe first integer part and second frequency control word F_lThe second integer part it is identical, be accordingly used in Synthesize first M signal S_h1With second M signal S_l1Primitive period it is identical, that is, be that the first primitive period and second are former Begin the period.

For example, second M signal S_l1Second average period T_lIt can be indicated by formula (5):

T_l=(1-r_l)·T_A+r_l·T_BFormula (5)

In formula (5), T_lIndicate second M signal S_l1The second average period, r_lIndicate second frequency control word F_l Two fractional parts, T_A=I_lΔ indicates the first primitive period, T_B=(I_l+ 1) Δ indicates the second primitive period, I_lIndicate second Frequency control word F_lThe second integer part, and I_l=I_h, Δ expression fiducial time unit.

Fig. 4 shows according to an embodiment of the present disclosure in r_h=0.5 and r_lThe first centre letter in the case where=0.25 Number S_h1Waveform and second M signal S_l1Waveform.With reference to Fig. 4, in r_h=0.5 and r_lIn the case where=0.25, in first Between signal S_h1With T_AT_BPattern cycle circulation, second M signal S_i1With T_AT_AT_AT_BPattern cycle circulation.As a result, first M signal S_h1The first average period can be (T_A+T_B)/2, second M signal S_l1The second average period can be (3T_A+T_B)/4。

The foregoing describe the embodiments that the first DCO sub-circuit and the 2nd DCO sub-circuit are realized based on TAF technology.Based on TAF The direct periods synthesizer of time average frequency (Time Average Frequency-Direct Period may be implemented in technology Synthesis, TAF-DPS) circuit framework.Therefore, in some embodiments, the first DCO sub-circuit 2011 and the 2nd DCO Circuit 2021 may include the direct periods synthesizer device of time average frequency based on TAF-DPS circuit framework.It later will be with reference to figure 10 time average frequency direct periods synthesizer devices of the description based on TAF-DPS circuit framework.It is to be appreciated that TAF-DPS circuit frame Structure is a kind of implementation of TAF technology, and embodiment of the disclosure is without being limited thereto.For example, can adopt in other embodiments With realizing the first DCO sub-circuit 2011 and the 2nd DCO sub-circuit 2021 based on other circuit structures of TAF technology.

In the embodiment that the first DCO sub-circuit and the 2nd DCO sub-circuit are realized based on TAF technology, first M signal S_h1Average frequency and second M signal S_l1Average frequency between difference on the frequency can be indicated by formula (6).In addition, the One M signal S_h1First average period T_hWith second M signal S_l1Second average period T_lPeriodic inequality can pass through Formula (7) indicates.

t_R'=T_h-T_l=F_h·Δ-F_lΔ=(I_h+r_h)·Δ-(I_l+r_l) Δ=(r_h-r_l)·Δ (7)

In formula (6) and formula (7), f_RIndicate first M signal S_h1Average frequency and second M signal S_l1Average frequency Difference on the frequency between rate, t_R' indicate first M signal S_h1First average period T_hWith second M signal S_l1It is second flat Equal cycle T_lBetween periodic inequality, r_hIndicate first frequency control word F_hThe first fractional part, r_lIndicate second frequency control word F_lThe second fractional part, I_hIndicate first frequency control word F_hThe first integer part, I_lIndicate second frequency control word F_l's Second integer part, and I_l=I_h, Δ expression fiducial time unit.From formula (6) as can be seen that first M signal S_h1Be averaged Frequency and second M signal S_l1Average frequency between difference on the frequency can be according to first frequency control word F_hThe first decimal Part and second frequency control word F_lThe second fractional part determine, the difference between the first fractional part and the second fractional part Value is very small, then first M signal S_h1Average frequency and second M signal S_l1Average frequency between difference on the frequency It is very small.In addition, due to first M signal S_h1First average period T_hIt is based on the first primitive period and the second original week What the phase was averagely obtained by the time, second M signal S_l1Second average period T_lIt is also based on the first primitive period and second What the primitive period was averagely obtained by the time, that is to say, that first M signal S_h1It is not that the size in each period is equal to T_h, And second M signal S_l1It is not that the size in each period is equal to T_l.For example, the first primitive period T_A, the second primitive period T_B, first M signal T average period_hBetween relationship can satisfy: T_A≤T_h≤T_B.Therefore, above-mentioned formula (7) only indicates One M signal S_h1The first average period and second M signal S_l1The second average period difference.For example, letter among first Number S_h1First average period T_hBe byWhat a period averagely obtained, wherein u₁=-log₂r_LSB1, r_LSB1For the first frequency Rate control word F_hThe first fractional part r_hThe corresponding value of least significant bit (least significant bit).Similarly, Second M signal S_l1Second average period T_lBe byWhat a period averagely obtained, wherein u₂=-log₂r_LSB2, r_LSB2For second frequency control word F_lThe second fractional part r_lThe corresponding value of least significant bit.For example, in r_h=0.125 (i.e. Binary value is 0.001B) in the case where, r_hLeast significant bit it is corresponding value be 0.125.For example, in r_h=0.75 (i.e. two into Value processed is 0.11B) in the case where, r_hLeast significant bit it is corresponding value be 0.25 (i.e. binary value is 0.01B).Formula (8) is shown Process is gone outThe first M signal S that a period averagely obtains_h1First average period T_h。

In formula (8), u₁=-log₂r_LSB1, r_LSB1For first frequency control word F_hThe first fractional part r_hIt is minimum effectively The corresponding value in position.

In some embodiments, the first conversion sub-circuit 2012 can be configured as first M signal S_h1It is converted to The first output signal S with a kind of period (i.e. the first average period)_h。

For example, the first conversion sub-circuit 2012 may include first filter, first filter, which can be configured as, to be filtered out First M signal S_h1In high fdrequency component to obtain the first output signal S_h.According to the configuration of the first DCO sub-circuit 2011, The first M signal S of one DCO sub-circuit 2011 output_h1Including high fdrequency component and low frequency component.By filtering out letter among first Number S_h1In high fdrequency component, it is available only include a kind of period the first output signal S_h.That is, passing through the first conversion Sub-circuit 2012, can be by first M signal S_h1Be converted to the conventional clock signal with a kind of period.In some embodiment party In formula, first M signal S_h1High fdrequency component and low frequency component can be with first M signal S_h1Period switching speed Or frequency is related.As previously described, the first M signal S exported by the first DCO sub-circuit 2011_h1It may include two The kind period: the first primitive period T_AWith the second primitive period T_B, therefore " the period switching " in some embodiments of the disclosure can refer to First primitive period T_ATo the second primitive period T_BOr the second primitive period T_BTo the first primitive period T_ASwitching.For example, right In first M signal S_h1, frequency is greater than first M signal S_h1Period switching speed or frequency minimum value frequency Component is first M signal S_h1High fdrequency component, frequency be less than or equal to first M signal S_h1Period switching speed Or the frequency component of the minimum value of frequency is first M signal S_h1Low frequency component.For example, first M signal S_h1Period The speed of switching or the minimum value of frequency can be f_h1·r_LSB(for example, in F_hIt is f in the case where 8.125_h10.125), Wherein r_LSB1For first frequency control word F_hThe first fractional part r_hThe corresponding value of least significant bit, f_h1For the first centre letter Number S_h1Average frequency.In this case, the bandwidth of first filter can be configured as less than or equal to f_h1·r_LSB, from And filter out first M signal S_h1In high fdrequency component.First output signal S of first filter output as a result,_hOnly have one The kind period.

Fig. 5 shows according to an embodiment of the present disclosure in r_hFirst M signal S in the case where=0.5_h1Waveform And the first output signal S_hWaveform.With reference to Fig. 5, after being handled by the first conversion sub-circuit 2012, first M signal S_h1It is converted into the first output signal S only with a type of period_h, wherein the first output signal S_hThe value in period be First M signal S_h1First average period T_hValue.For example, in r_hIn the case where=0.5, the first output signal S_hPeriod For (T_A+T_B)/2。

For example, the parameter of first filter can be according to first M signal S_h1Average frequency and first fractional part Least significant bit determines.

For example, the parameter of first filter may include the bandwidth of first filter, the bandwidth of first filter can root It is determined according to formula (9).

Bwlp1≤f_h1·r_LSB1Formula (9)

In formula (9), Bwlp1 is the bandwidth of first filter, r_LSB1For first frequency control word F_hThe first fractional part r_h The corresponding value of least significant bit,For first M signal S_h1Average frequency, Δ be benchmark chronomere. That is the first conversion sub-circuit 2012 can filter out first M signal as long as the bandwidth of first filter meets formula (9) S_h1In high fdrequency component, with obtain only include a kind of period the first output signal S_h。

For example, first filter may be implemented as analog filter or digital filter.For example, first filter is low Bandpass filter.

In some embodiments, the second conversion sub-circuit 2022 can be configured as first M signal S_h1It is converted to The first output signal S with a kind of period (i.e. the second average period)_h。

For example, the second conversion sub-circuit 2022 may include second filter, second filter, which can be configured as, to be filtered out Second M signal S_l1In high fdrequency component to obtain the second output signal S_l.According to the configuration of the 2nd DCO sub-circuit 2021, The second M signal S of two DCO sub-circuits 2021 output_l1Including high fdrequency component and low frequency component.By filtering out letter among second Number S_l1In high fdrequency component, it is available only include a kind of period the second output signal S_l.That is, passing through the second conversion Sub-circuit 2022, can be by second M signal S_l1Be converted to the conventional clock signal with a kind of period.In some embodiment party In formula, second M signal S_l1High fdrequency component and low frequency component can be with second M signal S_l1Period switching speed Or frequency is related.For example, for second M signal S_l1, frequency is greater than second M signal S_l1Period switching speed or The frequency component of the minimum value of frequency is second M signal S_l1High fdrequency component, frequency be less than or equal to second M signal S_l1Period switching speed or frequency minimum value frequency component be second M signal S_l1Low frequency component.For example, the Two M signal S_l1Period switching speed or the minimum value of frequency can be f_h2·r_LSB2(for example, in F_lFor 8.125 feelings It is f under condition_h20.125), wherein r_LSB2For second frequency control word F_lThe second fractional part r_lLeast significant bit it is corresponding Value, f_h2For second M signal S_l1Average frequency.In this case, the bandwidth of second filter can be configured as small In or equal to f_h2·r_LSB2, to filter out second M signal S_l1High fdrequency component.The second of second filter output is defeated as a result, Signal S out_lOnly there is a kind of period.

For example, the parameter of second filter can be according to second M signal S_l1Average frequency and second frequency control word F_lThe second fractional part r_lLeast significant bit determine.

For example, the parameter of second filter may include the bandwidth of second filter, the bandwidth of second filter can root It is determined according to formula (10).

Bwlp2≤f_h2·r_LSB2Formula (10)

In formula (10), Bwlp2 indicates the bandwidth of second filter, r_LSB2Indicate second frequency control word F_lSecond fractional part Divide r_lThe corresponding value of least significant bit,Indicate second M signal S_l1Average frequency, Δ indicate fiducial time Unit.As long as the second conversion sub-circuit 2022 can filter out second that is, the bandwidth of second filter meets formula (10) M signal S_l1In high fdrequency component, it is available only include a kind of period the second output signal S_l。

For example, second filter also may be implemented as analog filter or digital filter.For example, second filter can Think low-pass filter.

The foregoing describe some embodiments of the first conversion sub-circuit 2012 and the second conversion sub-circuit 2022, however this It discloses without being limited thereto.In some embodiments, the first conversion sub-circuit 2012 may include the first phaselocked loop.In such case Under, the loop bandwidth including the first phaselocked loop in the first conversion sub-circuit 2012 can be determined according to formula (9).Some In embodiment, the second conversion sub-circuit 2022 may include the second phaselocked loop.In this case, it is included in the first conversion The loop bandwidth of the second phaselocked loop in circuit 2012 can be determined according to formula (10).It is will be described with reference to FIG. 11 later according to this The exemplary construction of the phaselocked loop of disclosed embodiment.

By the first conversion sub-circuit 2012 and the second conversion sub-circuit 2022, can by frequency difference it is minimum first in Between signal S_h1With second M signal S_l1Be converted to the first minimum output signal S of cycle differentiation_hWith the second output signal S_l.Formula (11) the first output signal S can be indicated_hPeriod and the second output signal S_lPeriod between periodic inequality.

t_R=T_h-T_l=F_h·Δ-F_lΔ=(I_h+r_h)·Δ-(I_l+r_l) Δ=(r_h-r_l) Δ formula (11)

In formula (11), t_RIndicate the first output signal S_hPeriod and the second output signal S_lPeriod between periodic inequality, r_hIndicate first frequency control word F_hThe first fractional part, r_lIndicate second frequency control word F_lThe second fractional part, I_hTable Show first frequency control word F_hThe first integer part, I_lIndicate second frequency control word F_lThe second integer part, and I_l=I_h, Δ indicates fiducial time unit.With reference to above-mentioned formula (7) and formula (11), the first output signal S_hPeriod and the second output signal S_l Period between periodic inequality t_RWith first M signal S_h1First average period T_hWith second M signal S_l1It is second flat Equal cycle T_lBetween periodic inequality t_R' equal.

Fig. 6 shows the first output signal S according to an embodiment of the present disclosure_hWith the second output signal S_lSchematic diagram.

With reference to Fig. 6, from the first output signal S_hPhase edge and the second output signal S_lPhase edge alignment At the time of (that is, phase alignment), by a cycle, the first output signal S_hA cycle rising edge and second Output signal S_lA cycle rising edge time difference be t_R.By two periods, the first output signal S_hSecond The rising edge in period and the second output signal S_lSecond period rising edge time difference be 2t_R.Similarly, by five Period, the first output signal S_hThe 5th period rising edge and the second output signal S_lThe 5th period rising edge Time difference is 5t_R.Therefore, from the first output signal S_hPhase edge and the second output signal S_lPhase edge alignment Time, by m period, the first output signal S_hM-th of period rising edge and the second output signal S_lM-th Time difference between the rising edge in period is mt_R, wherein m is the integer more than or equal to 1.

It in some embodiments, is 1ns and (r in fiducial time units of delta_h-r_lIn the case where)=0.000001, First output signal S_hPeriod and the second output signal S_lPeriod between periodic inequality t_RCan be 1 femtosecond (fs), thus root The signal that temporal resolution is femtosecond magnitude can be obtained according to the signal generating circuit that the embodiment of the present disclosure provides.In the disclosure In embodiment, temporal resolution can refer to the first output signal S_hPeriod time span and the second output signal S_lPeriod Time span between time difference.

In some embodiments, by the way that suitable fiducial time units of delta, first frequency control word F is arranged_hWith second Frequency control word F_l, the signal that temporal resolution is picosecond (ps) magnitude can be obtained.

Fig. 7 shows the schematic diagram of fiducial time units of delta according to an embodiment of the present disclosure.

With reference to Fig. 7, fiducial time units of delta can be adjacent for any two of the reference signal at K uniform phase interval Time span (for example, phase difference) between reference signal, wherein K is the positive integer greater than 1.For example, K=16,32,128 or Other numerical value.Therefore, fiducial time unit Δ can correspond to the reference signal at K uniform phase interval.

For example, it is assumed that the frequency of K reference signal is f_div, the period is T_div, then the value of Elementary Time Unit Δ can To be indicated by formula (12).

Δ=T_div/ K=1/ (Kf_div) formula (12)

Fig. 8 shows a kind of schematic diagram of fiducial time unit generative circuit according to some embodiments of the present disclosure.

For example, as shown in figure 8, fiducial time unit generative circuit may include twisted ring counter.Twisted ring counter can be with Including multiple d type flip flops.For example, with reference to Fig. 8, in order to generate the reference signal at K uniform phase interval, twisted ring counter can be with Including K/2 concatenated triggers.For example, trigger can be d type flip flop.It include K/2 concatenated touchings in twisted ring counter In the case where sending out device, the digit of twisted ring counter is K/2.

With reference to Fig. 8, the output end of each trigger of twisted ring counter is combined into K output end, for exporting K phase The evenly spaced reference signal in position.

Fig. 9 shows the schematic diagram of another fiducial time unit generative circuit according to some embodiments of the present disclosure.

With reference to Fig. 9, fiducial time unit generative circuit may include the first voltage controlled oscillator (VCO) 901, phase-locked loop Circuit 902 and K output end 903.First voltage controlled oscillator 901 is configured as with predetermined oscillation hunting of frequency.Phase-locked loop Circuit 902 is configured as the output frequency of the first voltage controlled oscillator 901 being locked as reference output frequency.K 903 quilt of output end It is configured as output to the reference signal at K uniform phase interval, wherein K is the positive integer greater than 1.For example, K=16,32,128 or Other numerical value.

For example, as shown in figure 9, phase-locked loop circuit 902 may include the first phase discriminator (PFD), the first loop filtering Device (LPF) and the first frequency divider (FN).

The frequency phase discriminator for example, the first phase discriminator is exemplary.

For example, the first loop filter can be low-pass filter.

For example, the frequency division coefficient of the first frequency divider is N₀, N₀For real number, and N₀More than or equal to 1.

For example, in the embodiments of the present disclosure, firstly, the reference signal with reference frequency can be input into the first phase demodulation Device subsequently enters the first voltage controlled oscillator subsequently into the first loop filter, and what last first voltage controlled oscillator generated has Predetermined oscillation frequency f_vcolSignal can be divided by frequency divider to obtain the crossover frequency f of fractional frequency signal_vcol/N₀, point Frequent rate f_vcol/N₀It feeds back to the first phase discriminator, reference frequency and crossover frequency of first phase discriminator for comparison reference signal f_vcol/N₀, when reference frequency and crossover frequency f_vcol/N₀Frequency and equal phase when, error between the two is zero, at this point, Phase-locked loop circuit 902 is in the lock state.

Although combining Fig. 8 and Fig. 9 to describe the illustrative embodiments of fiducial time unit generative circuit above, this Disclosed embodiment is without being limited thereto.For example, delay phase-locked loop (Delay-Locked Loop, DLL) Lai Shixian benchmark can be passed through Time quantum generative circuit, or fiducial time unit generative circuit can be realized by LC voltage controlled oscillator and difference engine.

Figure 10 shows straight according to the time average frequency based on TAF-DPS circuit framework of some embodiments of the present disclosure Connect the circuit diagram of periods synthesizer device.TAF-DPS circuit framework in Figure 10, which can be used for generating, to be had as shown in formula (3) averagely Period is T_TAFSynthesis clock signal.

With reference to Figure 10, the direct periods synthesizer device 100 of time average frequency may include the first input module, the second input mould Block 1030 and output module 1040.

For example, the first input module includes the first logic control circuit 1010 and the second logic control circuit with reference to Figure 10 1020.First logic control circuit 1010 includes first adder 1011, the first register 1012 and the second register 1013.The Two logic control circuits 1020 may include second adder 1021, third register 1022 and the 4th register 1023.

For example, the second input module 1030 includes the first multiplexer 1031 of K → 1, the 2nd multichannel of K → 1 with reference to Figure 10 The multiplexer of multiplexer 1032 and 2 → 1 1033.First multiplexer 1031 of K → 1 and the 2nd multiplexer of K → 1 1032 Multiple input terminals, the control for respectively including the reference signal for receiving K (K is greater than 1 integer) a uniform phase interval are defeated Enter end and output end.2 → 1 multiplexers 1033 include control signal, output end, for receiving the first K → 1 multiplexing Second input terminal of the first input end of the output of device 1031 and the output for receiving the 2nd multiplexer of K → 1 1032.Example Such as, the time span between the adjacent reference signal of any two of the reference signal at K uniform phase interval is (for example, phase Difference) it can correspond to fiducial time units of delta.

For example, output module 1040 includes trigger circuit with reference to Figure 10.Trigger circuit is for generating train of pulse.Triggering electricity Road includes d type flip flop 1041, the first phase inverter 1042 and the second phase inverter 1043.D type flip flop 1041 includes data input pin, uses In the input end of clock for the output for receiving the output end from 2 → 1 multiplexers 1033 and for exporting the first clock signal The output end of CLK1.First phase inverter 1042 includes input terminal for receiving the first clock signal clk 1 and for output signal To the output end of the data input pin of d type flip flop 1041.Second phase inverter 1043 includes for receiving the first clock signal clk 1 Input terminal and output end for exporting second clock signal CLK2.The output end of trigger circuit or the second phase inverter 1043 Output end can be used as the output end of TAF-DPS frequency synthesizer.

For example, the first clock signal clk 1 is output to the control signal of 2 → 1 multiplexers 1033 with reference to Figure 10, The output end of first phase inverter 1042 is connected to the data input pin of d type flip flop 1041.

For example, the most significant bit that first adder 1011 can store frequency control word F and the first register 1012 (most significant bits, for example, 5 bits) is added, and then will add up in the rising edge of second clock signal CLK2 As a result it is saved in the first register 1012；Alternatively, first adder 1011 can be by frequency control word F and the first register All information of 1012 storages are added, and then be will add up result in the rising edge of second clock signal CLK2 and are saved in first and post In storage 1012.In the rising edge of next second clock signal CLK2, the most significant bit of the first register 1012 storage It will be stored in the second register 1013, and the selection signal as the first multiplexer of K → 1 1031, for more from K Select a signal as the output signal of the first multiplexer of K → 1 1031 in phase input signal.

For example, the highest that second adder 1021 can store frequency control word F/2 and the first register 1012 is effective Position is added, and then be will add up result in the rising edge of second clock signal CLK2 and is saved in third register 1022.Under When the rising edge of one the first clock signal clk 1, the information that third register 1022 stores will be stored in the 4th register In 1023, and the selection signal as the 2nd multiplexer of K → 1 1023, for selecting one from K leggy input signal Output signal of a signal as the 2nd multiplexer of K → 1 1023.

For example, 2 → 1 multiplexers 1033 can select to come from the first K in the rising edge of the first clock signal clk 1 A conduct in the output signal of → 1 multiplexer 1031 and output signal from the 2nd multiplexer of K → 1 1032 The output signal of 2 → 1 multiplexers 1033, using the input clock signal as d type flip flop 1041.

It is averaged for example, one of the output end of the output end of d type flip flop 1041 and the second phase inverter 1043 can be used as the time The output of the direct periods synthesizer device 100 of frequency.For example, the direct periods synthesizer device of the time average frequency of the first generative circuit is defeated It is out first M signal, the output of the direct periods synthesizer device of the time average frequency of the second generative circuit is letter among second Number.

For example, the selection signal of the second register 1013 output can be used for selecting the direct periods synthesizer of time average frequency The selection signal of the failing edge of the clock signal of the synthesis of the generation of device 100, the output of the 4th register 1023 can be used for selecting The rising edge of the clock signal of the synthesis of the generation of the direct periods synthesizer device 100 of time average frequency, the first register 1012 are anti- The signal for being fed to first adder 1011 can be used for controlling the synthesis of the generation of the direct periods synthesizer device 100 of time average frequency Clock period switching.For ease of description, the selection signal that the second register 1013 exports can be known as failing edge control The selection signal that 4th register 1023 exports is known as rising edge control word by word processed, by the first register 1012 feedback to the The signal of one adder 1011 is known as fractional frequency control word.

It should be noted that in addition, working principle about TAF-DPS, it can be with bibliography L.XIU, " Nanometer Frequency Synthesis beyond the Phase-Locked Loop ", Piscataway, NJ 08854, USA, John Wiley IEEE-press, 2012 and L.XIU, " From Frequency to Time-Average-Frequency:a Paradigm Shift in the Design of Electronic System ", Piscataway, NJ 08854, USA, John Wiley IEEE-press, 2015.It is incorporated herein by reference in its entirety as reference.

Figure 11 shows the circuit diagram of the phaselocked loop according to some embodiments of the present disclosure.

With reference to Figure 11, phaselocked loop 110 may include that the second phase discriminator 1101, the second loop filter 1102, second are voltage-controlled Oscillator 1103 and the second frequency divider 1104.

For example, the second voltage controlled oscillator, which can be configured as to be generated according to control variable, has predetermined oscillation frequency f_vco2's Oscillator signal.For example, the second voltage controlled oscillator can be digital vco.

Oscillator signal is divided for example, the second frequency divider can be configured as to obtain with dividing frequency f_vco2/N₁ Fractional frequency signal.For example, the frequency division coefficient of the second frequency divider is N₁, N₁For real number, and N₁More than or equal to 1.

For example, the second phase discriminator can be configured as reception input signal, and the frequency f of comparator input signal_inWith frequency dividing The crossover frequency f of signal_vco2/N₁Between difference, to export Differential variable.The frequency phase demodulation for example, the second phase discriminator is exemplary Device.

For example, the second loop filter can be configured as the high fdrequency component filtered out in Differential variable, to generate control the The control variable of two voltage controlled oscillators.

For example, the second voltage controlled oscillator can be additionally configured to the frequency f when input signal_inWith the frequency of fractional frequency signal f_vco2/N₁When equal, generate and export with target frequency f_oEcho signal.In the frequency f of input signal_inWith fractional frequency signal Frequency f_vco2/N₁In the case where equal, phaselocked loop is in the lock state.

As described above, in some embodiments, the first conversion sub-circuit 2012 may include the first phaselocked loop. In this case, the first phaselocked loop may be implemented as phaselocked loop 110 shown in Figure 11.

For example, input signal is when the first phaselocked loop in the first conversion sub-circuit 2012 is implemented as phaselocked loop 110 First M signal S_h1, echo signal is the first output signal S_h.In this case, the second loop filtering of phaselocked loop 110 The bandwidth of device 1102 can be determined according to formula (9).

As described above, in some embodiments, the second conversion sub-circuit 2022 may include the second phaselocked loop. In this case, the second phaselocked loop may be implemented as phaselocked loop 110 shown in Figure 11.

For example, input signal is when the second phaselocked loop in the second conversion sub-circuit 2022 is implemented as phaselocked loop 110 Second M signal S_l1, echo signal is the second output signal S_l.In this case, the second loop filtering of phaselocked loop 110 The bandwidth of device 1102 can be determined according to formula (10).

Figure 12 show it is according to some embodiments of the present disclosure, in second frequency control word F_lIn the case where integer The block diagram of signal generating circuit.In this case, first frequency control word F_hIt may include that the first integer part and first are small Number part, second frequency control word F_lIncluding the second integer part and the second fractional part, and the second fractional part is 0, also It is to say, second frequency control word F_lFor integer, second frequency control word F_l(i.e. the second integer part) is equal to first frequency control word F_hThe first integer part, the first fractional part is not 0, that is to say, that the first fractional part and the second fractional part are unequal. First output signal S_hPeriod and the second output signal S_lPeriod it is unequal.

With reference to Figure 12, signal generating circuit 120 may include the first generative circuit 1210 and the second generative circuit 1220.The One generative circuit 1210 may include the first numerically-controlled oscillator (Digitally Controlled Oscillator, DCO) Sub-circuit 1211 and the first conversion sub-circuit 1212.Second generative circuit 1220 may include the 2nd DCO sub-circuit 1221, and second The output of DCO sub-circuit 1221 is as the second output signal S_l。

In some embodiments, the first output signal S_hPeriod and the second output signal S_lPeriod between period Difference and fiducial time units of delta and first frequency control word F_hThe first fractional part it is related.

For example, the first DCO sub-circuit 1211 can be configured as based on first frequency control word F_hWith fiducial time unit Δ generates first M signal S_h1, the first conversion sub-circuit 1212 can be configured as first M signal S_h1Be converted to One output signal S_h。

For example, the 2nd DCO sub-circuit 1221 can be configured as based on second frequency control word F_lWith fiducial time unit Δ generates the second output signal S_l.Due to second frequency control word F_lFor integer, thus the 2nd DCO sub-circuit 1221 generate the Two output signal S_lIt only include a kind of period, for example, the second output signal S that the 2nd DCO sub-circuit 1221 generates_lIt only include tool There is the first primitive period T_APulse.

In some embodiments, the first DCO sub-circuit 1211 can be realized based on TAF technology.In this case, The first M signal S that first DCO sub-circuit 1211 generates_h1It is by the first primitive period and the second primitive period with the side of interlocking What formula generated, that is to say, that first M signal S_h1It is that by the pulse with the first primitive period and there is the second original week What the pulse of phase generated in an interleaved manner.First M signal S generated_h1First average period T_hFormula (4) can be passed through It indicates.Description before being referred to about the example embodiment based on TAF technology the first DCO sub-circuit 1211 of realization.

In some embodiments, the 2nd DCO sub-circuit 1221 can be realized based on TAF technology.In this case, Due to second frequency control word F_lFor integer (i.e. second frequency control word F_lThe second fractional part be zero), therefore second output Signal S_lSecond average period T_lFor the first primitive period T_A.That is, the second of the 2nd DCO sub-circuit 1221 generation is defeated Signal S out_lWith a kind of period, i.e. the first primitive period T_A.Showing for the 2nd DCO sub-circuit 1221 is realized about based on TAF technology Example embodiment can refer to before description.

In the embodiment for realizing the first DCO sub-circuit 1211 and the 2nd DCO sub-circuit 1221 based on TAF technology, first M signal S_h1Average frequency and the second output signal S_lAverage frequency between difference on the frequency can be indicated by formula (13). In addition, first M signal S_h1First average period T_hWith the second output signal S_lThe periodic inequality of average period can pass through Formula (14) indicates.

t_R'=T_h-T_l=F_h·Δ-F_lΔ=(I_h+r_h)·Δ-I_lΔ=r_hΔ formula (14)

In formula (13) and formula (14), f_RIndicate first M signal S_h1Average frequency and the second output signal S_lBe averaged Difference on the frequency between frequency, t_R' indicate first M signal S_h1First average period T_hWith the second output signal S_lAverage week Periodic inequality between phase, r_hIndicate first frequency control word F_hThe first fractional part, I_hIndicate first frequency control word F_h One integer part, I_lIndicate second frequency control word F_lThe second integer part, and I_l=I_h, Δ expression fiducial time unit, the Two frequency control word F_lThe second fractional part be zero.First M signal S_h1Average frequency and the second output signal S_lIt is flat Difference on the frequency between equal frequency can be according to first frequency control word F_hThe first fractional part determine, when the first fractional part Value is very small, then first M signal S_h1Average frequency and the second output signal S_lAverage frequency between difference on the frequency nor It is often small.For example, in first frequency control word F_hThe very small situation of the first fractional part under, pass through the first DCO sub-circuit 1211 and the 2nd DCO sub-circuit 1221 can obtain the very small first M signal S of frequency difference_h1With the second output signal S_l.In addition, due to first M signal S_h1It is not to be equal to T in each period_h, therefore, formula (14) only indicates first M signal S_h1The first average period and the second output signal S_lAverage period difference.For example, first M signal S_h1It is first average Cycle T_hBe byWhat a period averagely obtained, wherein u₁=-log₂r_LSB1, r_LSB1For first frequency control word F_hFirst Fractional part r_hThe corresponding value of least significant bit.

In some embodiments, the first conversion sub-circuit 1212 can be configured as first M signal S_h1It is converted to The first output signal S with a kind of period (i.e. the first average period)_h。

In some embodiments, the first conversion sub-circuit 1212 may include first filter, and first filter can be with It is configured as filtering out first M signal S_h1In high fdrequency component to obtain the first output signal S_h.According to the first DCO sub-circuit 1211 configuration, the first M signal S of the first DCO sub-circuit 1211 output_h1Including high fdrequency component and low frequency component.Pass through filter Except first M signal S_h1In high fdrequency component, it is available only include a kind of period the first output signal S_h.In some realities It applies in mode, first M signal S_h1High fdrequency component and low frequency component can be with first M signal S_h1Period switching Speed or frequency are related.As previously described, the first M signal S exported by the first DCO sub-circuit 1212_h1It can wrap Include two kinds of periods: the first primitive period T_AWith the second primitive period T_B, therefore " the period switching " in some embodiments of the disclosure can To refer to the first primitive period T_ATo the second primitive period T_BOr the second primitive period T_BTo the first primitive period T_ASwitching.Example Such as, for first M signal S_h1In, frequency is greater than first M signal S_h1Period switching speed or frequency minimum value Frequency component be first M signal S_h1High fdrequency component, frequency be less than or equal to first M signal S_h1Period switching Speed or frequency minimum value frequency component be first M signal S_h1Low frequency component.For example, first M signal S_h1 Period switching speed or the minimum value of frequency can be f_h1·r_LSB(for example, in F_hIt is f in the case where 8.125_h1· 0.125), wherein r_LSB1For first frequency control word F_hThe first fractional part r_hThe corresponding value of least significant bit, f_h1It is first M signal S_h1Average frequency.In this case, the bandwidth of first filter can be configured as less than or equal to f_h1· r_LSB, to filter out first M signal S_h1High fdrequency component.First output signal S of first filter output as a result,_hOnly have There is a kind of period.

For example, the parameter of first filter can be according to first M signal S_h1Average frequency and first fractional part Least significant bit determines.

For example, the parameter of first filter may include the bandwidth of first filter, the bandwidth of first filter can root It is determined according to formula (9).

For example, first filter may be implemented as analog filter or digital filter.For example, first filter can be with For low-pass filter.

In some embodiments, the first conversion sub-circuit 1212 may include the first phaselocked loop.In this case, it wraps The loop bandwidth for including the first phaselocked loop in the first conversion sub-circuit 1212 can be determined according to formula (9).For example, the first lock Phase ring may be implemented as phaselocked loop 110 described in Figure 11.

By the first conversion sub-circuit 1212, first M signal S that can be minimum by frequency difference_h1With the second output letter Number S_lBe converted to the first minimum output signal S of cycle differentiation_hWith the second output signal S_l.Formula (15) can indicate the first output Signal S_hPeriod and the second output signal S_lAverage period between periodic inequality.

t_R=T_h-T_l=F_h·Δ-F_lΔ=(I_h+r_h)·Δ-I_lΔ=r_hΔ formula (15)

In formula (15), t_RIndicate the first output signal S_hPeriod and the second output signal S_lAverage period between week Phase is poor, r_hIndicate first frequency control word F_hThe first fractional part, I_hIndicate first frequency control word F_hInteger part, I_lTable Show second frequency control word F_lThe second integer part, and I_l=I_h, Δ expression fiducial time unit, second frequency control word F_l The second fractional part be zero.With reference to above-mentioned formula (14) and formula (15), the first output signal S_hPeriod and the second output signal S_l Average period between periodic inequality t_RWith first M signal S_h1First average period T_hWith the second output signal S_lBe averaged Periodic inequality t between period_R' equal.

In some embodiments, from the first output signal S_hWith the second output signal S_lAt the time of phase alignment, warp M period is spent, the first output signal S_hM-th of period rising edge and the second output signal S_lM-th of period rising edge Between time difference be mt_R, wherein m is the integer more than or equal to 1.

It in some embodiments, is 1ns and r in fiducial time units of delta_hIn the case where=0.000001, first Output signal S_hPeriod and the second output signal S_lAverage period between periodic inequality t_RIt can be 1 fs, thus according to this The signal generating circuit that open embodiment provides can obtain the signal that temporal resolution is femtosecond magnitude.In the implementation of the disclosure In example, temporal resolution can refer to the first output signal S_hPeriod time span and the second output signal S_lAverage period Time span between time difference.

In some embodiments, by the way that suitable fiducial time units of delta and first frequency control word F is arranged_h, can be with Obtain the signal that temporal resolution is picosecond (ps) magnitude.

An at least embodiment for the disclosure also provides a kind of digit time conversion circuit.Figure 13 A is shown according to the disclosure An at least embodiment digit time conversion circuit block diagram.

With reference to Figure 13 A, digit time conversion circuit 130 may include signal generating circuit 131 and time generative circuit 132.Signal generating circuit 131 may include the first generative circuit 1311 and the second generative circuit 1312.First generative circuit 1311 can be configured as based on first frequency control word F_hThe first output signal S is generated with fiducial time units of delta_h.Second is raw It can be configured as at circuit 1312 based on second frequency control word F_lThe second output signal S is generated with fiducial time units of delta_l。 For example, signal generating circuit 131 can be realized according to signal generating circuit described in any of the above embodiment.Time generates electricity Road 132, which can be configured as, receives digital signal, the first output signal S_hAnd the second output signal S_l, and based on number letter Number, the first output signal S_hAnd the second output signal S_lGenerate first time pulse signal corresponding with digital signal or second Time pulse signal.For example, time generative circuit 132 can be configured as based on digital signal and the first output signal S_h Period and the second output signal S_lThe difference in period generate first time pulse signal or the second time pulse signal.

In some embodiments, digital signal can have the n-bit for being expressed as<n-1: 0>, and wherein n can indicate number The bit wide of word signal, and n is the integer more than or equal to 1.For example, time generative circuit 132 can be configured as based on number The bit wide of signal and the first output signal S_hPeriod and the second output signal S_lPeriod difference generate it is corresponding with digital signal First time pulse signal or the second time pulse signal.

In some embodiments, as shown in Figure 13 B, first time pulse signal can be individual signals.In this feelings The first minimum interval and the first output signal S under condition, between the rising edge and failing edge of first time pulse signal_h's Period and the second output signal S_lPeriod difference it is related.Here, the first minimum interval indicates first time pulse signal Rising edge and failing edge between the smallest time interval, the first minimum interval can refer to that first time pulse signal exists The time interval between rising edge and failing edge in a cycle, that is to say, that the first minimum interval can refer to first The pulsewidth of single pulse in time pulse signal.

In some embodiments, as shown in fig. 13 c, the second time pulse signal may include the first subpulse signal and Second subpulse signal.In this case, the rising edge of the rising edge of the first subpulse signal and the second subpulse signal it Between the second minimum interval and fiducial time unit, the first output signal S_hPeriod and the second output signal S_lPeriod Difference it is related.Here, the second minimum interval indicates the upper of rising edge and the second subpulse signal of the first subpulse signal The smallest time interval between is risen, for example, the second minimum interval can refer on first of the first subpulse signal Rise the time interval between first rising edge corresponding with the second subpulse signal.For example, the first subpulse signal can Only to include single rising edge, the second subpulse signal can only include single rising edge, and the second minimum interval can refer to Time interval between the rising edge of first subpulse signal and the rising edge of the second subpulse signal.

For example, the first minimum interval and the second minimum interval can be equal.

For example, the first minimum interval or the second minimum interval can be indicated by formula (16).

DeltaT=nt_RFormula (16)

In formula (16), DeltaT indicates the first minimum interval or the second minimum interval, and n is indicated and digital signal Corresponding value (for example, bit wide of digital signal), t_RIndicate the first output signal S_hPeriod and the second output signal S_lWeek Periodic inequality between phase.For example, t_RIt can indicate the minimum time resolution ratio of digit time converter, i.e. 1 least significant bit (Least Significant bit, LSB) corresponding time.t_RSmaller, time precision (i.e. temporal resolution) is higher, and n is got over Greatly, the range (range) that DeltaT is covered is bigger.

Depending on the implementation of signal generating circuit 131, the first output signal S_hPeriod and the second output signal S_l's Periodic inequality between period can be indicated by formula (11) or formula (15).In addition, in some embodiments, being retouched as before It states, from the first output signal S_hWith the second output signal S_lAt the time of phase alignment, by m period, the first output letter Number S_hM-th of period rising edge and the second output signal S_lM-th of period rising edge between time difference be mt_R, Wherein, m is the integer more than or equal to 1.Therefore, the first output signal S can be based on_hM-th of period rising edge and second Output signal S_lM-th of period rising edge between time difference be mt_RTo generate first time pulse signal or generation The second time pulse signal including the first subpulse signal and the second subpulse signal.

In a kind of example, time generative circuit 132 may include the first counter, the second counter and decoder.The One counter can be configured as from the first output signal S_hWith the second output signal S_lStart at the time of phase alignment defeated to first Signal S out_hPeriod counted.Second counter can be configured as from the first output signal S_hWith the second output signal S_l Start at the time of phase alignment to the second output signal S_lPeriod counted.Decoder can be configured as: defeated first Signal S out_hPeriodicity be equal to value corresponding with digital signal (for example, in the case where the bit wide n) of digital signal, first Output signal S_hThe rising edge in n-th of period first time pulse signal is set 1 at the time of correspond to, and in the second output letter Number S_lPeriodicity be equal to value corresponding with digital signal (for example, in the case where the bit wide n) of digital signal, in the second output Signal S_lThe rising edge in n-th of period first time pulse signal is set 0 at the time of correspond to.Thus, it is possible to generate pulsewidth and be The first time pulse signal of DeltaT.Alternatively, decoder can be configured as: in the first output signal S_hPeriodicity be equal to Value corresponding with digital signal is (for example, in the case where the bit wide n) of digital signal, in the first output signal S_hN-th week The first subpulse signal of the second time pulse signal is set 1 at the time of the rising edge of phase corresponds to, in the second output signal S_l's Periodicity is equal to value corresponding with digital signal (for example, in the case where the bit wide n) of digital signal, in the second output signal S_l The rising edge in n-th of period the second subpulse signal of the second time pulse signal is set 1 at the time of correspond to.Thus, it is possible to Generate include the first subpulse signal and the second subpulse signal the second time pulse signal, and the first subpulse signal and the Corresponding second minimum interval of two subpulse signals is DeltaT.

In some embodiments, due to the first output signal S_hPeriod and the second output signal S_lPeriod between Periodic inequality is femtosecond magnitude or picosecond magnitude, therefore the first time pulse that pulsewidth is femtosecond magnitude or picosecond magnitude can be generated Signal, or generating including time interval is femtosecond magnitude or the first subpulse signal and the second subpulse signal of picosecond magnitude The second time pulse signal.

In some embodiments, in order to determine the first output signal S_hPhase and the second output signal S_lPhase pair At the time of neat, digit time conversion circuit 130 can also include phase detector circuit.Phase detector circuit, which can be configured as, determines the One output signal S_hWith the second output signal S_lPhase relation with generate instruction the first output signal S_hPhase with second output Signal S_lPhase alignment indication signal.In this case, time generative circuit 132 can be configured as based on number letter Number, the first output signal S_h, the second output signal S_lFirst time pulse signal or the second time pulse letter are generated with indication signal Number.Some embodiments of the digit time conversion circuit including phase detector circuit are described below.

Figure 14 A shows the block diagram of the digit time conversion circuit according to some embodiments of the present disclosure.

With reference to Figure 14 A, digit time conversion circuit 140 may include signal generating circuit 141, time generative circuit 142 With phase detector circuit 143.Signal generating circuit 141 may include the first generative circuit 1411 and the second generative circuit 1412.The One generative circuit 1311 can be configured as based on first frequency control word F_hThe first output letter is generated with fiducial time units of delta Number S_h.Second generative circuit 1312 can be configured as based on second frequency control word F_lSecond is generated with fiducial time units of delta Output signal S_l.Time generative circuit 142, which can be configured as, receives digital signal, the first output signal S_hAnd second output Signal S_l, and it is based on digital signal, the first output signal S_hAnd the second output signal S_lGenerate corresponding with digital signal One time pulse signal or the second time pulse signal.

Signal generating circuit 131 can be realized using the signal generating circuit in some embodiments described according to fig. 2. Signal generating circuit 131 may include the first generative circuit 201 and the second generative circuit 202.First generative circuit 201 can wrap Include the first DCO sub-circuit 2011 and the first conversion sub-circuit 2012.Second generative circuit 202 may include the 2nd DCO sub-circuit 2021 and second conversion sub-circuit 2022.

For example, the first DCO sub-circuit can be configured as: being based on first frequency control word F_hIt is raw with fiducial time units of delta At first M signal S_h1；Generating first M signal S_h1When output with first M signal S_h1Rising edge it is corresponding First rising edge control word and first M signal S_h1The corresponding first failing edge control word of failing edge and with first M signal S_h1Period switch corresponding first fractional frequency control word.First conversion sub-circuit 2012 can be configured as By first M signal S_h1Be converted to the first output signal S_h.It include the average frequency of time described in Figure 10 in the first DCO circuit In the embodiment of the direct periods synthesizer device of rate, the first failing edge control word corresponds to the second register in the first DCO circuit The selection signal of 1013 outputs, the first rising edge control word correspond to the 4th register 1023 output in the first DCO circuit Selection signal, and the first fractional frequency control word corresponds to the first register 1012 feedback in the first DCO circuit to first The signal of adder 1011.

For example, the 2nd DCO sub-circuit can be configured as: being based on second frequency control word F_lIt is raw with fiducial time units of delta At second M signal S_l1；Generating second M signal S_l1When output with second M signal S_l1Rising edge it is corresponding Second rising edge control word and second M signal S_l1The corresponding second failing edge control word of failing edge and with second M signal S_l1Period switch corresponding second fractional frequency control word.Second conversion sub-circuit can be configured as Two M signal S_l1Be converted to the second output signal.It include that time average frequency described in Figure 10 is direct in the 2nd DCO circuit In the embodiment of periods synthesizer device, the second register 1013 that the second failing edge control word corresponds in the 2nd DCO circuit is defeated Selection signal out, the second rising edge control word correspond to the selection letter of the 4th register 1023 output in the 2nd DCO circuit Number, and the first register 1012 feedback that the second fractional frequency control word corresponds in the 2nd DCO circuit arrives first adder 1011 signal.

For example, in this example, first frequency control word F_hIt may include the first integer part and the first fractional part, Two frequency control word F_lIt may include the second integer part and the second fractional part, the first integer part and the second integer part phase Together, and the first fractional part and the second fractional part are unequal.For example, the first fractional part and the second fractional part can be equal Not equal to 0.

For example, phase detector circuit 143 can be configured as: based on the first rising edge control word, the second rising edge control word, First failing edge control word, the second failing edge control word, the first fractional frequency control word and the second fractional frequency control word generate Indicate the first output signal S_hPhase and the second output signal S_lPhase alignment indication signal.Due in the first output letter Number S_hPhase and the second output signal S_lPhase between phase difference it is minimum in the case where will appear metastable state, therefore directly Compare the first output signal S_hWith the second output signal S_lPhase relation it is highly difficult.First exported by the first DCO sub-circuit Rising edge control word, the first failing edge control word and the first fractional frequency control word and the 2nd DCO sub-circuit output second Rising edge control word, the second failing edge control word and the second fractional frequency control word, available first output signal S_hWith Two output signal S_lPhase relation, thus in the first output signal S_hPhase and the second output signal S_lPhase between It still is able to carry out phase bit comparison in the very small situation of phase difference.The one of phase detector circuit 143 is described below in conjunction with Figure 14 B Kind example.

Figure 14 B shows the schematic diagram of the phase detector circuit 143 according to some embodiments of the present disclosure.

With reference to Figure 14 B, phase detector circuit 143 may include that the first data comparator sub-circuit 1431, the second data compare Device sub-circuit 1432, third data comparator sub-circuit 1433, the 4th comparator sub-circuit 1434 and indication signal generate son electricity Road 1435.First data comparator sub-circuit 1431, which can be configured as, controls the first rising edge control word and the second rising edge Word is compared and exports the first comparison result.Second data comparator sub-circuit 1432 can be configured as the first failing edge Control word is compared with the second failing edge control word and exports the second comparison result.Third data comparator sub-circuit 1433 can To be configured as the first fractional frequency control word being compared with zero and export third comparison result.4th data comparator Circuit 1434, which can be configured as, to be compared with zero by the second fractional frequency control word and exports the 4th comparison result.Instruction letter Number generating sub-circuit 1435 can be configured as: indicate the first rising edge control word and the second rising edge control in the first comparison result Word processed is equal, the first failing edge control word of the second comparison result instruction is equal with the second failing edge control word, the first fractional frequency Control word is equal to zero and second in the null situation of fractional frequency control word, the first output signal S of output instruction_hPhase Position and the second output signal S_lPhase alignment indication signal；And in the rest of the cases (for example, being indicated in the first comparison result First rising edge control word and the second rising edge control word is unequal or the second comparison result indicates the first failing edge control word With the second failing edge control word is unequal or the first fractional frequency control word is not equal to zero or and the second fractional frequency control Word processed is not equal in the case where zero), output signal or output do not indicate the first output signal S_hPhase with second output believe Number S_lThe signal that is misaligned of phase.

For example, the first data comparator sub-circuit 1431, the second data comparator sub-circuit 1432, third data comparator Sub-circuit 1433, the 4th comparator sub-circuit 1434 and indication signal generate sub-circuit 1435 can be by combinational logic electricity Road is implemented.

In one example, with reference to Figure 14 C, when the first DCO circuit and the 2nd DCO circuit include described in Figure 10 Between the direct periods synthesizer device of average frequency embodiment in, phase detector circuit 143 can also include the 5th posting of being connected in series Storage 1436 and the 6th register 1437 and the 7th register 1438 and the 8th register 1439 being connected in series.With reference to figure 10, the failing edge control word of the second register 1013 output have passed through the first register 1012 and the second register 1013, and the 4th The rising edge control word that register 1023 exports have passed through third register 1022 and the 4th register 1023.Therefore, in order to make The first fractional frequency control word, the rising edge control word of first DCO circuit output are synchronous with the holding of failing edge control word, Ke Yishe Set the 5th register 1436 and the 6th register 1437 of series connection.Similarly, in order to make the second of the 2nd DCO circuit output Fractional frequency control word, rising edge control word are synchronous with the holding of failing edge control word, and the 7th deposit of series connection can be set Device 1438 and the 8th register 1439.

In this example, the 5th register 1436, which can be configured as, receives the first decimal that the first DCO sub-circuit is sent Frequency control word, third data comparator sub-circuit 1433 can be configured as the first decimal for exporting the 6th register 1437 Frequency control word and zero is compared and exports third comparison result.7th register 1438 can be configured as reception second The second fractional frequency control word that DCO sub-circuit is sent, the 4th data comparator sub-circuit 1434 can be configured as the 8th The second fractional frequency control word and zero that register 1439 exports is compared and exports the 4th comparison result.5th register 1436 and the 7th register 1438 can have configuration identical with the first register 1012 in Figure 10, the 6th register 1437 It can have configuration identical with the second register 1013 in Figure 10 with the 8th register 1439.

It is to be appreciated that although Figure 14 C shows the 5th register 1436 and the 6th register 1437 is configured as to first The example that the first fractional frequency control word that DCO sub-circuit is sent is cached.However, embodiment of the disclosure is without being limited thereto. Believe for example, the 5th register 1436 and the 6th register 1437 can be set in third data comparator sub-circuit 1433 and instruction Number generate sub-circuit 1435 between, and be configured as caching third data comparator sub-circuit 1433 comparison result so that First comparison result, the second comparison result are synchronous with third comparison result.Similarly, the 7th register 1438 and the 8th register 1439 can be set between the 4th data comparator sub-circuit 1434 and indication signal generation sub-circuit 1435, and be configured as The comparison result of the 4th data comparator sub-circuit 1434 is cached, so that the first comparison result, the second comparison result and the 4th Comparison result is synchronous.

Figure 15 A shows the block diagram of the digit time conversion circuit according to some embodiments of the present disclosure.

With reference to Figure 15 A, digit time conversion circuit 150 may include signal generating circuit 151, time generative circuit 152 With phase detector circuit 153.Signal generating circuit 151 may include the first generative circuit 1511 and the second generative circuit 1512.The One generative circuit 1511 can be configured as based on first frequency control word F_hThe first output letter is generated with fiducial time units of delta Number S_h.Second generative circuit 1512 can be configured as based on second frequency control word F_lSecond is generated with fiducial time units of delta Output signal S_l.Time generative circuit 152, which can be configured as, receives digital signal, the first output signal S_hAnd second output Signal S_l, and it is based on digital signal, the first output signal S_hAnd the second output signal S_lGenerate corresponding with digital signal One time pulse signal or the second time pulse signal.

Signal generating circuit 151 can be using the signal generating circuit in some embodiments described according to Figure 12 come real It is existing.Signal generating circuit 131 may include the first generative circuit 1511 and the second generative circuit 1512.First generative circuit 1511 It may include the first DCO sub-circuit 1513 and the first conversion sub-circuit 1514.Second generative circuit 1512 may include the 2nd DCO Sub-circuit 1515.

For example, in this example, first frequency control word F_hIt may include the first integer part and the first fractional part, Two frequency control word F_lIncluding the second integer part and the second fractional part, and the second fractional part is 0, that is to say, that second Frequency control word F_lIt can be integer, second frequency control word F_l(i.e. the second integer part) is equal to first frequency control word F_h's First integer part, the first fractional part are not 0, that is to say, that the first fractional part and the second fractional part are unequal.

For example, the first DCO sub-circuit 1513 can be configured as: being based on first frequency control word F_hWith fiducial time unit Δ generates first M signal S_h1；Generating first M signal S_h1When output with first M signal S_h1Rising edge it is opposite The the first rising edge control word and first M signal S answered_h1The corresponding first failing edge control word of failing edge, Yi Jiyu First M signal S_h1Period switch corresponding first fractional frequency control word.First conversion sub-circuit 1514 can be matched It is set to first M signal S_h1Be converted to the first output signal S_h.It include putting down the time described in Figure 10 in the first DCO circuit In the embodiment of the direct periods synthesizer device of homogeneous rate, the first failing edge control word corresponds to the second deposit of the first DCO circuit The selection signal that device 1013 exports, what the 4th register 1023 that the first rising edge control word corresponds to the first DCO circuit exported Selection signal, and the first fractional frequency control word adds corresponding to the first register 1012 feedback of the first DCO circuit to first The signal of musical instruments used in a Buddhist or Taoist mass 1011.

For example, the 2nd DCO sub-circuit 1515 can be configured as: being based on second frequency control word F_lWith fiducial time unit Δ generates the second output signal S_l.It include the direct periods synthesizer device of time average frequency described in Figure 10 in the 2nd DCO circuit In 100 embodiment, the selection that the second register 1013 that the second failing edge control word corresponds to the 2nd DCO circuit exports is believed Number, the second rising edge control word corresponds to the selection signal that the 4th register 1023 of the 2nd DCO circuit exports.

For example, phase detector circuit 153 can be configured as: based on the first rising edge control word, the second rising edge control word, First failing edge control word, the second failing edge control word, the first fractional frequency control word generate the first output signal S of instruction_h's Phase and the second output signal S_lPhase alignment indication signal.Due in the first output signal S_hPhase and second output Signal S_lPhase between phase difference it is minimum in the case where will appear metastable state, therefore directly relatively the first output signal S_hWith Second output signal S_lPhase relation it is highly difficult.By under the first rising edge control word of the first DCO sub-circuit output, first It drops under the second rising edge control word and second that control word and the first fractional frequency control word and the 2nd DCO sub-circuit export Drop is along control word, available first output signal S_hWith the second output signal S_lPhase relation, thus in the first output signal S_hPhase and the second output signal S_lPhase between the very small situation of phase difference under still be able to carry out phase bit comparison. A kind of example of phase detector circuit 153 is described below in conjunction with Figure 15 B.

Figure 15 B shows the schematic diagram of the phase detector circuit 153 according to some embodiments of the present disclosure.

With reference to Figure 15 B, phase detector circuit 153 may include that the first data comparator sub-circuit 1531, the second data compare Device sub-circuit 1532 and third data comparator sub-circuit 1533.The second frequency as used in the 2nd DCO sub-circuit 1515 Control word F_lFor integer, therefore compared with the phase detector circuit 143 in Figure 14 B, phase detector circuit 153 can not include the 4th number According to comparator sub-circuit.First data comparator sub-circuit 1531 can be configured as will be in the first rising edge control word and second It rises and is compared along control word and exports the first comparison result.Second data comparator sub-circuit 1532 can be configured as One failing edge control word is compared with the second failing edge control word and exports the second comparison result.Third data comparator electricity Road 1533, which can be configured as, to be compared with zero by the first fractional frequency control word and exports third comparison result.Indication signal Generating sub-circuit 1535 can be configured as: indicate that the first rising edge control word and the second rising edge control in the first comparison result Word is equal, the first failing edge control word of the second comparison result instruction is equal with the second failing edge control word, the first fractional frequency control In the null situation of word processed, the first output signal S of output instruction_hPhase and the second output signal S_lPhase alignment finger Show signal；And in the rest of the cases (for example, indicating that the first rising edge control word and the second rising edge control in the first comparison result Word is unequal or the second comparison result indicates that the first failing edge control word and the second failing edge control word are unequal or first Fractional frequency control word is not equal in the case where zero), output signal or output do not indicate the first output signal S_hPhase with Second output signal S_lThe signal that is misaligned of phase.

For example, the first data comparator sub-circuit 1431, the second data comparator sub-circuit 1432, third data comparator Sub-circuit 1433 and indication signal generate sub-circuit 1435 can be implemented by combinational logic circuit.

It in one example, include in Figure 10 in the first DCO circuit 1513 and the 2nd DCO circuit 1515 with reference to Figure 15 C In the embodiment of the direct periods synthesizer device 100 of the time average frequency of description, phase detector circuit 153 can also include that series connection connects The 5th register 1536 connect and the 6th register 1537.With reference to Figure 10, the failing edge control word of the second register 1013 output It has passed through the first register 1012 and the second register 1013, the rising edge control word of the 4th register 1023 output have passed through the Three registers 1022 and the 4th register 1023.Therefore, in order to make the first DCO circuit output the first fractional frequency control word, Rising edge control word is synchronous with the holding of failing edge control word, and the 5th register 1536 and the 6th deposit of series connection can be set Device 1537.

In this example, the 5th register 1536, which can be configured as, receives the first DCO sub-circuit 1513 is sent first Fractional frequency control word, third data comparator sub-circuit 1533 can be configured as export the 6th register 1537 first Fractional frequency control word and zero is compared and exports third comparison result.5th register 1536 can have in Figure 10 The identical configuration of first register 1012, the 6th register 1537 can have identical with the second register 1013 in Figure 10 Configuration.

It is to be appreciated that although Figure 15 C shows the 5th register 1536 and the 6th register 1537 is configured as to first The example that the first fractional frequency control word that DCO sub-circuit is sent is cached.However, embodiment of the disclosure is without being limited thereto. Believe for example, the 5th register 1536 and the 6th register 1537 can be set in third data comparator sub-circuit 1533 and instruction Number generate sub-circuit 1535 between, and be configured as caching third data comparator sub-circuit 1533 comparison result so that First comparison result, the second comparison result are synchronous with third comparison result.

An at least embodiment for the disclosure also provides a kind of signal creating method.Figure 16 is shown according to the disclosure at least The flow chart of the signal creating method of one embodiment.

Signal creating method according to an at least embodiment for the disclosure may include step S161 and S162.

Step S161: the first output signal is generated based on first frequency control word and fiducial time unit；

Step S162: the second output signal is generated based on second frequency control word and fiducial time unit.

In some embodiments, for the signal generating circuit of Fig. 2 description, first frequency control word may include first Integer part and the first fractional part, second frequency control word include the second integer part and the second fractional part, the first integer Part is equal to the second integer part, and the first fractional part and the second fractional part are unequal, the period of the first output signal and institute The period for stating the second output signal is unequal.Characteristic about fiducial time unit can refer to before description.

In some embodiments, step S161 may include: raw based on first frequency control word and fiducial time unit At first M signal；And first M signal is converted into the first output signal.First can be generated based on TAF method M signal.About the various embodiments that the method for generating first M signal can be described with reference to before, thereof will be omitted right Its description.

For example, it may include: the height filtered out in first M signal that first M signal, which is converted to the first output signal, Frequency component is to be converted to the first output signal for first M signal.

In some embodiments, step S162 may include: raw based on second frequency control word and fiducial time unit At second M signal；And second M signal is converted into the second output signal.Second can be generated based on TAF method M signal.About the various embodiments that the method for generating second M signal can be described with reference to before, thereof will be omitted right Its description.

For example, it may include: the height filtered out in second M signal that second M signal, which is converted to the second output signal, Frequency component is to be converted to the second output signal for second M signal.

In some embodiments, the periodic inequality between the period of the first output signal and the period of the second output signal with Decimal difference between fiducial time unit and the first fractional part and the second fractional part is related.Therefore, suitable by being arranged Fiducial time units of delta, first frequency control word and second frequency control word, can obtain temporal resolution be femtosecond or skin The signal of second-time.

In some embodiments, for the signal generating circuit of Figure 12 description, first frequency control word may include the One integer part and the first fractional part, second frequency control word include the second integer part and the second fractional part, and second Fractional part is 0, that is to say, that second frequency control word F_lIt can be integer, second frequency control word (i.e. the second integer portion Point) be equal to first frequency control word the first integer part, the first fractional part is not 0, that is to say, that the first fractional part and Second fractional part is unequal.

In some embodiments, step S161 may include: raw based on first frequency control word and fiducial time unit At first M signal；And first M signal is converted into the first output signal.First can be generated based on TAF method M signal.About the various embodiments that the method for generating first M signal can be described with reference to before, thereof will be omitted right Its description.

For example, it may include: the height filtered out in first M signal that first M signal, which is converted to the first output signal, Frequency component is to be converted to the first output signal for first M signal.

In some embodiments, the second output signal can be generated based on TAF method, for example, step S162 can be with It include: that the second output signal is generated based on second frequency control word and fiducial time unit.Second output signal only has one kind Period, about generate the second output signal method can with reference to before describe various embodiments, thereof will be omitted to its Description.

In some embodiments, the periodic inequality between the period of the first output signal and the period of the second output signal with Fiducial time unit and first frequency control word F_hThe first fractional part it is related.As a result, by the way that suitable fiducial time is arranged Units of delta and first frequency control word can obtain the signal that temporal resolution is femtosecond or picosecond magnitude.

An at least embodiment for the disclosure also provides a kind of digit time conversion method.Figure 17 shows according to the disclosure The flow chart of the digit time conversion method of an at least embodiment.

With reference to Figure 17, the digit time conversion method according to an at least embodiment for the disclosure may include step S171, S172, S173 and S174.

Step S171: the first output signal is generated based on first frequency control word and fiducial time unit.

Some embodiments of step S171 can refer to process described above S161.

Step S172: the second output signal is generated based on second frequency control word and fiducial time unit.

Some embodiments of step S172 can refer to process described above S162.

For example, step S171 can the first generative circuit as described in any of the above-described embodiment execute, step S172 can be with The second generative circuit as described in any of the above-described embodiment executes.

By step S171 and S172, the first output signal and the second output signal can be generated, wherein the first output letter Number period and the second output signal period between periodic inequality and fiducial time unit, first frequency control word and second frequency Rate control word is related.In some embodiments, the week between the period of the first output signal and the period of the second output signal Phase difference and decimal difference between fiducial time unit and the first fractional part and the second fractional part are related.In some embodiment party Periodic inequality and fiducial time unit and the first frequency in formula, between the period of the first output signal and the period of the second output signal Rate control word F_hThe first fractional part it is related.Therefore, the embodiment depending on step S172, the period of the first output signal Periodic inequality between the period of the second output signal can be indicated by formula (11) or formula (15).

Step S173: digital signal, the first output signal and the second output signal are received.

In some embodiments, digital signal can have the n-bit for being expressed as<n-1: 0>, and wherein n can indicate number The bit wide of word signal, and n is the integer more than or equal to 1.

Step S174: it is generated based on digital signal, the first output signal and the second output signal corresponding with digital signal First time pulse signal or the second time pulse signal.

For example, step S173 and S174 time generative circuit and phase detector circuit as described in any of the above-described embodiment It executes.

For example, the characteristic about first time pulse signal can be with reference to above in the embodiment of digit time conversion circuit In to the associated description of first time pulse signal, the characteristic about the second time pulse signal can be with reference to above in number Between conversion circuit embodiment in the associated description of the second time pulse signal.

In some embodiments, step S174 may include bit wide, the first output signal and based on digital signal Two output signals generate first time pulse signal or the second time pulse signal corresponding with digital signal.

In some embodiments, as previously described, from the phase of the first output signal and the second output signal At the time of phase alignment, by m period, the rising edge and the second output signal in m-th of period of the first output signal M-th of period rising edge between time difference be mt_R, wherein m is the integer more than or equal to 1.

In a kind of example, step S174 may include: the phase from the phase and the second output signal of the first output signal Start to count the period of the first output signal (for example, starting counting from 1) at the time of the alignment of position；From the first output signal Phase and the second output signal phase alignment at the time of start to count the period of the second output signal；It is defeated first First time pulse signal is set 1 at the time of the rising edge in n-th of period of signal corresponds to out, and in the second output signal First time pulse signal is set 0 at the time of the rising edge in n-th of period corresponds to.For example, from the phase of the first output signal with The phase alignment moment of second output signal starts to count the period of the first output signal, corresponding when count value is n The first output signal period be the first output signal n-th of period.For example, from the phase of the first output signal and the The phase alignment moment of two output signals starts to count the period of the second output signal, corresponding when count value is n The period of second output signal is n-th of period of the second output signal.Thus, it is possible to generate pulsewidth (when the i.e. first minimum Between be spaced) be DeltaT first time pulse signal.

Additionally or alternatively, step S174 may include: the rising edge pair in n-th of period of the first output signal The first subpulse signal is set 1 at the time of answering, by second at the time of the rising edge in n-th of period of the second output signal corresponds to Second subpulse signal of time pulse signal sets 1.For example, from the phase of the first output signal and the phase of the second output signal The alignment moment starts to count the period of the first output signal, the week of corresponding first output signal when count value is n Phase is n-th of period of the first output signal.For example, from the phase of the first output signal and the phase pair of the second output signal The neat moment starts to count the period of the second output signal, the period of corresponding second output signal when count value is n N-th of period of as the second output signal.Thus, it is possible to generate including the first subpulse signal and the second subpulse signal Second time pulse signal, and the first subpulse signal and corresponding second minimum interval of the second subpulse signal are DeltaT。

In some embodiments, digit time conversion method can also comprise determining that the first output signal and the second output The phase relation of signal indicates the phase and the indication signal of the phase alignment of the second output signal of the first output signal to generate. In this case, step S174 may include: based on digital signal, the first output signal, the second output signal and instruction letter Number generate first time pulse signal or the second time pulse signal.For example, receiving indication signal in step S174 In the case where (indication signal is the phase alignment for indicating the phase and the second output signal of the first output signal), then start pair The period of first output signal and the period of the second output signal are counted.

Method about the phase relation for determining the first output signal and the second output signal can be with reference to above various Embodiment omits descriptions thereof here.

In some embodiments, due to the period between the period of the first output signal and the period of the second output signal Difference can be femtosecond magnitude or picosecond magnitude, therefore the first time pulse that pulsewidth is femtosecond magnitude or picosecond magnitude can be generated Signal, or generating including time interval is femtosecond magnitude or the first subpulse signal and the second subpulse signal of picosecond magnitude The second time pulse signal.

In some embodiments, digit time conversion method described in Figure 17 can be applied to each according to the disclosure The digit time conversion circuit of kind embodiment.

For the disclosure, need to illustrate there are also the following:

(1) attached drawing of embodiment of the disclosure relates only to the structure being related to embodiment of the disclosure, other structures It can refer to and be commonly designed.

(2) in the absence of conflict, the feature in embodiment of the disclosure and embodiment can be combined with each other to obtain New embodiment.

The above is only exemplary embodiment of the invention, protection scope and is not intended to limit the present invention, this hair Bright protection scope is determined by the attached claims.