阅读说明：本技术 一种实时视频缩放的硬件电路及其缩放方法 (A kind of hardware circuit and its Zoom method of real-time video scaling ) 是由 杜高明 范涛 王家舜 于 2019-09-04 设计创作，主要内容包括：本发明公开了一种实时视频缩放的硬件电路及其缩放方法,该硬件电路包括：复位编码模块、水平预缩放模块、垂直缩放模块和复位解码模块；复位编码模块对摄像头输入的像素点进行编码；水平预缩放模块在对像素点进行水平方向上的预缩放；垂直缩放模块对预缩放的像素点进行垂直方向上的缩放；复位编码模块对垂直缩放后的像素点进行解码,恢复到摄像头输入的编码格式。本发明能绕开存储设备的读取/写入时间造成的性能瓶颈,从而提升视频缩放的处理速度、减少存储资源的面积开销,以达到实时同步处理。(The invention discloses the hardware circuit and its Zoom method of a kind of real-time video scaling, which includes: to reset coding module, horizontal pre- Zoom module, vertically scale module and reset decoder module；The pixel that coding module inputs camera is resetted to encode；Horizontal pre- Zoom module is carrying out the pre- scaling in horizontal direction to pixel；Vertically scale module carries out the scaling in vertical direction to the pixel scaled in advance；It resets coding module to be decoded the pixel after vertically scale, is restored to the coded format of camera input.Performance bottleneck caused by the read/write time that the present invention can get around storage equipment, thus the area overhead for promoting the processing speed of video scaling, reducing storage resource, to reach real-time synchronization processing.)

1. a kind of hardware circuit of real-time video scaling, it is characterized in that by reset coding module, horizontal pre- Zoom module, vertical contracting Amplification module and reset decoder module composition；

The pre- Zoom module of level is negative anti-by asynchronous FIFO _ 1, ROM_1 group, register cell, horizontal arithmetic unit and level Current feed circuit composition；

The vertically scale module is by asynchronous FIFO _ 2, ROM_2 group, BRAM group, vertical arithmetic element and vertical negative-feedback circuit Composition；

Assuming that the image resolution ratio after scaling is a_ when the resolution ratio of former frame original image is o_width × o_length width×a_length；

The ith pixel point for resetting coding module and obtaining current row k under camera input clock frequency, and to current The highest order of the ith pixel point of row k is extended, using the highest order expanded as flag bit, by remaining conduct Data bit；Whether the ith pixel point that current row k is judged further according to the frame enable signal that camera is transmitted is a frame image The first row first pixel, if so, by the mark position be " 1 ", otherwise, by mark position be " 0 "；To The ith pixel point of row k after to coding；

The ROM_1 group is as storage address and to be stored with row interpolation coefficient according to line displacement amount；Assuming that the row k after coding Ith pixel point j-th of pixel of the row k after pre- scaling, the pre- scaling are obtained after horizontal pre- Zoom module J-th of pixel of row k afterwards is mapped in s-th of pixel on horizontal image before scaling in advance for row k, wherein s= J × (o_width/a_width), then the line displacement amount is the fractional part of s, and the integer part of s is denoted as c；

Asynchronous FIFO _ 1 according to pixel of the camera input clock frequency after i-th of row k coding successively For pixel after each coding of row k is written when reaching horizontal pre-stored values r, asynchronous FIFO _ 1 is again by row k Pixel after i-th of coding passes to the register cell, until the received pixel number of the register cell institute When for n, indicate that the register cell storage finishes, thus after the pre- scaling of j-th for starting to calculate the row k after pre- scaling Pixel；

The horizontal arithmetic unit is from the pixel after n coding for obtaining row k in the register cell, further according to described The offset of pixel after j-th of row k pre- scaling from the corresponding n interpolation coefficient of ROM_1 group reading and according to The mode of assembly line carries out interpolation calculation, to obtain pre- interpolated data and as the pixel after j-th of pre- scaling of row k Point judges whether c*=c+2 is true, if so, the enabled letter of pre- scaling of the pixel after then enabling j-th of pre- scaling of row k Number be 0, be otherwise 1；；

Pixel calculating after scaling in advance for j-th of row k finishes, and the asynchronous FIFO _ 1 output empty is outputed signal to The horizontal negative-feedback circuit, the horizontal negative-feedback circuit generate feedback signal according to the empty output signal；

If the feedback signal is effective, the pixel after n coding of the row k stored in the register cell is kept Constant, i is not added 1；If the feedback signal is invalid, after n coding of the row k stored in the register cell Pixel is updated judgement, it is assumed that+1 pixel of jth of the row k after pre- scaling is mapped in the image before horizontal pre- scaling Upper the s* pixel for row k, c* are that the integer part of s* keeps i constant if c*=c, and utilizes register cell Pixel after n coding of middle stored row k calculates the pixel after jth+1 pre- scaling of row k, if c* ≠ c, Then it is described i is added 1 after so that the pixel after n of the row k stored in the register cell coding carries out 1 Shift LD, and after obtaining jth+1 pre- scaling that the pixel after n of updated row k coding is used to calculate row k Pixel；

The ROM_2 group is as storage address and to be stored with column interpolation coefficient according to line skew amount；Assuming that j-th of row k Pixel after pre- scaling obtains j-th of pixel of the b row after vertically scale after vertically scale module, described vertical J-th of pixel of the b row after scaling be mapped on the image before vertically scale be v row j-th of pixel, wherein v =b × (o_length/a_length), the then fractional part that the line skew amount is v, the integer part of v are denoted as d；And v The line skew amount of capable each pixel is all the same；

It is successively write scaling the pixel after frequency scales in advance since j-th of row k according to level is pre- asynchronous FIFO _ 2 For pixel after entering each pre- scaling of row k when reaching vertical pre-stored values u, asynchronous FIFO _ 2 are according still further to vertical pre- Pixel after j-th of row k pre- scaling is transmitted in BRAM group by scaling frequency, until the received picture of the BRAM group institute When vegetarian refreshments number is n × a_width, indicate that the BRAM group storage finishes, thus the n × a_width preshrunk to being stored Pixel after putting updates judgement, it is assumed that it is the of v* row that j-th of pixel of b-1 row, which is mapped in the image before scaling, J pixel, d* is the integer part of v*, if d*=d, the BRAM is pre- from reading in row k j-th in asynchronous FIFO _ 2 Pixel and covering after scaling are written at j-th of row of storage kth-n+1 of BRAM storage region；It is described if d* ≠ d N × a_width the pixel stored in BRAM remains unchanged；

The V-scaling unit from the pixel read in the BRAM group in n row after j-th of each row pre- scaling, further according to The line skew amount of the b row reads corresponding n interpolation coefficient from the ROM group and carries out interpolation in the way of assembly line It calculates, obtains interpolated data and as the pixel after j-th of scaling of b row；Judge whether d*=d+2 is true, if so, The pre- scaling enable signal of pixel after then enabling j-th of pre- scaling of b row is 0, is otherwise 1；

It is described to reset the pixel after decoder module is scaled according to j-th of vertical pre- scaling frequency acquisition b row, and according to it After flag bit generation scaling after the frame enable signal of image, the flag bit is deleted, to obtain the jth of decoded b row A pixel is for showing.

2. a kind of real-time video Zoom method, it is characterized in that carrying out as follows:

Step 1 assumes that when the resolution ratio of former frame original image be o_width × o_length, the image resolution ratio after scaling For a_width × a_length；Any a line pixel in original image is defined for row k pixel, in row k pixel Any one pixel be ith pixel point；

Assuming that the ith pixel point of the row k before pre- scaling obtains the jth of the row k after pre- scaling after pre- scaling processing A pixel；

Assuming that j-th of pixel of the row k after pre- scaling be mapped on the image before pre- scaling be row k s-th of pixel Point, wherein s=j × (o_width/a_width), then enabling line displacement amount is the fractional part of s, and the integer part of s is denoted as c；

Assuming that -1 pixel of jth of the row k after pre- scaling be mapped on the image before pre- scaling be row k the s* picture The integer part of vegetarian refreshments, s* is denoted as c*；

Assuming that scaling after b row j-th of pixel be mapped in scaling before image on be v row j-th of pixel, In, v=b × (o_length/a_length), then enabling line skew amount is the fractional part of v, and the integer part of v is denoted as d；And v The line skew amount of capable each pixel is all the same；

Assuming that j-th of pixel of the b-1 row after scaling is mapped in the image before scaling as j-th of pixel of v* row The integer part of v* is denoted as d*；

Step 2, initialization k=1, b=1；

Step 3, initialization i=0；

Step 4, initialization j=0；

I+1 is assigned to i by step 5；

Step 6 is extended the highest order of the ith pixel point of current row k, using the highest order expanded as mark Position, using remaining position as data bit；

Step 7, judge current row k ith pixel point whether be a frame image the first row first pixel, if Being is then " 1 " by the mark position, is " 0 " by mark position otherwise；Thus i-th of picture of the row k after being encoded Vegetarian refreshments executes step 5；

Step 8 judges whether i >=n is true, if so, then follow the steps 9；Otherwise, step 5 is executed；

The value of j+1 is assigned to j by step 9, judges whether j > a_width is true, if not, step 10 is executed, otherwise, then is sentenced Whether disconnected k >=n is true, if so, 15 are thened follow the steps, otherwise, executes step 3；

Step 10, scaled according to row k i-th, the (i-1)-th ... i-th-n+1 before picture point with after j-th of row k scaling The offset of pixel calculates j-th of preshrunk video reproduction vegetarian refreshments of row k；

Step 11 judges whether c*=c+2 is true, if so, the preshrunk of the pixel after then enabling j-th of pre- scaling of row k Putting enable signal is 1, is otherwise 0；

Step 12 judges whether k >=n is true, if so, execute step 13；Otherwise, then judge whether c*=c is true, if c*= C is set up, and thens follow the steps 9, otherwise, executes step 5；

Step 13, according to the pixel and b row the after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel calculates j-th of pixel of b row after scaling after j scaling；

Judge whether 14, d*=d+2 is true, if so, the pre- scaling of the pixel after then enabling j-th of pre- scaling of b row makes Energy signal is 1, is otherwise 0；

Step 15 judges whether j > a_width is true, if so, after b+1 is then assigned to b, step 17 is executed, otherwise, b is protected It holds constant and executes step 16；

Step 16 judges whether c*=c is true, if so, 9 are thened follow the steps, otherwise, executes step 5；

Step 17 judges whether b > a_length is true, if so, then when former frame original image is disposed, and returns and hold Row step 1 handles next frame original image, otherwise, executes step 18；

Step 18 judges whether d*=d is true, if not, 3 are thened follow the steps, otherwise, executes step 19；

Step 19, according to the pixel and b row the after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel after j scaling calculates j-th of pixel of b row after scaling；

Step 20 judges whether d*=d+2 is true, if so, the preshrunk of the pixel after then enabling j-th of pre- scaling of b row Putting enable signal is 1, is otherwise 0；

Step 21 judges whether j > a_width is true, if so, after then by b+1 value to b, step 17 is executed, otherwise, b is kept It is constant, and after the value of j+1 is assigned to j, execute step 19.

Technical field

The invention belongs to the text-processing field in information technology, specifically a kind of hardware electricity of real-time video scaling Road and its Zoom method.

Background technique

It is soft to install image procossing as the key technology in digital image processing techniques in computer end for video scaling techniques The method of part operates to complete the scaling processing of image, has exchanged preferable image scaling quality for by longer time-consuming, is to pass The video image processing system of system is by the way of；But in practical applications, the hardware resource of system is needed to have parallel place The ability of image information is managed, thus achieve the effect that handle in real time, so common computer cannot achieve the quick disengaging of data, into And it is not applied for real-time system；To have the ability handled in real time, it is desirable to have parallel processing image information capability Hardware platform.

Traditional image scaling software processing time is longer, cannot achieve real-time scaling, realizes image currently based on FPGA Scaling is more popular, is mostly based on FPGA and realizes that the thinking of video scaling follows the roadmap of software, first by a frame data Be stored in RAM/DDR, the image data for reloading needs is handled, processing speed gain by hardware resource itself processing High speed is realized, although being able to achieve real-time scaling, the case where frame per second declines, the amplification for high magnification numbe are had before and after scaling It is unable to reach the ideal frame per second handled in real time.

Summary of the invention

The present invention is to propose a kind of hardware of real-time video scaling to solve above-mentioned the shortcomings of the prior art place Circuit and its Zoom method, performance bottleneck caused by the read/write time to get around storage equipment reduce storage resource Area overhead, to promote the processing speed of video scaling, and reach real-time synchronization processing.

The present invention adopts the following technical scheme that in order to solve the technical problem

A kind of the characteristics of hardware circuit of present invention real-time video scaling by reset coding module, horizontal pre- Zoom module, Vertically scale module and reset decoder module composition；

The pre- Zoom module of level is by asynchronous FIFO _ 1, ROM_1 group, register cell, horizontal arithmetic unit and level Negative-feedback circuit composition；

The vertically scale module is by asynchronous FIFO _ 2, ROM_2 group, BRAM group, vertical arithmetic element and vertical negative-feedback Circuit composition；

Assuming that when the resolution ratio of former frame original image is o_width × o_length, the image resolution ratio after scaling is a_width×a_length；

The ith pixel point for resetting coding module and obtaining current row k under camera input clock frequency, and it is right The highest order of the ith pixel point of current row k is extended, using the highest order expanded as flag bit, by remaining position As data bit；Whether the ith pixel point that current row k is judged further according to the frame enable signal that camera is transmitted is a frame Otherwise mark position, is " 0 " if so, being " 1 " by the mark position by first pixel of the first row of image；From And the ith pixel point of the row k after being encoded；

The ROM_1 group is as storage address and to be stored with row interpolation coefficient according to line displacement amount；Assuming that after coding The ith pixel point of row k obtains j-th of pixel of the row k after pre- scaling after horizontal pre- Zoom module, described pre- J-th of pixel of the row k after scaling is mapped in s-th of pixel on horizontal image before scaling in advance for row k, In, s=j × (o_width/a_width), then the line displacement amount is the fractional part of s, and the integer part of s is denoted as c；

Asynchronous FIFO _ 1 is according to camera input clock frequency since the pixel after i-th of coding of row k For pixel after being sequentially written in each coding of row k when reaching horizontal pre-stored values r, asynchronous FIFO _ 1 is again by kth Pixel after i-th capable of coding passes to the register cell, until the received pixel of the register cell institute When number is n, indicate that the register cell storage finishes, thus the pre- scaling of j-th for starting to calculate the row k after pre- scaling Pixel afterwards；

The horizontal arithmetic unit from obtained in the register cell n of row k encode after pixel, further according to The offset of pixel after the pre- scaling of j-th of the row k reads corresponding n interpolation coefficient simultaneously from the ROM_1 group Interpolation calculation is carried out in the way of assembly line, to obtain pre- interpolated data and as the picture after j-th of pre- scaling of row k Vegetarian refreshments judges whether c*=c+2 is true, if so, the pre- scaling of the pixel after then enabling j-th of pre- scaling of row k is enabled Signal is 0, is otherwise 1；；

Pixel calculating after scaling in advance for j-th of row k finishes, the asynchronous FIFO _ 1 output empty output letter Number give the horizontal negative-feedback circuit, the horizontal negative-feedback circuit according to the empty output signal generate feedback signal；

The pixel if feedback signal is effective, after n coding of the row k stored in the register cell It remains unchanged, i is not added 1；If the feedback signal is invalid, to n coding of the row k stored in the register cell Pixel afterwards is updated judgement, it is assumed that before+1 pixel of jth of the row k after pre- scaling is mapped in horizontal pre- scaling It is the s* pixel of row k on image, c* is that the integer part of s* keeps i constant if c*=c, and utilizes register Pixel after n coding of the row k stored in unit calculates the pixel after jth+1 pre- scaling of row k, if c* ≠ c, then it is described i is added 1 after so that the pixel after n of the row k stored in the register cell coding carries out 1 The shift LD of position, and obtain+1 preshrunk of jth that the pixel after n coding of updated row k is used to calculate row k Pixel after putting；

The ROM_2 group is as storage address and to be stored with column interpolation coefficient according to line skew amount；Assuming that the of row k Pixel after j pre- scalings obtains j-th of pixel of the b row after vertically scale after vertically scale module, described J-th of pixel of the b row after vertically scale be mapped on the image before vertically scale be v row j-th of pixel, In, v=b × (o_length/a_length), then the fractional part that the line skew amount is v, the integer part of v is denoted as d； And the line skew amount of each pixel of v row is all the same；

Asynchronous FIFO _ 2 scaled in advance according to horizontal pre- scaling frequency since j-th of row k after pixel according to For pixel after each pre- scaling of secondary write-in row k when reaching vertical pre-stored values u, asynchronous FIFO _ 2 are according still further to vertical Pixel after j-th of row k pre- scaling is transmitted in BRAM group by straight pre- scaling frequency, until the BRAM group is received Pixel number when being n × a_width, indicate that the BRAM group storage finishes, thus a to the n × a_width stored Pixel after pre- scaling updates judgement, it is assumed that j-th of pixel of b-1 row is mapped in the image before scaling as v* row J-th of pixel, d* be v* integer part, if d*=d, the BRAM from asynchronous FIFO _ 2 read row k in jth Pixel and covering after a pre- scaling are written at j-th of row of storage kth-n+1 of BRAM storage region；If d* ≠ d, institute N × a_width the pixel stored in BRAM is stated to remain unchanged；

The V-scaling unit from the pixel read in the BRAM group in n row after j-th of each row pre- scaling, then Corresponding n interpolation coefficient is read from the ROM group according to the line skew amount of the b row and is carried out in the way of assembly line Interpolation calculation obtains interpolated data and as the pixel after j-th of scaling of b row；Judge whether d*=d+2 is true, if It sets up, then otherwise it is 1 that the pre- scaling enable signal of the pixel after enabling j-th of pre- scaling of b row, which is 0,；

It is described to reset the pixel after decoder module is scaled according to j-th of vertical pre- scaling frequency acquisition b row, and root After frame enable signal according to image after its flag bit generation scaling, the flag bit is deleted, to obtain decoded b row J-th of pixel is for showing.

A kind of the characteristics of real-time video Zoom method of the invention is to carry out as follows:

Step 1 assumes that when the resolution ratio of former frame original image be o_width × o_length, the image point after scaling Resolution is a_width × a_length；Defining any a line pixel in original image is row k pixel, row k pixel Any one pixel in point is ith pixel point；

Assuming that the ith pixel point of the row k before pre- scaling obtains the row k after pre- scaling after pre- scaling processing J-th of pixel；

Assuming that it is that j-th of pixel of the row k after pre- scaling is mapped on the image before pre- scaling s-th of row k Pixel, wherein s=j × (o_width/a_width), then enabling line displacement amount is the fractional part of s, and the integer part of s is denoted as c；

Assuming that -1 pixel of jth of the row k after pre- scaling be mapped on the image before pre- scaling be row k s* The integer part of a pixel, s* is denoted as c*；

Assuming that j-th of pixel of the b row after scaling is mapped on the image before scaling as j-th of pixel of v row Point, wherein v=b × (o_length/a_length), then enabling line skew amount is the fractional part of v, and the integer part of v is denoted as d； And the line skew amount of each pixel of v row is all the same；

Assuming that j-th of pixel of the b-1 row after scaling is mapped in the image before scaling as j-th of picture of v* row The integer part of vegetarian refreshments v* is denoted as d*；

Step 2, initialization k=1, b=1；

Step 3, initialization i=0；

Step 4, initialization j=0；

I+1 is assigned to i by step 5；

Step 6 is extended the highest order of the ith pixel point of current row k, using the highest order expanded as Flag bit, using remaining position as data bit；

Step 7, judge current row k ith pixel point whether be a frame image the first row first pixel, It is " 0 " by mark position otherwise if so, being " 1 " by the mark position；Thus i-th of the row k after being encoded Pixel executes step 5；

Step 8 judges whether i >=n is true, if so, then follow the steps 9；Otherwise, step 5 is executed；

The value of j+1 is assigned to j by step 9, judges whether j > a_width is true, if not, step 10 is executed, otherwise, Judge whether k >=n is true again, if so, 15 are thened follow the steps, otherwise, executes step 3；

Step 10 scales preceding picture point and j-th of row k scaling according to row k i-th, the (i-1)-th ... i-th-n+1 The offset of pixel afterwards calculates j-th of preshrunk video reproduction vegetarian refreshments of row k；

Step 11 judges whether c*=c+2 is true, if so, pixel after then enabling j-th of row k pre- scaling Pre- scaling enable signal is 1, is otherwise 0；

Step 12 judges whether k >=n is true, if so, execute step 13；Otherwise, then judge whether c*=c is true, if C*=c is set up, and thens follow the steps 9, otherwise, executes step 5；

Step 13, according to the pixel and b after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel calculates j-th of pixel of b row after scaling after j-th of row scaling；

Judge whether 14, d*=d+2 is true, if so, the preshrunk of the pixel after then enabling j-th of pre- scaling of b row Putting enable signal is 1, is otherwise 0；

Step 15 judges whether j > a_width is true, if so, after b+1 is then assigned to b, step 17 is executed, otherwise, B is remained unchanged and is executed step 16；

Step 16 judges whether c*=c is true, if so, 9 are thened follow the steps, otherwise, executes step 5；

Step 17 judges whether b > a_length is true, if so, then when former frame original image is disposed, and return Receipt row step 1 handles next frame original image, otherwise, executes step 18；

Step 18 judges whether d*=d is true, if not, 3 are thened follow the steps, otherwise, executes step 19；

Step 19, according to the pixel and b after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel after j-th of row scaling calculates j-th of pixel of b row after scaling；

Step 20 judges whether d*=d+2 is true, if so, pixel after then enabling j-th of b row pre- scaling Pre- scaling enable signal is 1, is otherwise 0；

Step 21 judges whether j > a_width is true, if so, after then by b+1 value to b, execute step 17, otherwise, b It remains unchanged, and after the value of j+1 is assigned to j, executes step 19.

Compared with prior art, the beneficial effects of the present invention are:

1, the present invention scaling unused a large amount of DDR of circuit go one full frame image data of storage, therefore not by memory read/write The time-consuming limitation of one full frame image data；In circuit scaling processing, horizontal scaling module keeps in n pixel with register cell Point, vertically scale module keep in n row preshrunk video reproduction vegetarian refreshments with twoport BRAM group, i.e., entire circuit only keeps in low volume data can be into Row scaling processing, the read/write time for storing equipment not will cause the performance bottleneck of entire circuit；

2, in " FPGA design of video image zooming and realization " paper that the present invention is delivered with Xian Electronics Science and Technology University The real-time scaling architecture stated, which is compared, following advantage: the present invention keeps horizontal scaling module independent by design logic control circuit Operation can not be blocked, and with FIFO_2 (about a line image data size) come the advanced operation of the pre- Zoom module of buffer level Data keep vertical module faster than level module arithmetic speed using two clock domains, and such FIFO_2 can be emptied after accumulation, Until needing the data of the temporary pre- Zoom module of level to come again next time, thus by pre- scaling horizontal in entire framework and vertically Scaling by the time domain in western electric paper 60% parallelization processing promoted in time domain 100% fully parallelized processing and 80% is reduced in storage resource expense compared with framework in western electric paper；

3, the present invention is realized completely using the framework and horizontal pre- scaling of temporary low volume data processing with vertically scale The time-consuming path of the key of entire circuit is data zooming processing after parallelization, to the core algorithm unit in data scaling processing The processing of three class pipeline has been carried out, multiplication, displacement, add operation have been subjected to flowing water wire cutting, the data contract after assembly line The main time-consuming step for putting processing is the operation time of multiplier.After optimizing critical path, the scaling architecture of the design compared with Scaling architecture in western electricity paper is compared, and for scaling in proportion, is increased to 60 frames/second by 24 frames/second speed Manage speed；

4, in addition to the optimization in terms of speed, the present invention best base of image effect after interpolation method takes current interpolation In the sampling window of bicubic (cube) 4 × 4；Realize framework it is fully parallelized when, have the precision of multiple clock frequencies Problem and FIFO empty/Man Wenti, it is excellent to devise new reset coded format and negative-feedback circuit, process for this unstable situation Output image after change has higher Y-PSNR；

5, hardware circuit design of the present invention when using parametrization method, can pass through and change input, output with phase The configuration of relevant parameter carries out zooming in or out for arbitrary proportion to the video of arbitrary resolution size to realize；

6, present invention scaling algorithm can handle the video of ultra high-definition, high speed in real time after depth parallelization, to height The amplification of multiple also can achieve the frame per second of 100 frames or more；

7, the generally present invention improves speed by the parallelization of depth under the premise of with less storage resource, The processing scaled in real time to the high magnification numbe of ultra high-definition, high-speed video is realized, and good image quality, image quality are clear.

Detailed description of the invention

Fig. 1 is the linked, diagram of each module of hardware circuit of the present invention；

Fig. 2 is the horizontal pre- Zoom module schematic diagram of the present invention；

Fig. 3 is vertically scale module diagram of the present invention；

Fig. 4 is the coded format schematic diagram that the present invention resets that coding module uses；

Fig. 5 is the pre-amplification hardware circuit schematic diagram of horizontal pre- Zoom module；

Fig. 6 is the pre- diminution hardware circuit schematic diagram of horizontal pre- Zoom module；

Fig. 7 horizontal arithmetic unit schematic diagram；

Fig. 8 is the amplification hardware circuit schematic diagram of vertically scale module；

Fig. 9 is the diminution hardware circuit schematic diagram of vertically scale module；

Figure 10 is vertical arithmetic element schematic diagram；

Figure 11 is the comparison diagram of the present invention with the highest frequency of the various scaling circuits proposed in recent years；

Figure 12 is the comparison diagram of the present invention with the processing frame per second of the various scaling circuits proposed in recent years.

Specific embodiment

In the present embodiment, as shown in Figure 1, a kind of hardware circuit of real-time video scaling uses the design of depth parallelization, And it is made of reset coding module, horizontal pre- Zoom module, vertically scale module and reset decoder module, wherein reset coding Module receives camera and inputs pixel, and the pixel after exports coding gives horizontal preshrunk amplification module, horizontal pre- Zoom module Pre- scaling processing is carried out to pixel, after vertically scale module is to output scaling after the progress vertically scale processing of preshrunk video reproduction vegetarian refreshments Pixel, the pixel after scaling exports decoded pixel after resetting decoder module；

For the resize-window that we use in implementation process for 4 × 4, the interpolating function of scaling is S (x)；

Horizontal pre- Zoom module is negative anti-by asynchronous FIFO _ 1, ROM_1 group, register cell, horizontal arithmetic unit and level Current feed circuit composition, as shown in Figure 2；

Vertically scale module is by asynchronous FIFO _ 2, ROM_2 group, BRAM group, vertical arithmetic element and vertical negative-feedback circuit Composition, as shown in Figure 3；

Assuming that when the resolution ratio of former frame original image is o_width × o_length, the image resolution ratio after scaling is a_width×a_length；

The ith pixel point that coding module obtains current row k under camera input clock frequency is resetted, and to current The highest order of the ith pixel point of row k is extended, using the highest order expanded as flag bit, by remaining conduct Data bit, as shown in figure 4, Fig. 4 is the output format after the coding successively carried out to each pixel of any row；Further according to The frame enable signal that camera is transmitted judge current row k ith pixel point whether be a frame image the first row Otherwise mark position, is " 0 " if so, being " 1 " by mark position by one pixel；Thus the row k after being encoded Ith pixel point；

ROM_1 group is as storage address and to be stored with row interpolation coefficient according to line displacement amount；Establish storage interpolation coefficient The detailed process of table are as follows: [0,1] section is divided into 128 minizones, i.e., each minizone length is 1/128.Assuming that interpolation Function is S (x), and △ x is line displacement amount, and the value of △ x is that can calculate in section [0,1] for 1/128 multiple all values The corresponding value of S (x), as interpolation coefficient.Due to needing to calculate four different S (x), i.e. S (1+ △ for the same △ x X), S (△ x), S (1- △ x), S (2- △ x), interpolation table is as indicated with 1；

1 interpolation coefficient table of table

Δx	S(1+Δx)	S(Δx)	S(1-Δx)	S(1-Δx)
					0	0	32768	0	0
1/128	-126	32763	132	-1
					2/128	-248	32748	272	-4
3/128	-366	32724	419	-9
					4/128	-481	32690	575	-16
.	.	.	.	.
					.	.	.	.	.
.	.	.	.	.
					124/128	-24	575	32690	-481
125/128	-16	419	32724	-366
					126/128	-4	272	32748	-248
127/128	-1	132	32763	-126

Assuming that the ith pixel point of the row k after coding obtain pre- scaling after horizontal pre- Zoom module after row k J-th of pixel, j-th of pixel of the row k after pre- scaling be mapped on the image before horizontal pre- scaling as row k S-th of pixel, wherein s=j × (o_width/a_width), then line displacement amount is the fractional part of s, the integer part of s It is denoted as c, it is assumed that image A resolution ratio is o_width × o_length before former frame scales in advance, and the image B after pre- scaling is differentiated Rate is a_width × o_length；So according to ratio, our mapping points of the available B (j, k) on A is A (s, k) =A (j* (o_width/a_width), k), wherein zoom factor is a_width/0_width；

Asynchronous FIFO _ 1 according to pixel of the camera input clock frequency after i-th of row k coding successively Be written row k each coding after pixel when reaching horizontal pre-stored values r, due to asynchronous FIFO _ 1 reading and write clock Frequency is different, and horizontal pre- scaling clock frequency can be variant with desired clock frequency in practice, and asynchronous FIFO _ 1 is read and write Clock frequency it is undesirable when will appear that reading is empty or the phenomenon that be filled with, and pre-stored data is to read empty situation in order to prevent to occur, Horizontal pre-stored values r is set as 10 according to the precision of clock frequency in the specific implementation, as shown in Figure 5, Figure 6, prestores r pre- scalings Preceding pixel point carries out tally control by the pre- memory controller in the circuit that scales in advance of level, different when prestoring pixel and being not up to r The reading of step FIFO_1 enables the connected multiple selector of interface and is locked in always by pre- memory controller as on 0, and FIFO_1 at this time It writes and does not read to pre-stored data；It the depth of asynchronous FIFO _ 1 is set as 1024 prevents from being filled with to happen；Again will asynchronous FIFO _ 1 Pixel after i-th of coding of row k passes to register cell, until the received pixel number of register cell institute is When n, since the window of scaling is 4 × 4, therefore the value of n is set as 4, when register cell receives 4 pixels, just can be carried out The processing scaled in advance indicates that register cell storage finishes, so that j-th for starting to calculate the row k after pre- scaling is pre- Pixel after scaling, the row coordinate of j-th current of pixel of line control unit record as shown in Figure 5, Figure 6；

Horizontal arithmetic unit is from the pixel after n coding for obtaining row k in register cell, further according to row k The offset of pixel after j-th of pre- scaling is from the corresponding n interpolation coefficient of ROM_1 group reading and in the way of assembly line Interpolation calculation is carried out, as shown in Figure 5, Figure 6, zoom factor is multiplied to obtain multiplication knot with the row coordinate of current j-th of pixel 0 to 6 of fruit s, s is fractional part, and the fractional part of s is exported as the offset of current j-th of pixel to ROM_1 group； As Fig. 7 horizontal arithmetic unit will be carried out from data before the scaling read in 4 interpolation coefficients and register device unit in ROM_1 group Pre- zoom operation, by operation be divided into multiplication, addition and displacement three steps operation, with register keep in each step result pass to it is next Step, which reaches, realizes pipelining processing, thus the pixel after obtaining pre- interpolated data and being scaled in advance as j-th of row k, Judge whether c*=c+2 is true, if so, the pre- scaling enable signal of the pixel after then enabling j-th of row k pre- scaling is 0, it is otherwise 1；When carrying out pre-amplification processing to image, since zoom factor is less than 1, judge whether c* is equal to c+2's every time As a result one is set to and is not equal to, and horizontal pre- scaling enable signal is set to always 1 when not receiving feedback signal, as shown in figure 5, when anti- When feedback signal is invalid, enable signal is locked on 1；When carrying out pre- diminution processing to image, since zoom factor is greater than 1, often It is secondary judge c* whether be equal to c+2 result may for it is equal may also be unequal, therefore need to be judged with logic circuit this as a result, As shown in Figure 6, it is assumed that feedback signal is invalid, and multiple selector chooses the output result of logic circuit in dashed rectangle in Fig. 6；In In dashed rectangle, the s* of zoom factor and j being multiplied, s* the 7th to the 16 part c* as s* integer judges c* and deposits Whether the result after the s integer part c of storage in a register subtracts each other is 2, if so, enable signal is then set to 0, it otherwise, will Enable signal is set to 1；

Pixel calculating after scaling in advance for j-th of row k finishes, and asynchronous FIFO _ 1 output empty is outputed signal to Horizontal negative-feedback circuit, horizontal negative-feedback circuit generate feedback signal according to empty output signal；

If feedback signal is effective, the pixel after n coding of the row k stored in register cell is kept not Becoming, i is not added 1, and negative-feedback circuit as shown in Figure 5, Figure 6 generates feedback signal to linage-counter according to the empty signal of FIFO, if Effectively then linage-counter stops counting feedback signal, and enable signal is set to 0；If feedback signal is invalid, to register list Pixel after n coding of the row k stored in member is updated judgement, it is assumed that jth+1 of the row k after pre- scaling Pixel is mapped in the s* pixel on horizontal image before scaling in advance for row k, and c* is the integer part of s*, if c*= C then keeps i constant, and calculates the of row k using the pixel after n of the row k stored in register cell coding Pixel after j+1 pre- scalings, if c* ≠ c, after i is added 1, so that n of the row k stored in register cell is compiled Pixel after code carries out 1 shift LD, and obtains the pixel after n coding of updated row k for calculating Pixel after jth+1 pre- scaling of row k；When carrying out pre-amplification processing to image, since zoom factor is less than 1, often It is secondary judge c whether be equal to c* result may for it is equal may also be unequal, therefore need to judge this with logic control circuit As a result, as shown in figure 5, prestore at this time control signal it is no longer valid, multiple selector chooses logic circuit in Fig. 5 dashed rectangle Export result；In dashed rectangle, the 7th to 16 integer as s* of the s* that zoom factor is multiplied with the result of j, s* Part c*；Judge whether c* and the integer part c for the s being stored in register are equal, asynchronous FIFO _ 1 if unequal It reads enable signal en_rd to be set to 1 and carry out the update of preshrunk video reproduction vegetarian refreshments and export into register cell, different if equal The reading enable signal en_rd of step FIFO_1 is set to 0, and the pre- scaling preceding pixel point in register cell is without updating；To figure As carry out reduce processing when, due to zoom factor be greater than 1, every time judge c whether be equal to c* result one be set to it is unequal, therefore often It is secondary to be all updated operation, it has failed as shown in fig. 6, prestoring control signal, the reading enable signal of asynchronous FIFO _ 1 locks always On 1；

ROM_2 group is as storage address and to be stored with column interpolation coefficient according to line skew amount；Establish storage interpolation coefficient The detailed process of table are as follows: [0,1] section is divided into 128 minizones, i.e., each minizone length is 1/128.Assuming that interpolation Function is S (y), and △ y is line skew amount, and the value of △ y is that can calculate in section [0,1] for 1/128 multiple all values The corresponding value of S (y), as interpolation coefficient.Due to needing to calculate four different S (x), i.e. S (1+ △ for the same △ y Y), S (△ y), S (1- △ y), S (2- △ y)；Assuming that the pixel after the pre- scaling of j-th of row k passes through vertically scale module J-th of pixel of j-th of pixel of the b row after obtaining vertically scale afterwards, the b row after vertically scale is mapped in vertically It is j-th of pixel of v row on image before scaling, wherein v=b × (o_length/a_length), then line skew amount Integer part for the fractional part for v, v is denoted as d；And the line skew amount of each pixel of v row is all the same；

It is successively write scaling the pixel after frequency scales in advance since j-th of row k according to level is pre- asynchronous FIFO _ 2 For pixel after entering each pre- scaling of row k when reaching vertical pre-stored values u, FIFO_2 pre-stored data is water in order to prevent Flat pre- scaling clock frequency is with vertically scale clock frequency since precision is not allowed that FIFO_2 is caused to occur reading empty phenomenon, specific implementation When circuit in u be set as a_width；As shown in Figure 8, Figure 9, when pre- memory controller no count is to u, the reading of asynchronous FIFO _ 2 is enabled The multiple selector that signaling interface is connected is locked on 0 always by pre- memory controller, and asynchronous FIFO _ 2 are read-only at this time does not write directly To u data are prestored into, asynchronous FIFO _ 2 are according still further to the vertical pre- frequency that scales by the pixel after j-th of row k pre- scaling It is transmitted in BRAM group, when the received pixel number of BRAM group institute is n × a_width, indicates that the storage of BRAM group finishes, Since resize-window is 4 × 4, therefore BRAM scaling of vertical direction when receiving 4 × a_width pixel just can be carried out, The realization of this step is also realized that asynchronous FIFO _ 2 read to enable to be locked on 1 at this time, and BRAM is constantly read by pre- memory controller Preshrunk video reproduction vegetarian refreshments in asynchronous FIFO _ 2, until reading 4 × a_width pixel；To the n × a_ stored Pixel after a pre- scaling of width updates judgement, it is assumed that j-th of pixel of b-1 row is mapped in the image before scaling For j-th of pixel of v* row, d* is the integer part of v*, if d*=d, BRAM read row k from asynchronous FIFO _ 2 In pixel after j-th of pre- scaling and covering be written at j-th of row of storage kth-n+1 of BRAM storage region；It covers every time Overwrite enters by the loading control unit control in Fig. 8, Fig. 9, which is loaded into control and is realized by state machine, if d* ≠ d, BRAM Middle n × a_width stored pixel remains unchanged, when amplifying to image, since zoom factor is less than 1, often It is secondary judge d whether be equal to d* result may for it is equal may also be unequal, therefore need to judge this with logic control circuit As a result, as shown in figure 8, prestore at this time control signal it is no longer valid, multiple selector chooses logic circuit in Fig. 8 dashed rectangle Export result；In dashed rectangle, the v* that zoom factor is multiplied with the result of j, v* the 7th to 16 portion as v* integer Divide d*, judges whether d* and the integer part d for the v being stored in register are equal, the reading of asynchronous FIFO _ 2 if unequal Enable signal en_rd is set to 1, BRAM and is updated operation, and BRAM reads j-th of pixel of row k and cover and writes from FIFO_2 Enter at j-th of -3 row of kth of storage of BRAM storage region, the reading enable signal en_rd of asynchronous FIFO _ 2 if equal 0, BRAM is set to operate without updating；When being reduced to image, due to zoom factor be greater than 1, every time judge d whether etc. It is set in the result one of d* unequal, therefore is updated operation every time, has been lost as shown in figure 9, prestoring control signal at this time Effect, the reading enable signal of asynchronous FIFO _ 2 are that 1, BRAM is carried out update operation every time always；

V-scaling unit is from the pixel after j-th of pre- scaling for reading each row in n row in BRAM group, further according to b Capable line skew amount reads corresponding n interpolation coefficient from ROM group and carries out interpolation calculation in the way of assembly line, vertically Unit for scaling receives four preshrunk video reproduction vegetarian refreshments in 4 interpolation coefficients and BRAM of ROM group, due to BRAM as shown in Figure 10 Update be that circulation covering write-in realizes that position that the data of row k store every time is different, so needing 4 multi-path choices Device selects the preshrunk video reproduction vegetarian refreshments in BRAM, which is generated by state machine cycles, later carry out corresponding data Multiplication, addition, three step pipeline operations of displacement obtain scaled data and as the pixel after j-th of scaling of b row；Sentence Whether disconnected d*=d+2 is true, if so, the pre- scaling enable signal of the pixel after then enabling j-th of pre- scaling of b row is 0, Otherwise it is 1, when amplifying processing to image, since zoom factor is less than 1, judges whether d* is equal to the result of d+2 every time One is set to and is not equal to, and vertically scale enable signal is 1 when feedback signal is invalid always, as shown in figure 8, feedback signal is invalid When, enable signal is locked on 1 always；When carrying out reducing processing to image, since zoom factor is greater than 1, c* is judged every time Whether equal to the result of c+2 may for it is equal may also be unequal, therefore need to be judged with logic circuit this as a result, such as Fig. 9 institute Show, it is assumed that feedback signal is invalid, and multiple selector chooses the output of logic circuit in dashed rectangle as a result, zoom factor and j As a result the v* being multiplied, v* the 7th to the 16 part d* as v* integer judges that the d* and v's that is stored in register is whole Number part d's subtracts each other whether result is 2, if so, enable signal is then set to 0, otherwise, enable signal is set to 1；

Decoder module is resetted according to the pixel after j-th of scaling of vertical pre- scaling frequency acquisition b row, and according to it After flag bit generation scaling after the frame enable signal of image, deleted marker position, to obtain j-th of picture of decoded b row Vegetarian refreshments is for showing.The design for resetting coding module and reset decoder module ensures the stability of circuit and the scaling of high quality Image.

In the present embodiment, a kind of real-time video Zoom method is to carry out as follows:

Step 1 assumes that when the resolution ratio of former frame original image be o_width × o_length, the image point after scaling Resolution is a_width × a_length；Defining any a line pixel in original image is row k pixel, row k pixel Any one pixel in point is ith pixel point；

Assuming that the ith pixel point of the row k before pre- scaling obtains the row k after pre- scaling after pre- scaling processing J-th of pixel；

Assuming that it is that j-th of pixel of the row k after pre- scaling is mapped on the image before pre- scaling s-th of row k Pixel, wherein s=j × (o_width/a_width), then line displacement amount is the fractional part of s, and the integer part of s is denoted as c；

Assuming that -1 pixel of jth of the row k after pre- scaling be mapped on the image before pre- scaling be row k s* The integer part of a pixel, s* is denoted as c*；

Assuming that j-th of pixel of the b row after scaling is mapped on the image before scaling as j-th of pixel of v row Point, wherein v=b × (o_length/a_length), then line skew amount is the fractional part of v, and the integer part of v is denoted as d；And The line skew amount of each pixel of b row is all the same；

Assuming that j-th of pixel of the b-1 row after scaling is mapped in the image before scaling as j-th of picture of v* row The integer part of vegetarian refreshments v* is denoted as d*；

Step 2, initialization k=1, b=1；

Step 3, initialization i=0；

Step 4, initialization j=0；

I+1 is assigned to i by step 5；

Step 6 is extended the highest order of the ith pixel point of current row k, using the highest order expanded as Flag bit, using remaining position as data bit；

Step 7, judge current row k ith pixel point whether be a frame image the first row first pixel, It is " 0 " by mark position otherwise if so, being " 1 " by mark position；Thus the ith pixel of the row k after being encoded Point executes step 5；

Step 8 judges whether i >=n is true, if so, then follow the steps 9；Otherwise, step 5 is executed, due to sampling window 4 × 4, horizontal pre- scaling at least needs n data, and return step 5 carries out data update if without n data；

The value of j+1 is assigned to j by step 9, judges whether j > a_width is true, if not, execute step 10, j > a_ When width is invalid, illustrate that row k pixel is not fully completed pre- scaling, needs to be implemented step 10 and continue to row k jth+1 A pixel is scaled in advance, otherwise, then judges whether k >=n is true, if so, k+1 is assigned to k and executes step 15, it is no Then, k+1 is assigned to k and executes step 3, when j > a_width is set up, illustrate that the preshrunk video reproduction vegetarian refreshments of row k is all defeated Out, the preshrunk video reproduction vegetarian refreshments for starting to export+1 row of kth illustrates that vertically scale does not have started progress, at this time if k >=n is invalid It needs return step 3 to continue the horizontal preshrunk video reproduction vegetarian refreshments output of+1 row of kth, illustrates vertically scale if k >=n is set up Start to carry out, therefore jump to step 15, the value of b+1 can be assigned to b by step 15, and the meaning for jumping to step 15 is as k >=n B and k will update together, i.e., horizontal pre- scaling executes together with vertically scale；

Step 10 scales preceding picture point and j-th of row k scaling according to row k i-th, the (i-1)-th ... i-th-n+1 The offset of pixel afterwards calculates j-th of preshrunk video reproduction vegetarian refreshments of row k；

Step 11 judges whether c*=c+2 is true, if so, pixel after then enabling j-th of row k pre- scaling Pre- scaling enable signal is 1, is otherwise 0；

Step 12 judges whether k >=n is true, if so, step 13 is executed, horizontal pre- scaled data is illustrated as k >=n N × a_width is had reached, pixel after j-th of row k scaling can be exported；Otherwise, then judge whether c*=c is true, if c* =c is set up, and thens follow the steps 9, otherwise, executes step 5；Illustrate that horizontal pre- scaled data is not up to n × a_width as k < n, Current j-th of pixel of row k not can be carried out vertically scale, therefore next be scaled in advance to+1 pixel of row k jth, Need to judge whether i-th of scaling preceding pixel point of row k updates before scaling+1 pixel of row k jth in advance, if c*=c It sets up, does not then need to update, execute step 9；If c*=c is invalid, need to update, executes step 5；

Step 13, according to the pixel and b after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel calculates j-th of pixel of b row after scaling after j-th of row scaling；

Judge whether 14, d*=d+2 is true, if so, the preshrunk of the pixel after then enabling j-th of pre- scaling of b row Putting enable signal is 1, is otherwise 0；

Step 15 judges whether j > a_width is true, if so, after b+1 is then assigned to b, step 17 is executed, otherwise, B remains unchanged and executes step 16, if j > a_width establishment shows pixel all output after b row scaling, next It jumps to step 12 and starts to process b+1 row data；Pixel is not after showing the scaling of b row if j > a_width is invalid All output, next jumps to step 16 and is updated judgement；

Step 16 judges whether c*=c is true, if so, 9 are thened follow the steps, otherwise, step 5 is executed, after updating judgement Pixel after jumping to row k jth+1 pre- scaling of step 5 or step 9 output；

Step 17 judges whether b > a_length is true, if so, then when former frame original image is disposed, and return Receipt row step 1 handles next frame original image, otherwise, executes step 18；

Step 18 judges whether d*=d is true, if not, 3 are thened follow the steps, otherwise, step 19 is executed, judges defeated Whether need to update before j-th of pixel of b+1 row out, need to update if d*=d is invalid, executes step 3；If d*=d Establishment does not need then to update, and executes step 19；

Step 19, according to the pixel and b after the pre- scaling of j-th of each row in kth, kth -1...... kth-n+1 row The offset of pixel after j-th of row scaling calculates j-th of pixel of b row after scaling；

Step 20 judges whether d*=d+2 is true, if so, pixel after then enabling j-th of b row pre- scaling Pre- scaling enable signal is 1, is otherwise 0；

Step 21 judges whether j > a_width is true, if so, after then by b+1 value to b, execute step 17, otherwise, b It remains unchanged, and after the value of j+1 is assigned to j, executes step 19, since the corresponding d value of each pixel of b row is all identical, institute All not need to update to pixel after any scaling in b row, therefore the value of j+1 is assigned to execute step 19 after j, until j > Pixel all output after the current b+1 row scaling in surface, executes step 17, to b+2 row later when a_width is set up It is handled.

Figure 11, Figure 12 are the comparison diagram with the various scaling circuit highest frequencies and processing frame per second that propose in recent years, wherein Abscissa is below with reference to scaling architecture proposed in document:

[1] " algorithm is scaled in real time towards a kind of hard-wired video "；

【2】《Hardware architecture ofbi-cubic convolution interpolation for real time image scaling"；

【3】《Real-time FPGA-based architecture forbicubicinterpolation: anapplication for digital image scaling"；

[4] " FPGA design of video image zooming and realization "；

【5】《Algorithm and vlsi architecture for highperformanceadaptive video scaling"；

【6】《VLSI Realization ofLanczos Interpolation for a Generic Video ScalingAlgorithm"；By data in figure as it can be seen that hardware circuit framework more traditional in speed ability is very big compared to having Advantage, and be able to achieve the scaling of high frame per second.

In conclusion the present invention can keep in the place of the video data progress real-time synchronization acquired after low volume data to camera Image data read/write is stored this process time-consuming bring performance bottleneck of equipment so as to get around in conventional architectures by reason, Horizontal pre- scaling is with vertically scale complete parallel during entire scaling and each module uses the design of deep pipeline, Therefore the hardware circuit of real-time video scaling can complete superfast video image processing, reset coding module and reset decoder module Ensure the stability of circuit and the scaling video of high quality.