阅读说明：本技术 芯片级封装的具有金属填充的深沉降区触点的功率mosfet (The power MOSFET of the deep decanting zone contact with metal filling of wafer-level package ) 是由 刘运龙 杨红 H·林 吕天平 邹胜 Q·贾 熊育飞 于 2016-06-30 设计创作，主要内容包括：一种形成包含功率半导体装置的IC(180)的方法包含：提供衬底(100),所述衬底在其上具有外延层(150),所述外延层具有形成于其中的被金属前电介质PMD层(118)覆盖的至少一个晶体管(160)。从接触开口蚀刻穿过所述PMD到所述外延层中以形成延伸到所述装置的第一节点的沉降区沟槽。沉积金属填充材料(128b)以覆盖所述沉降区沟槽的侧壁和底部,但不完全填充所述沉降区沟槽。在所述金属填充材料上方沉积电介质填料层(128c)以填充所述沉降区沟槽。移除所述电介质填料层的覆盖层区域,在所述覆盖层区域中的所述金属填充材料的表面上停止以形成沉降区触点(128)。形成图案化互连金属,从而在所述互连金属与所述沉降区沟槽的所述侧壁上的金属填充材料之间提供连接。(It is a kind of to form the method for IC (180) comprising power semiconductor arrangement and include: to provide substrate (100), the substrate has epitaxial layer (150) on it, and the epitaxial layer has at least one transistor (160) formed therein covered by pre-metal dielectrics pmd layer (118).The PMD is etched through into the epitaxial layer from contact openings to form the decanting zone groove for the first node for extending to described device.Deposited metal packing material (128b) is to cover side wall and the bottom of the decanting zone groove, but the not completely filled decanting zone groove.In the filler metal disposed thereon dielectric filler layer (128c) to fill the decanting zone groove.The covering layer region for removing the dielectric filler layer stops on the surface of the filler metal in the covering layer region to form decanting zone contact (128).Patterning interconnection metal is formed, to provide connection between the filler metal on the side wall of the interconnection metal and the decanting zone groove.)

1. a kind of method for forming the Integrated circuit IC comprising power semiconductor arrangement comprising:

Substrate is provided, the substrate has epi layers of extension on it, and the epitaxial layer, which has, to be formed to be included in the extension At least one transistor covered in layer and by pre-metal dielectrics pmd layer；

At least part of the pmd layer and the epitaxial layer is etched through from contact openings to be formed and extend to the power half The decanting zone groove of at least first node of conductor device；

Deposited metal packing material, wherein the filler metal covers side wall and the bottom of the decanting zone groove, but not It is filled up completely the decanting zone groove；

In the filler metal disposed thereon dielectric filler layer to fill the decanting zone groove；

The covering layer region for removing the dielectric filler layer, the table of the filler metal in the covering layer region Stop on face to form decanting zone contact, and

Patterning interconnection metal is formed, with the metal on the side wall of the interconnection metal and the decanting zone groove Connection is provided between packing material.

2. according to the method described in claim 1, wherein the deposition filler metal includes the chemical vapor deposition of tungsten W Product CVD.

3. according to the method described in claim 1, wherein the deposition dielectric filler layer includes that spin-coating glass SOG is applied Layer.

4. according to the method described in claim 1, the wherein covering layer region packet for removing the dielectric filler layer Include chemically mechanical polishing CMP.

5. according to the method described in claim 1, wherein the epitaxial layer with a thickness of at least 5 μm, and the decanting zone ditch Slot reaches the interface between the epitaxial layer and the substrate.

6. according to the method described in claim 1, wherein the power semiconductor arrangement includes metal oxide semiconductcor field effect Transistor MOSFET device is answered, and wherein the first node includes drain electrode.

7. according to the method described in claim 1, wherein the power semiconductor arrangement includes bipolar devices, and wherein institute Stating first node includes collector.

8. according to the method described in claim 1, the doping level wherein in the epitaxial layer is smaller than the doping level in the substrate At least one order of magnitude, and the decanting zone contact extends in the substrate.

9. according to the method described in claim 1, further comprising: before the deposition filler metal, In Barrier metals liner is formed in the decanting zone groove.

10. a kind of power semiconductor arrangement comprising:

Substrate has epi layers of extension on it；

Second device terminal in first device terminal, trap and including one 's in buried type drain electrode and buried type collector 3rd device terminal；

Decanting zone contact comprising the decanting zone groove of filling, the decanting zone groove extend through pre-metal dielectric and arrive Up to the 3rd device terminal,

Wherein the decanting zone contact includes filler metal, and the filler metal covers the side of the decanting zone groove Wall and bottom, but it is not filled up completely the decanting zone groove, and

Interior dielectric packing layer, inside the filler metal for filling the decanting zone groove.

11. power semiconductor arrangement according to claim 10, wherein the filler metal includes tungsten W.

12. power semiconductor arrangement according to claim 10, wherein the dielectric filler layer includes having micropore The sintering spin-coating glass SOG coating of degree.

13. power semiconductor arrangement according to claim 10, wherein the epitaxial layer with a thickness of at least 5 μm, and Wherein the decanting zone groove reaches the interface between the epitaxial layer and the substrate.

14. power semiconductor arrangement according to claim 10, wherein the power semiconductor arrangement includes metal oxidation Object semiconductor field effect transistor MOSFET device, and wherein the 3rd device terminal includes the buried type drain electrode.

15. power semiconductor arrangement according to claim 10, wherein the power semiconductor arrangement includes ambipolar dress It sets, and wherein the 3rd device terminal includes the buried type collector.

16. a kind of Integrated circuit IC comprising power semiconductor arrangement comprising:

Substrate has epi layers of extension on it；

The power semiconductor arrangement, it includes:

Second device terminal in first device terminal, trap and including one 's in buried type drain electrode and buried type collector 3rd device terminal；

Decanting zone contact comprising the decanting zone groove of filling, the decanting zone groove extend through pre-metal dielectric and arrive Up to the 3rd device terminal,

Wherein the decanting zone contact includes filler metal, and the filler metal includes tungsten W, and the metal fills material Material covers side wall and the bottom of the decanting zone groove, but is not filled up completely the decanting zone groove, and

Interior dielectric packing layer, in the filler metal for filling the decanting zone groove.

17. IC according to claim 16, wherein dielectric filler layer includes the sintering spin-coating glass with micro-porosity SOG coating.

18. IC according to claim 16, wherein the epitaxial layer with a thickness of at least 5 μm, and the decanting zone ditch Slot reaches the interface between the epitaxial layer and the substrate.

19. IC according to claim 16, wherein the power semiconductor arrangement includes metal oxide semiconductcor field effect Transistor MOSFET device is answered, and wherein the 3rd device terminal includes the buried type drain electrode.

20. IC according to claim 16, wherein the power semiconductor arrangement includes bipolar devices, and wherein institute Stating 3rd device terminal includes collector.

Technical field

Revealed embodiment is related to vertical power semiconductor device.

Background technique

In power integrated circuit (IC), high power transistor often takes up the major part of chip area.Vertical big function Rate device is smaller than the area that horizontal higher power device occupies, but need contact by electric current from buried type drain electrode or buried type collector It is transported to substrate surface.In general, by a series of different energy be implanted into dopant formed decanting zone contact, with formed from The top surface of substrate extends downwardly into the highly doped diffsuin stack of buried type drain electrode or buried type collector.Even if having during operation The diffusion of decanting zone contact, but when high current flows through diffsuin stack, in fact it could happen that apparent voltage drop, this can limit vertical big function The performance of rate transistor.

In order to improve performance, some devices on IC require low contact resistance.Generally for contact resistance is reduced, increases and expand It dissipates area and forms multiple contacts to be diffused.This increases the area of IC and can also increase diffusion capacitance, this may Reduce the performance of IC.

Summary of the invention

The content of present invention is provided to introduce in simplified form hereinafter in the specific implementation comprising provided attached drawing The brief set of the disclosed concept further described in mode.The content of present invention is not intended to be limited to the model of advocated theme It encloses.

In power field effect transistor (FET) wafer-level package (CSP) device, it is recognized that, it usually needs from device Top surface extend downwardly into buried type drain electrode (for Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) or bury The deep low resistance decanting zone contact of formula collector (for bipolar devices) is connected with the low resistance for providing the top surface of device It connects.This enables all device terminals to be in the top table of tube core in the form of solder projection (for example, convex block on bonding welding pad) On face.For middle pressure power fet device, it is recognized that, it is known that decanting zone contact technique due to by small critical dimension (CD) and the depth of decanting zone contact is die pressing product design during high resistance generated to a small number of μm and being no longer enough generate Low connection (ON) resistance.Very deep decanting zone may be needed to touch due to being used to support the relatively thick epitaxial layer (epi) of middle die pressing product (for example, for 40V rated device, the thickness of epi can be about 5.8 μm to point (> 5 μm), and for 60V rated device, epi It is thicker, such as with a thickness of about 7.2 μm).

Revealed embodiment includes the method for forming decanting zone contact, and the method is processed only using filler metal It is partially filled with decanting zone groove, followed by interior dielectric packing layer is (for example, spin-coating glass (SOG) and/or other dielectrics Material) depositing operation to be to complete the filling to decanting zone groove.Filler metal provides low resistance, because electrical contact is It is carried out along the entire sidewall areas of decanting zone contact and bottom, and interior dielectric filler independently of decanting zone depth and sinks It drops area's area and executes the function of substantially completely filling decanting zone contact.

When using known deep decanting zone contact technique, especially when contact sizes are very big and depth dramatically increases, Significant wider and deeper decanting zone contact is realized in this processing, and the decanting zone contact overcomes contact metal (for example, W) to fill out Fill --- the known challenge comprising semiconductor (for example, Si) side wall barrier layer covering and metal seam (void area).It is revealed Method can also be by the Depth Expansion of decanting zone contact to wide range, and it is various to meet still can to provide low resistance Different product design demands.More generally, revealed method can provide the decanting zone contact of the depth of covering wide scope To meet different FET or bipolar design requirement.

Detailed description of the invention

With reference to the drawings, the drawings are not necessarily drawn to scale, in the accompanying drawings:

Fig. 1 is according to the cross-sectional view of the integrated circuit (IC) of example embodiment, and the integrated circuit has comprising being taken off Example power N-channel metal-oxide semiconductor (MOS) (NMOS) transistor of the decanting zone contact shown.

Fig. 2 is the cross-sectional view of the Example power NMOS transistor comprising revealed decanting zone contact.

Fig. 3 is the cross-sectional view of the Example power NMOS transistor comprising revealed decanting zone contact.

Fig. 4 A to Fig. 4 H is the cross-sectional view for the power nmos transistor described in the continuous fabrication stage shown in Fig. 3, Wherein Fig. 4 D to 4H depicts the revealed deep decanting zone processing for only forming the first and second deep decanting zones.

Fig. 5 is the cross-sectional view with the power nmos transistor to the revealed decanting zone contact of its drain electrode.

Fig. 6 is the cross-sectional view with the power npn bipolar transistor to the revealed decanting zone contact of its collector.

Specific embodiment

Describe example embodiment with reference to the accompanying drawings, wherein same reference numerals are for indicating similar or equivalence element.Movement Or the order illustrated of event be not considered as it is restrictive because it is some movement or event may in a different order and/or Occur simultaneously with other movements or event.Further, the movement of some diagrams or event may not be needed to implement according to this public affairs The method opened.

Moreover, such as it is further limit in the case where term as used herein " being coupled to " or " with ... couple " (etc.) be intended to describe directly or indirectly to be electrically connected.Therefore, if first device is " coupled " to second device, this company Connecing can be to only have the direct electrical connection of parasitics, or by via Jie comprising other devices and connection in passage path Enter the indirect electrical connection of item.For INDIRECT COUPLING, the information that item does not modify signal usually, but its adjustable electric current electricity are intervened Flat, voltage level and/or power level.

Fig. 1 is the cross-sectional view of the IC 180 comprising Example power semiconductor device, the Example power semiconductor device Including vertical power NMOS transistor 160, there are two (the decanting zone touchings of revealed low resistance decanting zone contact for the transistor tool Point) 128, it is shown as the drain electrode of its buried type.Although NMOS and NPN transistor is generally described herein, for affiliated neck The those of ordinary skill in domain also forms PMOS transistor it is evident that using this information by p-doping substitution n- doped region And PNP transistor, and vice versa.Therefore the power semiconductor arrangement can include being laid out with trench gate or planar gate PMOS or NMOS device perhaps PNP or NPN vertical bipolar device or more generally any device (no matter it is discrete or On IC), described device is needed from buried type device terminals (for example, the buried type terminal in the substrate with epi layers thereon) even It is connected on the top surface of tube core as electrical node.It is 5x 10 with typical doping level¹⁵cm^-3To 1x 10¹⁷cm^-3N-type Extension (epi) layer 150 is being about 1x 10 with typical doping level¹⁸cm^-3To 5x 10¹⁹cm^-3Low resistance weight n+ doped layer On, wherein n+ doped layer be shown by may the large-scale n+ substrates 100 of about 500 μ m-thicks provide.Substrate 100 and epi layer 150 To include silicon, SiGe or another semiconductor material.

Decanting zone contact 128 extends through epi layer 150 (for example, as about 5 μ m-thick of example) and enters the substrate 100.Decanting zone contact 128 is usually usually coated by barrier metals liner 128a.Barrier metals liner 128a include high melting metal layer or High melting metal layer stacks, such as the tin of 800A on the titanium of 600A In a particular embodiment.Barrier metals liner 128a there is also In the bottom of decanting zone contact.

Decanting zone contact 128 is further filled with filler metal 128b together with interior dielectric packing layer 128c, institute Tungsten (W) or the electro-coppering (on copper seed) of filler metal such as chemical vapor deposition (CVD) are stated, the interior dielectric is filled out Silica on the bed of material such as filler metal 128b.The typical thickness range of filler metal 128b is 0.1 μm to 1 μm. Size of the thickness of dielectric filler layer 128c based on decanting zone groove, because dielectric filler layer 128c completes decanting zone groove Filling.In addition to W and copper, filler metal 128b can also include the other metals of such as Ta or such as Pt or Pd platinum family gold Belong to the metal alloy of (PGM), its metal silicide or this metal comprising Ti-W.Decanting zone contact 128 is along decanting zone contact Side wall and bottom formed electrical contact, the decanting zone contact extend through as shown epi layer 150 entrance substrate 100.It is heavy Drop area contact 128 can be round or rectangular shape.

2 horizontal dotted lines shown above substrate 100 in epi layer 150 are provided for instruction dopant (for example, for n The phosphorus or arsenic of+substrate) from substrate 100 diffuse upward into epi layer 150.Although decanting zone contact 128 is shown as reaching substrate 100, but if decanting zone contact 128 is reached close to 150/ substrate of (i.e. in 0.5 μm to 1 μm) epi layer, 100 interface, this It may be enough to provide low resistance, because the part below decanting zone contact 128 of epi layer 150 may be enough heavy doping.

In order to illustrate some benefits of revealed decanting zone contact 128, power nmos transistor is used as example 160.As described above, such as power P MOS transistor or the discrete other transistors of vertical power bipolar transistor can also be used. In addition, as described above, transistor can be discrete device or be a part of IC as shown.Power nmos transistor 160 Source electrode is n-type diffusion region 112.The main body of NMOS transistor 160 is p- trap, is 160 provider region of NMOS transistor (main body) 104.The drain electrode of power nmos transistor 160 is 150 plus substrate 100 of epi layer.Gate-dielectric 108 makes transistor gate The main body 104 of electrode 110 and n-type diffusion region 112, the epi layer 150 of drain electrode and NMOS transistor 160 is electrically isolated.It shows Dielectric isolation layer 106, as LOCOS (local oxidation of silicon) layer or STI (shallow trench isolation) layer, the buffer layer make function Rate NMOS transistor 160 and decanting zone contact 128 are electrically isolated.

Main body 104 is connected to interconnecting line 140 by contact plunger 126.By barrier metal layer 134 (for example, TiN or TaN the contact plunger 126) framed is connected to p-type main body 104 by heavily-doped p-type diffusion region 114.N-type diffusion region 112 is logical It crosses source contact plug 124 and is connected to interconnecting line 138, the interconnecting line and interconnecting line 140 and 142 and all other It may include aluminium or copper that lead, which is equally used as example,.Contact hole 124' to main body 104 is etched through pre-metal dielectrics (PMD) layer 118, the pmd layer usually add the barrier metal layers 134 such as titanium nitride (Ti/TiN) to fill with such as titanium, and Then it is filled with such as CVD-W metal material.

During operation, when the grid for applying enough voltage to power nmos transistor 160 relative to the main body 104 are electric When pole 110, for enhancement device, in the main body 104 at adjacent gate dielectric layer 108 formed channel, and high current from The channel of power nmos transistor 160 is flowed through as the n-type diffusion region 112 of source electrode, and enters 100 region of substrate of drain electrode. It is brilliant by power NMOS when the contact resistance of conventional decanting zone contact is larger due to I=V/R (electric current=voltage/resistance) The electric current that body pipe 160 provides reduces.

Decanting zone contact 128 is shown as extending vertically through pmd layer 118 from the first interconnection layer 142, passes through epi layer 150 Into substrate 100 highly doped as described above.This significantly reduces with the concatenated contact resistance of power nmos transistor 160.Drop Low resistance causes high-power (high current) performance of the power device in this as NMOS transistor 160 to significantly improve.

The simple version of power nmos transistor 160 shown in Fig. 1 is shown as power nmos transistor in Fig. 2 160'.Counter structure in Fig. 1 and Fig. 2 is marked with identical number.Source/body contact 124,124' are by etching source electrode What contact was formed across the n-type diffusion region 112 as source electrode 112 and into p-type main body 104.In this version, make The main body 104 of vertical NMOS transistor 160 is short-circuited to for the n-type diffusion region 112 of source electrode, the transistor makes the main body Diode fails, and reduce the area of MOS transistor.The optional diffusion region p+ as p-type diffusion region 114 can be It is formed under source/body contact 124,124'.Power nmos transistor 160' be it is unidirectional, wherein decanting zone contact 128 is it Drain terminal.

Another simple version of power nmos transistor is shown in Figure 3 for power nmos transistor 160 " in Fig. 1.At this In a version, p- trap contact 126 is separated with source contact 124.Source contact 124 is only as source etch to n-type diffusion region 112, and do not enter main body 104 as in Figure 2.Power nmos transistor 160 " is two-way.Decanting zone contact 128 can be with As low resistance drain contact or low resistance source contact.When Vcc is connected to the n-type diffusion region 112 and Vdd is connected to When the contact 128 of decanting zone, then n-type diffusion region 112 is source electrode and decanting zone contact is the leakage of vertical NMOS transistor 160 " Pole.When Vcc is connected to decanting zone contact 128 and Vdd is connected to n-type diffusion region 112, then decanting zone is connected to source electrode simultaneously And n-type diffusion region 112 is the drain electrode of power nmos transistor 160 ".

The main manufacturing steps of power nmos transistor 160 " shown in Fig. 3 with decanting zone contact 128 are for example following Described in Fig. 4 A to 4C, in deep decanting zone technique, only show to form the first and second deep decanting zones in Fig. 4 D to 4H.It mentions Substrate 100 is supplied, the substrate has an epi layer 150 on it, and described epi layers has and be formed to be included in epi layer 150 And at least one transistor for being covered by pmd layer 118.Using masking layer 120 (for example, photoresist) in PMD 118 It is upper formed include pattern openings 122 the first contact patterns, formed the pattern openings for mos device for source electrode and P trap contact, and emitter and base contact are used for for bipolar devices.For example, then etching contact openings pass through Pmd layer 118 to reach the source electrode of power nmos transistor, and reaches the p+p- trap body contact as shown in Fig. 4 B.

Fig. 4 B shows the NMOS transistor after etching, to form the source contact opening for source contact plug 124 124a is inserted for the body contact opening 124a' of body contact plug 124', and for the body contact as shown in Fig. 4 C The 126a of plug 126.In figure 4 c, individual second decanting zone contact patterns 130 are yet formed on device, at least form one A opening is shown as decanting zone groove 128', wherein decanting zone contact 128 to be formed.Decanting zone groove 128' is etched through Pmd layer 118 across epi layer 150 and normally enters (or almost reaching to) substrate 100.It decanting zone groove 128' and therefore sinks The depth for dropping area contact 128 is typically at least 2 μm, and depends on the thickness of epi layer 150, and the thickness can be 5 or 7 μm Thickness, or it is thicker.Instead of having the only contact area as contact bottom, the contact area of decanting zone contact 128 includes decanting zone The bottom of contact 128 and the entire sidewall areas of decanting zone contact, the entire sidewall areas pass through the complete thickness of epi layer 150 Degree enters substrate 100.As shown in Fig. 4 C, show along the side wall and bottom of decanting zone contact 128 with identical as substrate Doping type (n-type in this example) optional implanted region 132 to add dopant to further decreasing resistance. Then the second contact patterns 130 are removed.

Although it is not shown, above-mentioned barrier metals liner 128a is usually heavy before deposited metal packing material 128b Product is into contact openings, to be usually coated to decanting zone groove 128'.Then deposited metal packing material (temperature: for example, CVD W) 128b, wherein filler metal 128b covers side wall and the bottom of decanting zone groove, but does not fill out completely as shown in Fig. 4 D Fill decanting zone groove.Filler metal 128b be generally filled on the channel bottom of decanting zone < 50% contact area, still Can be provided in any part, as example from 20% to 50% in the range of.Pad oxide is shown below PMD 118 118a。

The deposit dielectrics packing layer 128c on filler metal 128b, wherein dielectric is filled out as shown in Fig. 4 E Bed of material 128c is filled up completely decanting zone groove.Dielectric filler layer 128c may include SOG, tetraethyl orthosilicate (TEOS) or height Density plasma (HDP) CVD, for filling remaining contact after deposited metal packing material 128b (for example, CVD W) Opening.It is considered providing fabulous trench fill performance after hardening when the SOG of liquid form is deposited on chip, to provide burning Tie SOG.Being sintered SOG derived layer has unique micro-structure (for example, compared to CVD oxide) because the layer due to water and Solvent during formation by interconnected pores evaporation have micro-porosity, the hole at surface holding part open, this be because About 1000 DEG C be usually not provided in revealed SOG processing are required heat to remove completely micro-porosity.At one In embodiment, dielectric filler layer 128c includes external CVD liner medium, is such as deposited using TEOS, is different from followed by having The thicker inside of the micro-porosity of CVD oxide is sintered SOG coating.

The covering layer region of dielectric filler layer 128c is removed, is such as returned by dry (for example, plasma) oxide Chemically mechanical polishing (CMP) on the surface of etching or the filler metal 128b by stopping in the covering layer region. Structure caused by oxidation etch back process is shown in Fig. 4 F.Filler metal 128b described in etch-back, described in removing Layer region is covered, the structure of generation is shown in Fig. 4 G.Patterning interconnecting metal layer 170 is shown as being formed to provide interconnection gold Belong to the connection between the filler metal 128b on layer 170 and decanting zone side wall, the structure of generation is shown in Fig. 4 H.

Use the filler metal 128b for being only partially filled with the then decanting zone groove by electrolyte (such as SOG) filling Realize significant wider and deeper decanting zone contact, which overcome use known deep decanting zone contact process especially to work as contact Barrier/metal filling (for example, W) covering significant challenge is contacted when size and depth dramatically increase.Revealed method may be used also To reduce the aspect ratio of decanting zone contact and by the Depth Expansion of decanting zone contact to wide range, and remain as various Different product design demands provides low resistance decanting zone contact.

Plane high power NMOS transistor 500 with revealed decanting zone contact 128 is shown as serving as a contrast in Fig. 5 It is formed on epitaxial layer 150 on bottom 100.In general, the back side of substrate 100 is drain electrode.In some circuits, this present to partly leading The top body device/IC and bottom are provided which electric power and dissipate the heat generated during power nmos transistor 500 operates The problem of heat.

As shown in Figure 5, decanting zone contact 128 is used for heavy doping substrate 100 or other buried type n+ layers of electrical connections To the power supply for using only upper contacts.The source electrode 508 of power nmos transistor 500 is the n-type diffusion region of heavy doping, and main body 506 (for example, p traps) are shorted to source electrode 508 by the p-type diffusion region 504 and contact 516 of heavy doping.It is incited somebody to action when about main body 506 When enough voltage is applied to the gate electrode 505 on gate dielectric 108, in main body 506 under the gate electrode 505 Channel is formed, and electric current flows through n-type drain diffusion regions 510, the doping decanting zone diffusion region 512 n- and is shown as substrate 100 heavy doping n-type layer.

Substrate 100 and n- doping decanting zone diffusion region 512 are connected to top interconnection 522 by decanting zone contact 128.Top is mutual Even 520 it is shown to be coupled to p-type diffusion region 504.Decanting zone contact 128 makes Vcc and Vdd can be from power nmos transistor 500 top supply.Power nmos transistor 500 with decanting zone contact 128 is shown as touching with source/body short circuit The unidirectional NMOS transistor of point.Although Fig. 5 shows the power MOS transistor 500 with decanting zone contact 128, it is same Sample can be illustrated with two-way NMOS high power transistor or one-way or bi-directional PMOS high power transistor well.

Fig. 6 shows the high-power vertical NPN bipolar transistor 600 with revealed decanting zone contact 128.NPN is bis- P-type base diffusion area (p- base stage) 104' that gated transistors 600 include the n-type emitter diffusion 614 of heavy doping, are lightly doped With include the n-type collector Diffusion area that the n-type epi floor 150 of substrate 100 is shown as on the n+ floor of heavy doping.Heavy doping Collector provide low resistance, for handling high current.Decanting zone contact 128 passes through the epi layer 150 being relatively lightly doped and provides Low resistance path significantly improves the performance of npn bipolar transistor 600.Contact plunger 608 provides electrical connection by pmd layer 118 To emitter 614.The contact of contact plunger 610 provides the p-type diffusion region 114 with the heavy doping of p- base stage 104' electrical contact.

Example

Example further illustrates revealed embodiment in detail below, and the example is not necessarily to be construed as in any way It limits the scope of the present disclosure or content.

With a thickness of Example power NMOS transistor is formed on about 5 μm of epi layer on n+ substrate, epi layers and substrate are wrapped Include silicon.It removes to form the sedimentation with perimeter (CD > 3.5um) by decanting zone contact (CT) photoetching process/etching/photoresist Area contact is to form the decanting zone groove that hollow depth (depth in silicon) is about 5.2 μm.Barrier metals liner 128a includes Ti And TiN.Filler metal 128b includes the 7kA W as W-CVD, only partially fills decanting zone groove.Dielectric is filled out Bed of material 128c deposition includes the 5.5kA liner dielectric formed using TEOS depositing operation, followed by the liquid with a thickness of about 2 μm SOG coating, followed by solidification SOG (continuing 40 minutes at 400 DEG C) to provide sintering SOG.Oxide CMP, then internal corrosion W Filler metal 128b, and last aluminium interconnection deposition, and followed by patterning.

Although for high power semiconductor device description revealed low resistance decanting zone contact, this low resistance Decanting zone contact can be formed in any kind of semiconductor device/IC in the low resistance decanting zone that can have benefited from small area On.For example, the common method for reducing contact resistance is formed to multiple contacts of diffusion region or contact array.Sometimes, increase and expand Area's area is dissipated to accommodate multiple contacts.Compared to the array of multiple typical contacts, a kind of revealed low resistance decanting zone contact Lower resistance can be usually provided.Other than lower contact resistance, revealed decanting zone contact makes it possible to forming face The lesser diffusion region of product, the lesser diffusion region of area is also reduced by diode capacitance and is beneficial to circuit performance.

Revealed embodiment can be used for being formed semiconductor element, and the semiconductor element is various comprising being desirably integrated into The discrete tube core or IC tube core of a variety of different devices and Related product are formed in assembling stream.Semiconductor element may include One of the various elements and/or layer thereon, include barrier layer, dielectric layer, apparatus structure, active component and passive element, The passive element includes source region, drain region, bit line, base stage, emitter, collector, conductor wire, conductive hole etc..This Outside, it can be formed from the various techniques comprising bipolar, insulated gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS Semiconductor element.

This disclosure relates to field it should be understood to the one skilled in the art that many other realities within the scope of claims of the present invention It is possible for applying the variant of example and embodiment, and can further be added without departing from the scope of the disclosure Add, delete, substitutions and modifications.