阅读说明：本技术 一种状态可切换的三维三次马匹理疗电路 (Three-dimensional cubic horse physiotherapy circuit that state is changeable ) 是由 武同皓 于 2021-07-28 设计创作，主要内容包括：一种状态可切换的三维三次马匹理疗电路,由三个通道组成,第一通道的输出信号反馈到输入端,作为一路输入信号,该信号的前一级输出信号作为第二通道一路输入信号,且连接第二通道中乘法器A2的输入引脚,还连接第三通道中乘法器A4的输入引脚；第二通道的输出信号的前一级输出连接第一通道中乘法器A3的输入端,同时连接第三通道中的乘法器A4的输入端,第三通道的输出信号反馈到输入端,作为一路输入信号,同时连接第二通道中乘法器A2的输入端,该信号输出的前一级信号连接第一通道连接乘法器A3的输入引脚,同时连接第三通道中乘法器A1的输入端,乘法器A4的输出端连接乘法器A1的另一个输入端；本发明专利为可控混沌马匹理疗电路,电路结构十分简单且易实现,三通道信号均可控等,在马匹理疗以及非线性电路技术等领域有着重要的应用前景。(A three-dimensional cubic horse physical therapy circuit with switchable states comprises three channels, wherein an output signal of a first channel is fed back to an input end to serve as an input signal, a previous-stage output signal of the signal serves as an input signal of a second channel, is connected with an input pin of a multiplier A2 in the second channel and is also connected with an input pin of a multiplier A4 in a third channel; the output of the previous stage of the output signal of the second channel is connected with the input end of the multiplier A3 in the first channel and is also connected with the input end of the multiplier A4 in the third channel, the output signal of the third channel is fed back to the input end to be used as an input signal and is also connected with the input end of the multiplier A2 in the second channel, the previous stage of the signal output is connected with the input pin of the multiplier A3 in the first channel and is also connected with the input end of the multiplier A1 in the third channel, and the output end of the multiplier A4 is connected with the other input end of the multiplier A1; the controllable chaotic physical therapy circuit for the horses is simple and easy to realize in circuit structure, controllable in three-channel signals and the like, and has important application prospects in the fields of physical therapy for the horses, nonlinear circuit technology and the like.)

1. A three-dimensional cubic horse physical therapy circuit with switchable states is composed of three channels and is characterized in that an output signal of a first channel is fed back to an input end to serve as an input signal, a previous-stage output signal of the signal serves as an input signal of a second channel, is connected with an input pin of a multiplier A2 in the second channel and is also connected with an input pin of a multiplier A4 in a third channel; the output of the previous stage of the output signal of the second channel is connected with the input end of the multiplier A3 in the first channel, and is simultaneously connected with the input end of the multiplier A4 in the third channel; the output signal of the third channel is fed back to the input end as an input signal, and is simultaneously connected with the input end of the multiplier A2 in the second channel, the previous-stage signal of the signal output is connected with the input pin of the multiplier A3 connected with the first channel, and is simultaneously connected with the input end of the multiplier A1 in the third channel, and the output end of the multiplier A4 is connected with the other input end of the multiplier A1;

the output signal of the first channel is connected with a resistor R11; a pin 2 of the inverter U1 is connected with a resistor R11, a resistor R12 and a resistor R13, the other end of the resistor R12 is connected with the output end of the multiplier A3, the other end of the resistor R13 is connected with a pin 6 of the inverter U1, and a pin 6 of the inverter U1 is connected with a pin 2 of the inverting integrator U3 through a resistor R14; one end of the capacitor C1 is connected with the 2 pin of the inverse integrator U3, the other end of the capacitor C1 is connected with the 6 pin of the inverse integrator U3, and the 6 pin of the inverse integrator U3 is connected with the 2 pin of the inverter U2 through a resistor R15; a pin 2 of the inverter U2 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with a pin 6 of the inverter U2; the 3 pin of the inverter U1, the 3 pin of the inverter U2 and the 3 pin of the inverse integrator U3 are grounded; the 4 pins of the inverter U1, the 4 pins of the inverter U2 and the 4 pins of the inverse integrator U3 are connected with VDD (negative voltage), the 7 pins of the inverter U1, the 7 pins of the inverter U2 and the 7 pins of the inverse integrator U3 are connected with VCC (positive voltage), the output end of the inverter U2 of the first channel is a signal-x, and the output end of the inverse integrator U3 is a signal x;

the multiplier A2 in the second channel is connected with the 2 pins of the inverter U4 through a resistor R22; the resistor R21 is connected with the pin 2 of the U4 of the inverter, and the pin 2 is connected with the pin 6 of the U4 of the inverter through the resistor R23; pin 6 is connected with a resistor R24, a resistor R24 is connected with pin 2 of the inverse integrator U6, pin 2 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with pin 6 of the inverse integrator U6; the 6 pin of the inverting integrator U6 is connected to the 2 pin of the inverter U5 through a resistor R25; a pin 2 of the inverter U5 is connected with one end of a resistor R26, and the other end of the resistor R26 is connected with a pin 6 of the inverter U5; the 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD (negative voltage), the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC (positive voltage), the output end signal of the second channel inverter U5 is-y, and the output end signal of the second channel inverse integrator U6 is y;

the output end of the multiplier A4 in the third channel is connected with the input end of the multiplier A1, the multiplier A1 is connected to the 2 pin of the inverter U9 through the R35, and the resistor R34 is also connected with the 2 pin of the inverter U9; the inverter U9 is connected with a pin 6 of the inverter U9 through a resistor R36; pin 6 is connected with a resistor R37, a resistor R37 is connected with pin 2 of the inverse integrator U11, pin 2 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with pin 6 of the inverse integrator U11; the 6 pin of the inverting integrator U11 is connected to the 2 pin of the inverter U10 through a resistor R38; a pin 2 of the inverter U10 is connected with one end of a resistor R39, and the other end of the resistor R39 is connected with a pin 6 of the inverter U10; the 3 pin of the inverter U9, the 3 pin of the inverting integrator U11 and the 3 pin of the inverter U10 are grounded; the 4 pins of the inverter U9, the 4 pins of the inverting integrator U11 and the 4 pins of the inverter U10 are connected with VDD (negative voltage), the 7 pins of the inverter U9, the 7 pins of the inverter integrating U11 and the 7 pins of the inverter U10 are connected with VCC (positive voltage), the output end signal of the third channel inverter U10 is-z, and the output end signal of the third channel inverting integrator U11 is z.

2. The three-dimensional cubic horse physiotherapy circuit with switchable states of claim 1, wherein the inverter U1, the inverter U2, the inverting integrator U3, the inverter U4, the inverter U5, the inverting integrator U6, the inverter U9, the inverter U10 and the inverting integrator U11 are all implemented by an operational amplifier LM 741.

3. The three-dimensional cubic horse physiotherapy circuit with switchable states of claim 1, wherein the multiplier A1, the multiplier A2, the multiplier A3 and the multiplier A4 are respectively a multiplier AD 633.

Technical Field

The invention relates to a physical therapy circuit technology for horses, and belongs to the technical field of design of three-dimensional cubic physical therapy circuit devices with switchable states.

Background

At present, horses are mainly used in both equestrian sports and dairy production, and the physical therapy of horses is very important in the fields of equestrian sports, war horses and the like, and directly concerns the health diagnosis problem of horses. The most important horse physiotherapy circuit of the horse physiotherapy instrument needs to abandon the traditional periodic and nonlinear circuits.

A chaotic circuit technology with high complexity is adopted in a horse physiotherapy circuit, most circuits of the existing chaotic circuit technology cannot realize cycle and chaotic switching, and meanwhile, the circuit structure and the resistance parameter are selected when the key part of the state chaotic circuit is switched, the circuit structure is designed, and the initial value is set, which is the key point of many engineers working on physiotherapy circuit design. Meanwhile, the chaotic circuit of the system is designed, so that the control of chaotic signals can be enhanced, and the signal types of rest and movement of the horse can be realized.

The invention aims to solve the problems that the chaotic physical therapy circuit in the prior art is not controlled in state transition, the chaotic system circuit is not easy to design, the initial value is difficult to determine and the like.

Disclosure of Invention

The invention aims to provide a three-dimensional cubic horse physical therapy circuit with switchable states, wherein signals output by a nonlinear system of the three-dimensional cubic horse physical therapy circuit have strong chaotic characteristics, hiding property and the like, the complexity of the system can reach 0.9, and the initial value of the circuit can directly control the complexity.

In order to achieve the purpose, the invention adopts the technical scheme that:

a three-dimensional cubic horse physical therapy circuit with switchable states comprises three channels, wherein an output signal of a first channel is fed back to an input end to serve as an input signal, a previous-stage output signal of the signal serves as an input signal of a second channel, is connected with an input pin of a multiplier A2 in the second channel and is also connected with an input pin of a multiplier A4 in a third channel; the output of the previous stage of the output signal of the second channel is connected with the input end of the multiplier A3 in the first channel, and is simultaneously connected with the input end of the multiplier A4 in the third channel; the output signal of the third channel is fed back to the input end as an input signal, and is simultaneously connected with the input end of the multiplier A2 in the second channel, the previous-stage signal of the signal output is connected with the input pin of the multiplier A3 connected with the first channel, and is simultaneously connected with the input end of the multiplier A1 in the third channel, and the output end of the multiplier A4 is connected with the other input end of the multiplier A1;

the output signal of the first channel is connected with a resistor R11; a pin 2 of the inverter U1 is connected with a resistor R11, a resistor R12 and a resistor R13, the other end of the resistor R12 is connected with the output end of the multiplier A3, the other end of the resistor R13 is connected with a pin 6 of the inverter U1, and a pin 6 of the inverter U1 is connected with a pin 2 of the inverting integrator U3 through a resistor R14; one end of the capacitor C1 is connected with the 2 pin of the inverse integrator U3, the other end of the capacitor C1 is connected with the 6 pin of the inverse integrator U3, and the 6 pin of the inverse integrator U3 is connected with the 2 pin of the inverter U2 through a resistor R15; a pin 2 of the inverter U2 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with a pin 6 of the inverter U2; the 3 pin of the inverter U1, the 3 pin of the inverter U2 and the 3 pin of the inverse integrator U3 are grounded; the 4 pins of the inverter U1, the 4 pins of the inverter U2 and the 4 pins of the inverse integrator U3 are connected with VDD (negative voltage), the 7 pins of the inverter U1, the 7 pins of the inverter U2 and the 7 pins of the inverse integrator U3 are connected with VCC (positive voltage), the output end of the inverter U2 of the first channel is a signal-x, and the output end of the inverse integrator U3 is a signal x;

the multiplier A2 in the second channel is connected with the 2 pins of the inverter U4 through a resistor R22; the resistor R21 is connected with the pin 2 of the U4 of the inverter, and the pin 2 is connected with the pin 6 of the U4 of the inverter through the resistor R23; pin 6 is connected with a resistor R24, a resistor R24 is connected with pin 2 of the inverse integrator U6, pin 2 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with pin 6 of the inverse integrator U6; the 6 pin of the inverting integrator U6 is connected to the 2 pin of the inverter U5 through a resistor R25; the 2 pin of the inverter U5 is connected with one end of a resistor R26, and the other end of the resistor R26 is connected with the 6 pin of the inverter U5. The 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD (negative voltage), the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC (positive voltage), the output end signal of the second channel inverter U5 is-y, and the output end signal of the second channel inverse integrator U6 is y;

the output end of the multiplier A4 in the third channel is connected with the input end of the multiplier A1, the multiplier A1 is connected to the 2 pin of the inverter U9 through the R35, and the resistor R34 is also connected with the 2 pin of the inverter U9. The inverter U9 is connected with a pin 6 of the inverter U9 through a resistor R36; pin 6 is connected with a resistor R37, a resistor R37 is connected with pin 2 of the inverse integrator U11, pin 2 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with pin 6 of the inverse integrator U11; the 6 pin of the inverting integrator U11 is connected to the 2 pin of the inverter U10 through a resistor R38; the 2 pin of the inverter U10 is connected with one end of a resistor R39, and the other end of the resistor R39 is connected with the 6 pin of the inverter U10. The 3 pin of the inverter U9, the 3 pin of the inverting integrator U11 and the 3 pin of the inverter U10 are grounded; the 4 pins of the inverter U9, the 4 pins of the inverting integrator U11 and the 4 pins of the inverter U10 are connected with VDD (negative voltage), the 7 pins of the inverter U9, the 7 pins of the inverter integrating U11 and the 7 pins of the inverter U10 are connected with VCC (positive voltage), the signal of the output end of the third channel inverter U10 is-z, and the signal of the output end of the third channel inverting integrator U11 is z;

the invention can observe the x-y, x-z, y-z phase diagram on the common oscilloscope, has simple circuit structure, reliable circuit performance and easy realization, and is suitable for a physical therapy controllable circuit and the like.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Fig. 2 is a graph of the x-output waveform of fig. 1.

Fig. 3 is a waveform diagram of the y output of fig. 1.

Fig. 4 is a waveform diagram of the z-output of fig. 1.

Fig. 5 is an x-y output phase diagram of fig. 1.

FIG. 6 is an x-z output phase diagram of FIG. 1.

FIG. 7 is a y-z output phase diagram of FIG. 1.

Detailed Description

The invention is described in detail below with reference to the figures and examples.

Referring to fig. 1, a three-dimensional cubic horse physical therapy circuit with switchable states is composed of three channels, an output signal of a first channel is fed back to an input end as an input signal, a previous stage output signal of the signal is used as an input signal of a second channel, and is connected with an input pin of a multiplier a2 in the second channel and also connected with an input pin of a multiplier a4 in a third channel; the output of the previous stage of the output signal of the second channel is connected with the input end of the multiplier A3 in the first channel, and is simultaneously connected with the input end of the multiplier A4 in the third channel; the output signal of the third channel is fed back to the input end as an input signal, and is simultaneously connected with the input end of the multiplier A2 in the second channel, the previous-stage signal of the signal output is connected with the input pin of the multiplier A3 connected with the first channel, and is simultaneously connected with the input end of the multiplier A1 in the third channel, and the output end of the multiplier A4 is connected with the other input end of the multiplier A1;

the output signal of the first channel is connected with a resistor R11; a pin 2 of the inverter U1 is connected with a resistor R11, a resistor R12 and a resistor R13, the other end of the resistor R12 is connected with the output end of the multiplier A3, the other end of the resistor R13 is connected with a pin 6 of the inverter U1, and a pin 6 of the inverter U1 is connected with a pin 2 of the inverting integrator U3 through a resistor R14; one end of the capacitor C1 is connected with the 2 pin of the inverse integrator U3, the other end of the capacitor C1 is connected with the 6 pin of the inverse integrator U3, and the 6 pin of the inverse integrator U3 is connected with the 2 pin of the inverter U2 through a resistor R15; a pin 2 of the inverter U2 is connected with one end of a resistor R16, and the other end of the resistor R16 is connected with a pin 6 of the inverter U2; the 3 pin of the inverter U1, the 3 pin of the inverter U2 and the 3 pin of the inverse integrator U3 are grounded; the 4 pins of the inverter U1, the 4 pins of the inverter U2 and the 4 pins of the inverse integrator U3 are connected with VDD (negative voltage), the 7 pins of the inverter U1, the 7 pins of the inverter U2 and the 7 pins of the inverse integrator U3 are connected with VCC (positive voltage), the output end of the inverter U2 of the first channel is a signal-x, and the output end of the inverse integrator U3 is a signal x;

the multiplier A2 in the second channel is connected with the 2 pins of the inverter U4 through a resistor R22; the resistor R21 is connected with the pin 2 of the U4 of the inverter, and the pin 2 is connected with the pin 6 of the U4 of the inverter through the resistor R23; pin 6 is connected with a resistor R24, a resistor R24 is connected with pin 2 of the inverse integrator U6, pin 2 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with pin 6 of the inverse integrator U6; the 6 pin of the inverting integrator U6 is connected to the 2 pin of the inverter U5 through a resistor R25; the 2 pin of the inverter U5 is connected with one end of a resistor R26, and the other end of the resistor R26 is connected with the 6 pin of the inverter U5. The 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD (negative voltage), the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC (positive voltage), the output end signal of the second channel inverter U5 is-y, and the output end signal of the second channel inverse integrator U6 is y;

the output end of the multiplier A4 in the third channel is connected with the input end of the multiplier A1, the multiplier A1 is connected to the 2 pin of the inverter U9 through the R35, and the resistor R34 is also connected with the 2 pin of the inverter U9. The inverter U9 is connected with a pin 6 of the inverter U9 through a resistor R36; pin 6 is connected with a resistor R37, a resistor R37 is connected with pin 2 of the inverse integrator U11, pin 2 is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with pin 6 of the inverse integrator U11; the 6 pin of the inverting integrator U11 is connected to the 2 pin of the inverter U10 through a resistor R38; the 2 pin of the inverter U10 is connected with one end of a resistor R39, and the other end of the resistor R39 is connected with the 6 pin of the inverter U10. The 3 pin of the inverter U9, the 3 pin of the inverting integrator U11 and the 3 pin of the inverter U10 are grounded; the 4 pins of the inverter U9, the 4 pins of the inverting integrator U11 and the 4 pins of the inverter U10 are connected with VDD (negative voltage), the 7 pins of the inverter U9, the 7 pins of the inverter integrating U11 and the 7 pins of the inverter U10 are connected with VCC (positive voltage), the signal of the output end of the third channel inverter U10 is-z, and the signal of the output end of the third channel inverting integrator U11 is z;

the inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U9, the inverter U10 and the inverse integrator U11 all adopt an operational amplifier LM 741.

The multiplier a1, the multiplier a2, the multiplier A3 and the multiplier a4 adopt a multiplier AD 633.

In fig. 1, the first channel resistance R11 is 20K Ω, the resistance R12 is 100K Ω, the resistance R13 is 10K Ω, the resistance R14 is 10K Ω, the resistance R15 is 1K Ω, the resistance R16 is 1K Ω, and the capacitance C1 is 10 nF; the second channel resistance R21 is 3.3K Ω, the resistance R22 is 2K Ω, the resistance R23 is R24 is 10K Ω, the resistance R25 is 10K Ω, the resistance R26 is 10K Ω, and the capacitance C2 is 10 nF; the third channel resistance R34 ═ 50K Ω, R35 ═ 1K Ω, R36 ═ 10K Ω, R37 ═ R38 ═ R39 ═ 10K Ω, and the capacitance C3 ═ 10 nF; VCC 15, VDD-15V.

The working principle of the invention is as follows:

the chaotic characteristic of the physical therapy circuit for the horses is very complex, and the physical therapy circuit is suitable for two states of horse movement and rest, and certainly provides a relevant model for part of nonlinear control theories. The dimensionless mathematical model involved is as follows:

in the formula (1), x, y and z are state variables, and a, b and c are parameters of the equation. The system (1) is a three-dimensional cubic horse physical therapy circuit with switchable states, and at the moment, the equation of the oscillating circuit disclosed by the invention is as follows:

the circuit related to the invention consists of circuits of a first channel, a second channel and a third channel, and the circuits of the first channel, the second channel and the third channel realize a first function, a second function and a third function in an equation (2) in a time sharing manner. When the analog multiplier uses AD633, the output waveform diagram of the circuit is shown in fig. 2, 3 and 4, the phase diagram of the circuit output is shown in fig. 5, 6 and 7, and the chaotic characteristic of the three-dimensional circuit with controllable line balance point is shown in the diagrams, so that the chaotic type is enriched. The initial value of the circuit can realize the control of the output signal type (period and chaos), and the initial value circuit can be realized by adopting switch switching.