System and method for reducing the loss of power of supply convertor
阅读说明：本技术 用于减少电源变换器的电源损耗的系统和方法 (System and method for reducing the loss of power of supply convertor ) 是由 刘拓夫 翟向坤 方烈义 于 2019-08-29 设计创作，主要内容包括：本公开涉及用于减少电源变换器的电源损耗的系统和方法。用于电源变换器的控制器和方法。例如,用于电源变换器的控制器包括：第一端子,被配置为接收第一端子电压；第二端子,被配置为接收第二端子电压；比较器,被配置为接收第一阈值电压和第二端子电压并且至少部分地基于第一阈值电压和第二端子电压来生成比较信号；和开关,被配置为接收第一端子电压和比较信号,该开关还被配置为在比较信号处于第一逻辑电平时被闭合以允许电流通过开关流出第二端子；其中,比较器还被配置为：在第一端子电压小于第二阈值电压时,接收第一参考电压作为第一阈值电压。(This disclosure relates to the system and method for the loss of power for reducing supply convertor.Controller and method for supply convertor.For example, the controller for supply convertor includes: first terminal, it is configured as receiving first terminal voltage；Second terminal is configured as receiving Second terminal voltage；Comparator is configured as receiving first threshold voltage and Second terminal voltage and is based at least partially on first threshold voltage and Second terminal voltage to generate comparison signal；And switch, it is configured as receiving first terminal voltage and comparison signal, which is additionally configured to be closed when comparison signal is in the first logic level to allow electric current to pass through switch outflow Second terminal；Wherein, comparator is also configured to receive the first reference voltage as first threshold voltage when first terminal voltage is less than second threshold voltage.)
1. a kind of controller for supply convertor, the controller include:
First terminal is configured as receiving first terminal voltage；
Second terminal is configured as receiving Second terminal voltage；
Comparator is configured as receiving first threshold voltage and the Second terminal voltage, and is based at least partially on described First threshold voltage and the Second terminal voltage generate comparison signal；And
Switch, is configured as receiving the first terminal voltage and the comparison signal, the switch is additionally configured to described Comparison signal is closed to allow electric current to flow out the Second terminal by the switch when being in the first logic level；
Wherein, the comparator is also configured to
When the first terminal voltage is less than second threshold voltage, the first reference voltage is received as the first threshold electricity Pressure；With
When the first terminal voltage is greater than the second threshold voltage, the second reference voltage is received as the first threshold Voltage；
Wherein, first reference voltage is greater than second reference voltage；Wherein, the comparator is also configured to
When the first threshold voltage is greater than the Second terminal voltage, the ratio for being in first logic level is generated Compared with signal；With
When the first threshold voltage is less than the Second terminal voltage, generates the comparison in the second logic level and believe Number；
Wherein, second logic level is different from first logic level.
2. controller according to claim 1, in which:
First logic level is logic high；And
Second logic level is logic low.
3. controller according to claim 1, wherein the switch is additionally configured to be in described in the comparison signal It is opened when the second logic level to be not allow current through the switch and flow out the Second terminal.
4. controller according to claim 1, wherein the switch includes transistor, and the transistor is configured as It is switched on when the comparison signal is in first logic level to allow the electric current to pass through described in transistor outflow Second terminal.
5. controller according to claim 4, wherein the transistor is additionally configured to be in institute in the comparison signal It is disconnected when stating the second logic level to be not allow current through the transistor and flow out the Second terminal.
6. controller according to claim 4, wherein the transistor is junction gate field effect transistor.
7. controller according to claim 1, wherein the Second terminal is coupled to capacitor, the capacitor quilt It is configured to receive the electric current from the Second terminal and provides the Second terminal voltage to the Second terminal.
8. a kind of controller for supply convertor, the controller include:
First terminal is configured as receiving first terminal voltage；
Second terminal is configured as receiving Second terminal voltage；
First comparator is configured as receiving first threshold voltage and comparator input voltage, and is based at least partially on institute First threshold voltage and the comparator input voltage are stated to generate the first comparison signal, the first comparator is additionally configured to Described first in the first logic level is generated when the first threshold voltage is greater than the comparator input voltage to compare Signal, and generate when the first threshold voltage is less than the comparator input voltage in described in the second logic level First comparison signal, second logic level are different from first logic level；
First switch is configured as receiving first comparison signal and exports second threshold voltage, and the switch is also matched It is set to and exports the first reference voltage as the second threshold when first comparison signal is in first logic level Voltage, and the second reference voltage is exported as described second when first comparison signal is in second logic level Threshold voltage, second reference voltage are different from first reference voltage；
Second comparator is configured as receiving the second threshold voltage and the Second terminal voltage, and at least partly The second comparison signal is generated based on the second threshold voltage and the Second terminal voltage, second comparator is also matched It is set to and generates second ratio in third logic level when the second threshold voltage is greater than the Second terminal voltage It generates compared with signal, and when the second threshold voltage is less than the Second terminal voltage in described in the 4th logic level Second comparison signal, the 4th logic level are different from the third logic level；And
Second switch, is configured as receiving the first terminal voltage and second comparison signal, the second switch also by It is configured to be closed when second comparison signal is in the third logic level to allow electric current to open by described second It closes and flows out the Second terminal；
Wherein, the comparator input voltage is associated with the first terminal voltage.
9. controller according to claim 8, wherein in the comparator input voltage with the first terminal voltage Increase and when increasing and reducing with the reduction of the first terminal voltage, first reference voltage is greater than described the Two reference voltages.
10. controller according to claim 8, wherein in the comparator input voltage with the first terminal electricity The increase of pressure and when reducing and increasing with the reduction of the first terminal voltage, first reference voltage is less than described Second reference voltage.
11. controller according to claim 8, in which:
First logic level is identical with the third logic level；And
Second logic level is identical with the 4th logic level.
12. controller according to claim 11, in which:
First logic level is logic high；
Second logic level is logic low；
The third logic level is the logic high；And
4th logic level is in the logic low.
13. controller according to claim 8, wherein the second switch is additionally configured to compare letter described second It is opened when number being in four logic level to be not allow current through the second switch and flow out the Second terminal.
14. controller according to claim 8, wherein the second switch includes transistor, and the transistor is configured To be switched on when second comparison signal is in the third logic level to allow the electric current to pass through the transistor Flow out the Second terminal.
15. controller according to claim 14, wherein the transistor is additionally configured in second comparison signal It is disconnected when in four logic level to be not allow current through the transistor and flow out the Second terminal.
16. controller according to claim 14, wherein the transistor is junction gate field effect transistor.
17. controller according to claim 8, wherein the Second terminal is coupled to capacitor, the capacitor quilt It is configured to receive the electric current from the Second terminal and provides the Second terminal voltage to the Second terminal.
18. a kind of method for supply convertor, which comprises
Receive first terminal voltage；
Receive Second terminal voltage；
Receive the Second terminal voltage and first threshold voltage；
The Second terminal voltage and the first threshold voltage are based at least partially on to generate comparison signal；
Receive the first terminal voltage and the comparison signal；And
When the comparison signal is in the first logic level, closure switch are to allow electric current to flow through the switch；
Wherein, the reception Second terminal voltage and first threshold voltage include:
When the first terminal voltage is less than second threshold voltage, the first reference voltage is received as the first threshold electricity Pressure；With
When the first terminal voltage is greater than the second threshold voltage, the second reference voltage is received as the first threshold Voltage；
Wherein, first reference voltage is greater than second reference voltage；Wherein, described to be based at least partially on described second Terminal voltage and the first threshold voltage include: to generate comparison signal
When the first threshold voltage is greater than the Second terminal voltage, the ratio for being in first logic level is generated Compared with signal；With
When the first threshold voltage is less than the Second terminal voltage, generates the comparison in the second logic level and believe Number；
Wherein, second logic level is different from first logic level.
19. according to the method for claim 18, in which:
First logic level is logic high；And
Second logic level is logic low.
20. according to the method for claim 18, further includes:
When the comparison signal is in second logic level, the switch is opened not allow electric current to flow through described open It closes.
21. according to the method for claim 18, further includes:
The electric current is received by capacitor；And
The Second terminal voltage is provided by the capacitor.
22. a kind of method for supply convertor, which comprises
Receive first terminal voltage；
Receive Second terminal voltage；
Receive first threshold voltage and comparator input voltage；
The first threshold voltage and the comparator input voltage are based at least partially on to generate the first comparison signal, it is described The first threshold voltage and the comparator input voltage, which are based at least partially on, to generate the first comparison signal includes:
When the first threshold voltage is greater than the comparator input voltage, generates and be in described the first of the first logic level Comparison signal；With
When the first threshold voltage is less than the comparator input voltage, generates and be in described the first of the second logic level Comparison signal, second logic level are different from first logic level；
Receive first comparison signal；
First comparison signal is based at least partially on to export second threshold voltage, it is described to be based at least partially on described One comparison signal includes: to export second threshold voltage
When first comparison signal is in first logic level, the first reference voltage is exported as the second threshold Voltage；With
When first comparison signal is in second logic level, the second reference voltage is exported as the second threshold Voltage, second reference voltage are different from first reference voltage；
Receive the second threshold voltage and the Second terminal voltage；
The second threshold voltage and the Second terminal voltage are based at least partially on to generate the second comparison signal, it is described extremely The second threshold voltage and the Second terminal voltage, which are at least partly based on, to generate the second comparison signal includes:
When the second threshold voltage is greater than the Second terminal voltage, second ratio in third logic level is generated Compared with signal；With
When the second threshold voltage is less than the Second terminal voltage, second ratio in the 4th logic level is generated Compared with signal, the 4th logic level is different from the third logic level；
Receive the first terminal voltage and second comparison signal；And
When second comparison signal is in the third logic level, closure switch are to allow electric current to flow through the switch；
Wherein, the comparator input voltage is associated with the first terminal voltage.
23. according to the method for claim 22, wherein in the comparator input voltage with the first terminal voltage Increase and when increasing and reducing with the reduction of the first terminal voltage, first reference voltage is greater than described the Two reference voltages.
24. according to the method for claim 22, wherein in the comparator input voltage with the first terminal voltage Increase and when reducing and increasing with the reduction of the first terminal voltage, first reference voltage is less than described the Two reference voltages.
25. according to the method for claim 22, in which:
First logic level is identical with the third logic level；And
Second logic level is identical with the 4th logic level.
26. according to the method for claim 25, in which:
First logic level is logic high；
Second logic level is logic low；
The third logic level is the logic high；And
4th logic level is in the logic low.
27. according to the method for claim 22, further includes:
When second comparison signal is in four logic level, it is described not allow electric current to flow through to open the switch Switch.
28. according to the method for claim 22, further includes:
The electric current is received by capacitor；And
The Second terminal voltage is provided by the capacitor.
Technical field
Certain embodiments of the present invention is related to integrated circuit.It is used for more specifically, some embodiments of the present invention provide The system and method for reducing the loss of power of supply convertor.
Background technique
Supply convertor is widely used in consumption electronic product (for example, portable device).Supply convertor can be by electric power Another form is converted to from a kind of form.As an example, electric power is converted to direct current (DC) from exchange (AC), is converted to from DC AC, AC is converted to from AC or is converted to DC from DC.In addition, supply convertor electric power can be converted to from a voltage it is another Voltage.Supply convertor includes linear quantizer and switched-mode converter.
Many traditional supply convertors include power management chip.Some power management chips use low-voltage power supply, one A little power management chips use high voltage supply.It is not usually required to using the power management chip of high voltage supply using additional starting And power supply device；Therefore, these power management chips can usually reduce the cost and volume of supply convertor.
Fig. 1 is the simplification figure for showing traditional AC-DC supply convertor.Supply convertor 100 include: diode 102,104, 106,108 and 134；Capacitor 110,132 and 136；Resistor 114；Controller 120；Inductor 138；With switch 160.Control Device 120 (for example, chip) includes terminal 122,124,126,128 and 130 (for example, pin).In addition, controller 120 (for example, Chip) include voltage control module 140 (for example, VDD control module), under-voltage locking module 142 (for example, UVLO module), go Magnetic testi module 144, constant current and/or constant voltage adjustment module 146 (for example, CC/CV adjustment module), current sense mould Block 148, protective module 150, modulation control module 152 and driver 154.In addition, capacitor 136 includes terminal 116 and 118. For example, supply convertor 100 is AC-DC buck converter.
In some instances, switch 160 is transistor.In some examples, modulation control module 152 is pulse width tune Make (PWM) control module.According to some embodiments, supply convertor 100 provides output electric current and/or output electricity to load 190 Pressure.According to some embodiments, capacitor 136 be include the polarized capacitor of anode terminal 116 and cathode terminal 118, and sun Extreme son 116 is connected to terminal 128.
As shown in Figure 1, capacitor 132 provides voltage 166 (for example, V to controller 120 by terminal 130DD), and control Device 120 processed receives voltage 162 also at terminal 128.Capacitor 110 provides voltage 112 (for example, VIN), it is equal to voltage 162, And the anode terminal 116 of polarized capacitor 136 is also biased in voltage 162.
Fig. 2 is the simplification figure for showing another tradition AC-DC supply convertor.Supply convertor 200 include: diode 202, 204,206,208 and 234；Capacitor 210,232 and 236；Resistor 214；Controller 220；Inductor 238；With switch 260. Controller 220 (for example, chip) includes terminal 222,224,226,228 and 230 (for example, pin).In addition, 220 (example of controller Such as, chip) include voltage control module 240 (for example, VDD control module), under-voltage locking module 242 (for example, UVLO module), Demagnetization detection module 244, constant current and/or constant voltage adjustment module 246 (for example, CC/CV adjustment module), current sense Module 248, protective module 250, modulation control module 252 and driver 254.In addition, capacitor 236 includes 216 He of terminal 218.For example, supply convertor 200 is AC-DC buck-boost converter.
In some instances, switch 260 is transistor.In some examples, modulation control module 252 is pulse width tune Make (PWM) control module.According to some embodiments, supply convertor 200 provides output electric current and/or output electricity to load 290 Pressure.According to some embodiments, capacitor 236 be include the polarized capacitor of anode terminal 216 and cathode terminal 218, and sun Extreme son 216 is connected to terminal 228.
As shown in Fig. 2, capacitor 232 provides voltage 266 (for example, V to controller 220 by terminal 230DD), and control Device 220 processed receives voltage 262 also at terminal 228.Capacitor 210 provides voltage 212 (for example, VIN), and polarized capacitor 236 anode terminal 216 is biased in voltage 262.
Fig. 3 is the simplification figure for showing at least some of module of traditional AC-DC supply convertor.Certain of supply convertor 300 A little modules include: diode 302,304,306 and 308；Capacitor 310 and 332；And controller 320.320 (example of controller Such as, chip) certain module include terminal 326,328 and 330 (for example, pin) and voltage control module 340 (for example, VDD is controlled Molding block).As shown in figure 3, voltage control module 340 includes junction gate field effect transistor (JFET) 380, diode 382 With comparator 384.In some examples, supply convertor 300 is supply convertor 100, is, for example, AC-DC decompression transformation Device.In some instances, supply convertor 300 is supply convertor 200, is, for example, AC-DC buck-boost converter.
As shown in figure 3, JFET 380 includes drain terminal 390, source terminal 392 and gate terminal 394, and comparator 384 include input terminal 370 and 372 and output terminal 374.Capacitor 332 provides electricity to controller 320 by terminal 330 Pressure 366 is (for example, VDD), and controller 320 receives voltage 362 (for example, V also at terminal 328HV).In addition, capacitor 310 Voltage 312 is provided (for example, VIN)。
According to some embodiments, supply convertor 300 is identical as supply convertor 100.In some instances, diode 302,304,306 and 308 is identical as diode 102,104,106 and 108 respectively, capacitor 310 and 332 respectively with capacitor 110 and 132 is identical, and controller 320 is identical as controller 120.In some examples, terminal 326,328 and 330 respectively with Terminal 126,128 and 130 identical, and voltage control module 340 is identical as voltage control module 140.In some instances, electric Pressure 366 is (for example, VDD) with voltage 166 (for example, VDD) identical, voltage 362 is identical as voltage 162, and voltage 312 (for example, VIN) with voltage 112 (for example, VIN) identical.
According to some embodiments, supply convertor 300 is identical as supply convertor 200.In some instances, diode 302,304,306 and 308 is identical as diode 202,204,206 and 208 respectively, capacitor 310 and 332 respectively with capacitor 210 and 232 is identical, and controller 320 is identical as controller 220.In some examples, terminal 326,328 and 330 respectively with Terminal 226,228 and 230 identical, and voltage control module 340 is identical as voltage control module 240.In some instances, electric Pressure 366 is (for example, VDD) with voltage 266 (for example, VDD) identical, voltage 362 is identical as voltage 262, and voltage 312 (for example, VIN) with voltage 212 (for example, VIN) identical.
As shown in figure 3, comparator 384 receives voltage 364 (for example, V at terminal 370REF) and connect at terminal 372 Voltage 366 is received (for example, VDD), and the output signal 368 at terminal 374.Voltage 366 is (for example, VDD) led to by capacitor 332 The offer of terminal 330 is crossed, and signal 368 is received by the gate terminal 394 of JFET 380.Voltage control module 340 is configured as Keep voltage 366 (for example, VDD) stablize in voltage 364 (for example, VREF) near.
If voltage 366 is (for example, VDD) it is lower than voltage 364 (for example, VREF), then signal 368 be in logic high and JFET 380 is connected by signal 368.When JFET 380 is switched on, electric current 396 is (for example, IJFET) it is greater than zero, and electric current 396 Flow through JFET 380, diode 382 and terminal 330, and charge to capacitor 332 with increase voltage 366 (for example, VDD).If voltage 366 is (for example, VDD) it is higher than voltage 364 (for example, VREF), then signal 368 be in logic low and JFET 380 is disconnected by signal 368.When JFET 380 is disconnected, electric current 396 is (for example, IJFET) it is equal to zero, and electric current 396 It does not charge to capacitor 332.
As shown in Figure 1, Figure 2 and Figure 3, supply convertor can usually be reduced using the power management chip of high voltage supply Cost and volume, but they can generally also reduce the system effectiveness of supply convertor.Therefore, it needs to improve using high voltage supply The technology of power management chip.
Summary of the invention
Certain embodiments of the present invention is related to integrated circuit.It is used for more specifically, some embodiments of the present invention provide The system and method for reducing the loss of power of supply convertor.Only by way of example, some embodiments of the present invention have been Applied to the supply convertor with high voltage supply.But it is to be understood that the present invention has the wider scope of application.
According to some embodiments, a kind of controller for supply convertor includes: first terminal, is configured as reception One terminal voltage；Second terminal is configured as receiving Second terminal voltage；Comparator is configured as receiving first threshold voltage With Second terminal voltage, and first threshold voltage and Second terminal voltage are based at least partially on to generate comparison signal；With And switch, it is configured as receiving first terminal voltage and comparison signal, which is additionally configured to be in first in comparison signal It is closed when logic level to allow electric current to pass through switch outflow Second terminal；Wherein, comparator is also configured in first end When sub- voltage is less than second threshold voltage, the first reference voltage is received as first threshold voltage；And in first terminal voltage When greater than second threshold voltage, the second reference voltage is received as first threshold voltage；Wherein, the first reference voltage is greater than second Reference voltage；Wherein, comparator is also configured to generate when first threshold voltage is greater than Second terminal voltage and be in first The comparison signal of logic level；And it when first threshold voltage is less than Second terminal voltage, generates and is in the second logic level Comparison signal；Wherein, the second logic level is different from the first logic level.
According to some embodiments, a kind of controller for supply convertor includes: first terminal, is configured as reception One terminal voltage；Second terminal is configured as receiving Second terminal voltage；First comparator is configured as receiving first threshold Voltage and comparator input voltage and first threshold voltage and comparator input voltage are based at least partially on to generate first Comparison signal, first comparator are additionally configured to generate when first threshold voltage is greater than comparator input voltage and patrol in first The first comparison signal of level is collected, and is generated when first threshold voltage is less than comparator input voltage in the second logic electricity The first flat comparison signal, the second logic level are different from the first logic level；First switch is configured as reception first and compares Signal and second threshold voltage is exported, which is additionally configured to the output when the first comparison signal is in the first logic level First reference voltage is as second threshold voltage, and the second reference of output when the first comparison signal is in the second logic level Voltage is different from the first reference voltage as second threshold voltage, the second reference voltage；Second comparator is configured as reception Two threshold voltages and Second terminal voltage, and second threshold voltage and Second terminal voltage are based at least partially on to generate Two comparison signals, the second comparator are additionally configured to generate when second threshold voltage is greater than Second terminal voltage and patrol in third The second comparison signal of level is collected, and is generated when second threshold voltage is less than Second terminal voltage and is in the 4th logic level The second comparison signal, the 4th logic level be different from third logic level；And second switch, it is configured as receiving first end Sub- voltage and the second comparison signal, second switch are additionally configured to be closed when the second comparison signal is in third logic level To allow electric current to flow out Second terminal by second switch；Wherein, comparator input voltage is associated with first terminal voltage.
According to some embodiments, a kind of method for supply convertor includes: to receive first terminal voltage；Receive second Terminal voltage；Receive Second terminal voltage and first threshold voltage；It is based at least partially on Second terminal voltage and first threshold Voltage generates comparison signal；Receive first terminal voltage and comparison signal；And the first logic level is in comparison signal When, closure switch are to allow electric current to flow through switch；Wherein, it receives Second terminal voltage and first threshold voltage includes: first When terminal voltage is less than second threshold voltage, the first reference voltage is received as first threshold voltage；And in first terminal electricity When pressure is greater than second threshold voltage, the second reference voltage is received as first threshold voltage；Wherein, the first reference voltage is greater than the Two reference voltages；Wherein, Second terminal voltage and first threshold voltage are based at least partially on to generate comparison signal include: In When first threshold voltage is greater than Second terminal voltage, the comparison signal for being in the first logic level is generated；And in first threshold When voltage is less than Second terminal voltage, the comparison signal for being in the second logic level is generated；Wherein, the second logic level is different from First logic level.
According to some embodiments, a kind of method for supply convertor includes: to receive first terminal voltage；Receive second Terminal voltage；Receive first threshold voltage and comparator input voltage；And it is based at least partially on first threshold voltage and ratio The first comparison signal is generated compared with device input voltage.For example, being based at least partially on first threshold voltage and comparator input electricity Pressure come generate the first comparison signal include: first threshold voltage be greater than comparator input voltage when, generate be in the first logic First comparison signal of level；And when first threshold voltage is less than comparator input voltage, generate in the second logic electricity The first flat comparison signal, the second logic level are different from the first logic level.In some instances, this method further include: connect Receive the first comparison signal；And the first comparison signal is based at least partially on to export second threshold voltage.For example, at least partly Ground exported based on the first comparison signal second threshold voltage include: when the first comparison signal is in the first logic level, it is defeated The first reference voltage is as second threshold voltage out；And when the first comparison signal is in the second logic level, output second Reference voltage is different from the first reference voltage as second threshold voltage, the second reference voltage.In some examples, this method is also It include: to receive second threshold voltage and Second terminal voltage；And it is based at least partially on second threshold voltage and Second terminal Voltage generates the second comparison signal.For example, being based at least partially on second threshold voltage and Second terminal voltage to generate Two comparison signals include: to generate the second ratio in third logic level when second threshold voltage is greater than Second terminal voltage Compared with signal；And when second threshold voltage is less than Second terminal voltage, generates second in the 4th logic level and compare letter Number, the 4th logic level is different from third logic level.In some instances, this method further include: receive first terminal voltage With the second comparison signal；And when the second comparison signal is in third logic level, closure switch are to allow electric current to flow through out It closes.For example, comparator input voltage is associated with first terminal voltage.
According to embodiment, one or more benefits may be implemented.With reference to following detailed description and drawings, can sufficiently manage Solve these benefits and various additional objects, features and advantages of the invention.
Detailed description of the invention
Fig. 1 is the simplification figure for showing traditional AC-DC supply convertor.
Fig. 2 is the simplification figure for showing another tradition AC-DC supply convertor.
Fig. 3 is the simplification figure for showing at least some of module of traditional AC-DC supply convertor.
Fig. 4 is the simplified timing diagram according to the supply convertor as shown in Figure 3 of some embodiments.
Fig. 5 is the simplification figure for showing AC-DC supply convertor according to some embodiments of the present invention.
Fig. 6 is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.
Fig. 7 is the simplification for showing at least some of module of AC-DC supply convertor according to some embodiments of the present invention Figure.
Fig. 8 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.
Fig. 8 B is the simplified timing diagram of supply convertor as shown in Figure 8 A according to some embodiments of the present invention.
Fig. 9 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.
Fig. 9 B is the simplified timing diagram of supply convertor as shown in Figure 9 A according to some embodiments of the present invention.
Figure 10 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.
Figure 10 B is the simplified timing diagram of supply convertor as shown in Figure 10 A according to some embodiments of the present invention.
Figure 11 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.
Figure 11 B is the simplified timing diagram of supply convertor as shown in Figure 11 A according to some embodiments of the present invention.
Figure 12 is the simplified timing diagram of supply convertor as shown in Figure 7 according to some embodiments of the present invention.
Figure 13 is the simplified timing diagram of supply convertor as shown in Figure 7 according to some embodiments of the present invention.
Figure 14 is the simplified timing diagram of supply convertor as shown in Figure 7 according to certain embodiments of the present invention.
Specific embodiment
Certain embodiments of the present invention is related to integrated circuit.It is used for more specifically, some embodiments of the present invention provide The system and method for reducing the loss of power of supply convertor.Only by way of example, some embodiments of the present invention have been Applied to the supply convertor using high voltage supply.But it is to be understood that the present invention has the wider scope of application.
Fig. 4 is the simplified timing diagram according to the supply convertor 300 as shown in Figure 3 of some embodiments.Waveform 466 indicates The voltage 366 changed over time is (for example, VDD), waveform 462 indicates the voltage 362 changed over time (for example, VHV), and wave Shape 496 indicates the electric current 396 changed over time (for example, IJFET).For example, supply convertor 300 is supply convertor 100, and And voltage 362 is (for example, VHV) it is equal to voltage 312 (for example, VIN)。
In some instances, as shown in waveform 466, voltage 366 is (for example, VDD) voltage 364 is adjusted in (for example, VREF) Near.In some examples, as shown in waveform 496, electric current 396 is (for example, IJFET) maximum value be equal to junction gate field-effect The maximum current that transistor (JFET) 380 can provide is (for example, IJFET_MAX).In some instances, electric current 396 (for example, IJFET) average value be equal to controller 320 (for example, chip) operating current (for example, IIC)。
According to some embodiments, as shown in figure 4, when JFET 380 is connected, from drain terminal 390 to source terminal 392 Voltage drop it is very big.For example, the loss of power as caused by the voltage drop is about are as follows:
Wherein, PHV_LossIt indicates as from drain terminal 390 to the loss of power caused by the voltage drop of source terminal 392.Separately Outside, VHVIndicate voltage 362, and IICIt indicates the operating current of controller 320, is equal to the electric current 396 according to some embodiments Average value.
In some embodiments, as in equationi, if VHVIncrease, then PHV_LossAlso increase.For example, by from drain electrode end The loss of power caused by 390 voltage drop to source terminal 392 of son is converted into heat, which increase controller 320 (for example, Chip) temperature and reduce the system effectiveness of supply convertor 300.
Fig. 5 is the simplification figure for showing AC-DC supply convertor according to some embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 500 includes: diode 502,504,506,508 and 534；Capacitor 510,532 and 536；Resistor 514； Controller 520；Inductor 538；With switch 560.Controller 520 (for example, chip) includes 522,524,526,528 and of terminal 530 (for example, pins).In addition, controller 520 (for example, chip) includes voltage control module 540 (for example, VDD controls mould Block), under-voltage locking module 542 (for example, UVLO module), demagnetization detection module 544, constant current and/or constant voltage adjust Module 546 (for example, CC/CV adjustment module), current sensing module 548, protective module 550, modulation control module 552 and driving Device 554.In addition, capacitor 536 includes terminal 516 and 518.For example, supply convertor 500 is AC-DC buck converter.
In some instances, switch 560 is transistor.In some examples, modulation control module 552 is pulse width tune Make (PWM) control module.According to some embodiments, supply convertor 500 provides output electric current and/or output electricity to load 590 Pressure.According to some embodiments, capacitor 536 be include the polarized capacitor of anode terminal 516 and cathode terminal 518, and sun Extreme son 516 is connected to terminal 528.
As shown in figure 5, capacitor 532 provides voltage 566 to controller 520 by terminal 530 according to some embodiments (for example, VDD), and controller 520 receives voltage 562 (for example, V also at terminal 528HV).For example, capacitor 510 provides Voltage 512 is (for example, VIN), it is equal to voltage 562, and the anode terminal 516 of polarized capacitor 536 is also biased in voltage At 562.As an example, voltage control module 540 is realized according to voltage control module 740 as shown in Figure 7.
Fig. 6 is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 600 includes: diode 602,604,606,608 and 634；Capacitor 610,632 and 636；Resistor 614； Controller 620；Inductor 638；With switch 660.Controller 620 (for example, chip) includes 622,624,626,628 and of terminal 630 (for example, pins).In addition, controller 620 (for example, chip) includes voltage control module 640 (for example, VDD controls mould Block), under-voltage locking module 642 (for example, UVLO module), demagnetization detection module 644, constant current and/or constant voltage adjust Module 646 (for example, CC/CV adjustment module), current sensing module 648, protective module 650, modulation control module 652 and driving Device 654.In addition, capacitor 636 includes terminal 616 and 618.For example, supply convertor 600 is AC-DC buck-boost converter.
In some instances, switch 660 is transistor.In some examples, modulation control module 652 is pulse width tune Make (PWM) control module.According to some embodiments, supply convertor 600 provides output electric current and/or output electricity to load 690 Pressure.According to some embodiments, capacitor 636 be include the polarized capacitor of anode terminal 616 and cathode terminal 618, and sun Extreme son 616 is connected to terminal 628.
As shown in fig. 6, capacitor 632 provides voltage 666 to controller 620 by terminal 630 according to some embodiments (for example, VDD), and controller 620 receives voltage 662 also at terminal 628.In some instances, capacitor 610 provides electricity Pressure 612 is (for example, VIN), and the anode terminal 616 of polarized capacitor 636 is biased at voltage 662.As an example, voltage Control module 640 is realized according to voltage control module 740 as shown in Figure 7.
Fig. 7 is the simplification for showing at least some of module of AC-DC supply convertor according to some embodiments of the present invention Figure.The figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many Variation, substitutions and modifications.The certain module of supply convertor 700 includes: diode 702,704,706 and 708；Capacitor 710 With 732；With controller 720.The certain module of controller 720 (for example, chip) includes terminal 726,728 and 730 (for example, drawing Foot) and voltage control module 740 (for example, VDD control module).As shown in fig. 7, voltage control module 740 include switch 776, Junction gate field effect transistor (JFET) 780, diode 782 and comparator 784 and 786.In some examples, power supply becomes Parallel operation 700 is supply convertor 500, is, for example, AC-DC buck converter.In some instances, supply convertor 700 is electricity Source converter 600 is, for example, AC-DC buck-boost converter.
As shown in fig. 7, JFET 780 includes drain terminal 790, source terminal 792 and gate terminal according to some embodiments Son 794, comparator 784 includes input terminal 770 and 772 and output terminal 774, and comparator 786 includes input terminal 787 and 788 and output terminal 789.In some instances, capacitor 732 provides voltage to controller 720 by terminal 730 766 (for example, VDD), and controller 720 receives voltage 762 (for example, V also at terminal 728HV).In some examples, electric Container 710 provides voltage 712 (for example, VIN)。
According to some embodiments, supply convertor 700 is identical as supply convertor 500.In some instances, diode 702,704,706 and 708 is identical as diode 502,504,506 and 508 respectively, capacitor 710 and 732 respectively with capacitor 510 and 532 is identical, and controller 720 is identical as controller 520.In some examples, terminal 726,728 and 730 respectively with Terminal 526,528 and 530 identical, and voltage control module 740 is identical as voltage control module 540.In some instances, electric Pressure 766 is (for example, VDD) with voltage 566 (for example, VDD) identical, voltage 762 is identical as voltage 562, and voltage 712 (for example, VIN) with voltage 512 (for example, VIN) identical.
According to some embodiments, supply convertor 700 is identical as supply convertor 600.In some instances, diode 702,704,706 and 708 is identical as diode 602,604,606 and 608 respectively, capacitor 710 and 732 respectively with capacitor 610 and 632 is identical, and controller 720 is identical as controller 620.In some examples, terminal 726,728 and 730 respectively with Terminal 626,628 and 630 identical, and voltage control module 740 is identical as voltage control module 640.In some instances, electric Pressure 766 is (for example, VDD) with voltage 666 (for example, VDD) identical, voltage 762 is identical as voltage 662, and voltage 712 (for example, VIN) with voltage 612 (for example, VIN) identical.
In some embodiments, comparator 786 receives signal 797 (for example, V at input terminal 787TH), in input terminal Signal 798 is received at son 788 (for example, VREP), and the output signal 799 at output terminal 789.In some examples, if Signal 797 is (for example, VTH) it is greater than signal 798 (for example, VREP), then signal 799 is in logic high.In some instances, such as Fruit signal 797 is (for example, VTH) it is less than signal 798 (for example, VREP), then signal 799 is in logic low.In some embodiments In, signal 799 is received by switch 776.In some instances, if signal 799 is in logic high, switch 776 will be electric Pressure 764 is (for example, VREF1) be connected to the input terminal 770 of comparator 784, and comparator 784 by voltage 764 (for example, VREF1) Receive input terminal 770.In some examples, if signal 799 is in logic low, switch 776 is by voltage 765 (for example, VREF2) be connected to the input terminal 770 of comparator 784, and comparator 784 by voltage 765 (for example, VREF2) receive To input terminal 770.In some instances, comparator 784 receives voltage 766 (for example, V also at terminal 772DD) and in terminal Output signal 768 at 774.
According to some embodiments, if signal 799 is in logic high, comparator 784 receives electricity at terminal 770 Pressure 764 is (for example, VREF1), voltage 766 is received at terminal 772 (for example, VDD), and the output signal 768 at terminal 774. For example, if voltage 766 is (for example, VDD) it is less than voltage 764 (for example, VREF1), then signal 768 is in logic high.Another In one example, if voltage 766 is (for example, VDD) it is greater than voltage 764 (for example, VREF1), then signal 768 is in logic low. In some examples, voltage 766 is (for example, VDD) provided by capacitor 732 by terminal 730, and signal 768 is by JFET 780 Gate terminal 794 receive.In some instances, voltage control module 740 is configured as keeping voltage 766 (for example, VDD) In Voltage 764 is (for example, VREF1) nearby stablize.For example, voltage 766 is (for example, VDD) voltage 764 is adjusted in (for example, VREF1) attached Closely.
According to some embodiments, if signal 799 is in logic low, comparator 784 receives electricity at terminal 770 Pressure 765 is (for example, VREF2), voltage 766 is received at terminal 772 (for example, VDD), and the output signal 768 at terminal 774. For example, if voltage 766 is (for example, VDD) it is less than voltage 765 (for example, VREF2), then signal 768 is in logic high.Another In one example, if voltage 766 is (for example, VDD) it is greater than voltage 765 (for example, VREF2), then signal 768 is in logic low. In some examples, voltage 766 is (for example, VDD) provided by capacitor 732 by terminal 730, and signal 768 is by JFET 780 Gate terminal 794 receive.In some instances, voltage control module 740 is configured as keeping voltage 766 (for example, VDD) steady Voltage 765 is scheduled on (for example, VREF2) near.For example, voltage 766 is (for example, VDD) voltage 765 is adjusted in (for example, VREF2) attached Closely.
According to some embodiments, if signal 768 is in logic high, JFET 780 is connected by signal 768.One In a little examples, when JFET 780 is connected, electric current 796 is (for example, IJFET) it is greater than zero, and electric current 796 flows through JFET 780, two Pole pipe 782 and terminal 730, and charged to capacitor 732 to increase voltage 766 (for example, VDD).According to certain implementations Example, if signal 768 is in logic low, JFET 780 is disconnected by signal 768.In some examples, as JFET 780 When disconnection, electric current 796 is (for example, IJFET) it is equal to zero, and electric current 796 does not charge to capacitor 732.
As shown in fig. 7, generating signal 798 (for example, V according to some embodimentsREP) to indicate voltage 762 (for example, VHV) Size.In some embodiments, signal 798 is (for example, VREP) with voltage 762 (for example, VHV) proportional (for example, directly proportional), And voltage 765 is (for example, VREF2) it is less than voltage 764 (for example, VREF1).For example, signal 798 is (for example, VREP) with voltage 762 (for example, VHV) increase and increase, and as voltage 762 is (for example, VHV) reduction and reduce, and voltage 765 (for example, VREF2) it is less than voltage 764 (for example, VREF1).In certain embodiments, voltage 798 is (for example, VREP) and voltage 762 (for example, VHV) be inversely proportional, and voltage 765 is (for example, VREF2) it is greater than voltage 764 (for example, VREF1).For example, signal 798 is (for example, VREP) As voltage 762 is (for example, VHV) reduction and increase, and as voltage 762 is (for example, VHV) increase and reduce, and electricity Pressure 765 is (for example, VREF2) it is greater than voltage 764 (for example, VREF1)。
In some embodiments, signal 798 is (for example, VREP) generated by divider, and with voltage 762 (for example, VHV) at Ratio (for example, directly proportional), for example, as shown in Fig. 8 A and/or Fig. 8 B.In certain embodiments, signal 798 is (for example, VREP) by Current-sense resistor generates, and with voltage 762 (for example, VHV) proportional (for example, directly proportional), for example, such as Fig. 9 A and/or Shown in Fig. 9 B.In some embodiments, signal 798 is (for example, VREP) generated by auxiliary winding, and in amplitude with voltage 762 (for example, VHV) proportional (for example, directly proportional), for example, as shown in Figure 10 A and/or Figure 10 B.In certain embodiments, signal 798 (for example, VREP) generated by driver, and with voltage 762 (for example, VHV) be inversely proportional, for example, such as Figure 11 A and/or Figure 11 B It is shown.
Fig. 8 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 800 includes: diode 502,504,506,508 and 534；Capacitor 510,532 and 536；Resistor 514； Controller 520；Inductor 538；With switch 560.Controller 520 (for example, chip) includes 522,524,526,528 and of terminal 530 (for example, pins).In addition, controller 520 (for example, chip) includes voltage control module 540 (for example, VDD controls mould Block), under-voltage locking module 542 (for example, UVLO module), demagnetization detection module 544, constant current and/or constant voltage adjust Module 546 (for example, CC/CV adjustment module), current sensing module 548, protective module 550, modulation control module 552 and driving Device 554.In addition, capacitor 536 includes terminal 516 and 518.In some examples, supply convertor 800 and supply convertor 500 is identical, and supply convertor 500 is identical as supply convertor 700.In some instances, voltage control module 540 and electricity Press control module 740 identical.For example, supply convertor 800 is AC-DC buck converter.
As shown in Figure 8 A, according to some embodiments, supply convertor 800 further includes resistor 810 and 820, and is controlled Device 520 (for example, chip) further includes terminal 830 (for example, pin).In some instances, resistor 810 includes 812 He of terminal 814, and resistor 820 includes terminal 822 and 824.In some examples, terminal 812 receives voltage 512 (for example, VIN), Equal to voltage 562, and terminal 814 is connected to terminal 822.In some instances, terminal 814 and 822 generates 898 (example of voltage Such as, VDIV), it is received by controller 520 in terminal 830 and by controller 520 for generating signal 798 (for example, VREP)。 For example, signal 798 is (for example, VREP) with voltage 898 (for example, VDIV) identical.
Fig. 8 B is the simplified timing diagram of supply convertor 800 as shown in Figure 8 A according to some embodiments of the present invention. The figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many changes Change, substitutions and modifications.Waveform 830 indicates the voltage 562 changed over time (for example, VHV), and the expression of waveform 840 becomes at any time The voltage 898 of change is (for example, VDIV)。
In certain embodiments, voltage 562 is (for example, VHV) it is equal to voltage 512 (for example, VIN), and change over time, As shown in waveform 830.In some embodiments, voltage 898 is (for example, VDIV) with voltage 562 (for example, VHV) proportional (for example, It is directly proportional), and voltage 898 is (for example, VDIV) change over time, as shown in waveform 840, and voltage 765 is (for example, VREF2) Less than voltage 764 (for example, VREF1).In some instances, voltage 562 is (for example, VHV) with voltage 762 (for example, VHV) identical.
Fig. 9 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 900 includes: diode 502,504,506,508 and 534；Capacitor 510,532 and 536；Resistor 514； Controller 520；Inductor 538；With switch 560.Controller 520 (for example, chip) includes 522,524,526,528 and of terminal 530 (for example, pins).In addition, controller 520 (for example, chip) includes voltage control module 540 (for example, VDD controls mould Block), under-voltage locking module 542 (for example, UVLO module), demagnetization detection module 544, constant current and/or constant voltage adjust Module 546 (for example, CC/CV adjustment module), current sensing module 548, protective module 550, modulation control module 552 and driving Device 554.In addition, capacitor 536 includes terminal 516 and 518.In some examples, supply convertor 900 and supply convertor 500 is identical, and supply convertor 500 is identical as supply convertor 700.In some instances, voltage control module 540 and electricity Press control module 740 identical.As shown in Figure 9 A, resistor 514 be used as current-sense resistor, generate voltage 910 (for example, VCS).For example, voltage 910 is (for example, V according to some embodimentsCS) received by controller 520 in terminal 524, and by controlling Device 520 processed is for generating signal 798 (for example, VREP).As an example, supply convertor 900 is AC-DC buck converter.
Fig. 9 B is the simplified timing diagram of supply convertor 900 as shown in Figure 9 A according to some embodiments of the present invention. The figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many changes Change, substitutions and modifications.Waveform 940 indicates the voltage 562 changed over time (for example, VHV), the expression of waveform 950 changes over time Voltage 910 is (for example, VCS), and waveform 960 indicates the voltage 798 changed over time (for example, VREP).For example, supply convertor 900 be AC-DC buck converter, is worked using constant on-time with quasi-resonance (QR) mode.
In certain embodiments, voltage 562 is (for example, VHV) it is equal to voltage 512 (for example, VIN), and change over time, As shown in waveform 940.In some embodiments, voltage 910 is (for example, VCS) respectively reach multiple crest voltages, and multiple peaks Threshold voltage changes over time, as shown in waveform 950.For example, voltage 910 is (for example, VCS) multiple crest voltages and voltage 562 (for example, VHV) proportional (for example, directly proportional), and voltage 765 is (for example, VREF2) it is less than voltage 764 (for example, VREF1).In In some embodiments, voltage 798 is (for example, VREP) change over time, as shown in waveform 960.For example, waveform 960 is voltage 910 (for example, VCS) multiple peak values envelope.As an example, voltage 798 is (for example, VREP) with voltage 562 (for example, VHV) proportional (for example, directly proportional), and voltage 765 is (for example, VREF2) it is less than voltage 764 (for example, VREF1).For example, voltage 562 (for example, VHV) with voltage 762 (for example, VHV) identical.
Figure 10 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 1000 includes: diode 502,504,506,508 and 534；Capacitor 510,532 and 536；Resistor 514；Controller 520；Inductor 538；With switch 560.Controller 520 (for example, chip) includes terminal 522,524,526,528 With 530 (for example, pins).In addition, controller 520 (for example, chip) includes voltage control module 540 (for example, VDDControl mould Block), under-voltage locking module 542 (for example, UVLO module), demagnetization detection module 544, constant current and/or constant voltage adjust Module 546 (for example, CC/CV adjustment module), current sensing module 548, protective module 550, modulation control module 552 and driving Device 554.In addition, capacitor 536 includes terminal 516 and 518.In some examples, supply convertor 1000 and supply convertor 500 is identical, and supply convertor 500 is identical as supply convertor 700.In some instances, voltage control module 540 and electricity Press control module 740 identical.For example, supply convertor 1000 is AC-DC buck converter.
As shown in Figure 10 A, according to some embodiments, supply convertor 1000 further includes inductor 1010 and resistor 1020 and 1026, and controller 520 (for example, chip) further includes terminal 1030 (for example, pin).In some examples, electric Sensor 1010 is used as the auxiliary winding for being coupled to inductor 538.For example, auxiliary winding (for example, inductor 1010) generates voltage 1012.In some instances, resistor 1020 and 1026 is the part of divider, is connected to inductor 1010.For example, partial pressure Device includes resistor 1020 and 1026, and divider generates voltage 1098 (for example, VFB) proportional to voltage 1012 (for example, It is directly proportional).In some examples, voltage 1098 is (for example, VFB) received by controller 520 in terminal 1030, and by controlling Device 520 is for generating signal 798 (for example, VREP)。
Figure 10 B is the simplification timing of supply convertor 1000 as shown in Figure 10 according to some embodiments of the present invention Figure.The figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many Variation, substitutions and modifications.Waveform 1040 indicates the voltage 562 changed over time (for example, VHV), the expression of waveform 1050 becomes at any time The voltage 1098 of change is (for example, VFB), and waveform 1060 indicates the voltage 798 changed over time (for example, VREP)。
In certain embodiments, voltage 562 is (for example, VHV) it is equal to voltage 512 (for example, VIN), and change over time, As shown in waveform 1040.In some embodiments, voltage 1098 is (for example, VFB) multiple valley point voltages are arrived separately at, and it is multiple Valley point voltage changes over time, as shown in waveform 1050.For example, voltage 1098 is (for example, VFB) multiple valley point voltages amplitude With voltage 562 (for example, VHV) proportional (for example, directly proportional), and voltage 765 is (for example, VREF2) be less than voltage 764 (for example, VREF1).In certain embodiments, voltage 798 is (for example, VREP) change over time, as shown in waveform 1060.For example, waveform 1060 It is voltage 1098 (for example, VFB) multiple valleies envelope.As an example, voltage 798 is (for example, VREP) in amplitude with voltage 562 (for example, VHV) proportional (for example, directly proportional), and voltage 765 is (for example, VREF2) it is less than voltage 764 (for example, VREF1)。 For example, voltage 562 is (for example, VHV) with voltage 762 (for example, VHV) identical.
Figure 11 A is the simplification figure for showing AC-DC supply convertor according to certain embodiments of the present invention.The figure only shows Example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many change, replace and repair Change.Supply convertor 1100 includes: diode 502,504,506,508 and 534；Capacitor 510,532 and 536；Resistor 514；Controller 520；Inductor 538；With switch 560.Controller 520 (for example, chip) includes terminal 522,524,526,528 With 530 (for example, pins).In addition, controller 520 (for example, chip) includes voltage control module 540 (for example, VDD controls mould Block), under-voltage locking module 542 (for example, UVLO module), demagnetization detection module 544, constant current and/or constant voltage adjust Module 546 (for example, CC/CV adjustment module), current sensing module 548, protective module 550, modulation control module 552 and driving Device 554.In addition, capacitor 536 includes terminal 516 and 518.In some examples, supply convertor 1100 and supply convertor 500 is identical, and supply convertor 500 is identical as supply convertor 700.In some instances, voltage control module 540 and electricity Press control module 740 identical.As shown in Figure 11 A, according to some embodiments, driver 554 generate driving signal 1120 (for example, VGATE).In some instances, driving signal 1120 is (for example, VGATE) switch 560 is sent to by terminal 522.Show certain In example, controller 520 is using driving signal 1120 (for example, VGATE) Lai Shengcheng signal 798 is (for example, VREP).For example, power supply becomes Parallel operation 1100 is AC-DC buck converter.
Figure 11 B is the simplification timing of supply convertor 1100 as shown in Figure 11 A according to some embodiments of the present invention Figure.The figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many Variation, substitutions and modifications.Waveform 1140 indicates the voltage 562 changed over time (for example, VHV), the expression of waveform 1150 becomes at any time The voltage 1120 of change is (for example, VGATE), and waveform 1160 indicates the voltage 798 changed over time (for example, VREP).For example, electric Source converter 1100 is AC-DC buck converter, is worked with quasi-resonance (QR) mode.
In certain embodiments, voltage 562 is (for example, VHV) it is equal to voltage 512 (for example, VIN), and change over time, As shown in waveform 1140.In some embodiments, voltage 1120 is (for example, VGATE) in logic high and in logic low Change between level, and voltage 1120 is (for example, VGATE) duty ratio change over time, as shown in waveform 1150.Certain In embodiment, voltage 798 is (for example, VREP) change over time, as shown in waveform 1160.In some instances, while voltage 798 (for example, VREP) with voltage 1120 (for example, VGATE) duty ratio it is proportional (for example, directly proportional).In some examples, voltage 798 (for example, VREP) with voltage 562 (for example, VHV) be inversely proportional, and voltage 765 is (for example, VREF2) be greater than voltage 764 (for example, VREF1).In some instances, voltage 562 is (for example, VHV) with voltage 762 (for example, VHV) identical.
Figure 12 is the simplified timing diagram of supply convertor 700 as shown in Figure 7 according to some embodiments of the present invention.It should Figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many variations, Substitutions and modifications.Waveform 1210 indicates the voltage 766 changed over time (for example, VDD), the expression of waveform 1220 changes over time Signal 798 is (for example, VREP), and waveform 1230 indicates the electric current 796 changed over time (for example, IJFET).For example, power supply becomes Parallel operation 700 is AC-DC buck converter, is worked using constant on-time with quasi-resonance (QR) mode, and signal 798 (for example, VREP) with voltage 762 (for example, VHV) proportional (for example, directly proportional).
According to some embodiments, in time t1Place, signal 798 is (for example, VREP) signal 797 is become larger than (for example, VTH), As shown in waveform 1220.In some instances, in time t1Place, by comparator 784 in the received voltage of terminal 770 from voltage 764 (for example, VREF1) become voltage 765 (for example, VREF2).In some examples, in time t1Place, voltage 766 is (for example, VDD) It becomes larger than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 becomes patrolling from logic high Volume low level, and JFET 780 is in the signal 768 of logic low and goes off.In some instances, in time t1 Place, as shown in waveform 1230, electric current 796 is (for example, IJFET) can be provided from junction gate field effect transistor (JFET) 780 Maximum current is (for example, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
According to some embodiments, from time t1To time t2, signal 798 is (for example, VREP) be remained above signal 797 (for example, VTH), as shown in waveform 1220.In some instances, from time t1To time t2, received in terminal 770 by comparator 784 Voltage remains voltage 765 (for example, VREF2).In some examples, from time t1To time t2, voltage 766 is (for example, VDD) protect It holds and is greater than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 is maintained at logic low, and And JFET 780 is remained open.In some instances, from time t1To time t2, electric current 796 is (for example, IJFET) zero is kept equal to, As shown in waveform 1230, and electric current 796 does not charge to capacitor 732.In some instances, from time t1To time t2, Voltage 766 is (for example, VDD) be remained above by comparator 784 in the received voltage of terminal 770 (for example, VREF2), voltage 766 (for example, VDD) reduce at any time, as shown in waveform 1210.In some examples, from time t1To time t2, 796 (example of electric current Such as, IJFET) zero is kept equal to, and since the operating current of controller 720 (for example, chip) is (for example, IIC), so voltage 766 (for example, VDD) reduce at any time.
According to some embodiments, in time t2Place, signal 798 is (for example, VREP) signal 797 is remained above (for example, VTH), As shown in waveform 1220.In some instances, in time t2Place, is remained by comparator 784 in the received voltage of terminal 770 Voltage 765 is (for example, VREF2).In some examples, in time t2Place, voltage 766 is (for example, VDD) become smaller than by comparator 784 at terminal 770 received voltage (for example, VREF2), signal 768 becomes logic high from logic low, and The signal 768 that JFET 780 is in logic high becomes being connected.In some instances, in time t2Place, such as waveform 1230 Shown, electric current 796 is (for example, IJFET) from zero become the maximum electricity that junction gate field effect transistor (JFET) 780 can provide Stream is (for example, IJFET_MAX), and electric current 796 charges to capacitor 732.
According to some embodiments, from time t2To time t3, signal 798 is (for example, VREP) be remained above signal 797 (for example, VTH), as shown in waveform 1220.In some instances, from time t2To time t3, received in terminal 770 by comparator 784 Voltage remains voltage 765 (for example, VREF2).In some examples, from time t2To time t3, voltage 766 is (for example, VDD) quilt It adjusts in voltage 765 (for example, VREF2) near, as shown in waveform 1210, signal 768 is in logic high and in logic Change between low level, and JFET 780 changes between conducting and disconnection.In some instances, from time t2To time t3, Electric current 796 is (for example, IJFET) be equal to junction gate field effect transistor (JFET) 780 can provide maximum current (for example, IJFET_MAX) between and equal to zero between change, as shown in waveform 1230.In some examples, from time t2To time t3, electric current 796 are carrying out capacitor 732 to charge and change between not charging to capacitor 732.
According to some embodiments, in time t3Place, signal 798 is (for example, VREP) signal 797 is become smaller than (for example, VTH), As shown in waveform 1220.In some instances, in time t3Place, by comparator 784 in the received voltage of terminal 770 from voltage 765 (for example, VREF2) become voltage 764 (for example, VREF1).In some examples, in time t3Place, voltage 766 is (for example, VDD) It becomes smaller than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), signal 768 is in logic high, and And JFET 780 is in the conducting of signal 768 of logic high.In some instances, in time t3Place, such as 1230 institute of waveform Show, electric current 796 is (for example, IJFET) it is equal to the maximum current (example that junction gate field effect transistor (JFET) 780 can be provided Such as, IJFET_MAX), and electric current 796 charges to capacitor 732.
According to some embodiments, from time t3To time t4, signal 798 is (for example, VREP) remain less than signal 797 (for example, VTH), as shown in waveform 1220.In some instances, from time t3To time t4, received in terminal 770 by comparator 784 Voltage remains voltage 764 (for example, VREF1).In some examples, from time t3To time t4, voltage 766 is (for example, VDD) protect It holds and is less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), signal 768 is maintained at logic high, and And JFET 780 is held on.In some instances, from time t3To time t4, electric current 796 is (for example, IJFET) keep equal to knot The maximum current that type gate field effect transistor (JFET) 780 can provide is (for example, IJFET_MAX), as shown in waveform 1230, and And electric current 796 charges to capacitor 732.In some instances, from time t3To time t4, voltage 766 is (for example, VDD) protect It holds and is less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), voltage 766 is (for example, VDD) increase with time, As shown in waveform 1210.
According to some embodiments, in time t4Place, signal 798 is (for example, VREP) signal 797 is remained less than (for example, VTH), As shown in waveform 1220.In some instances, in time t4Place, is remained by comparator 784 in the received voltage of terminal 770 Voltage 764 is (for example, VREF1).In some examples, in time t4Place, voltage 766 is (for example, VDD) become larger than by comparator 784 at terminal 770 received voltage 764 (for example, VREF1), signal 768 becomes logic low from logic high, and The signal 768 that JFET 780 is in logic low is gone off.In some instances, in time t4Place, such as waveform 1230 Shown, electric current 796 is (for example, IJFET) maximum current (example that can be provided from junction gate field effect transistor (JFET) 780 Such as, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
According to some embodiments, from time t4To time t5, signal 798 is (for example, VREP) remain less than signal 797 (for example, VTH), as shown in waveform 1220.In some instances, from time t4To time t5, received in terminal 770 by comparator 784 Voltage remains voltage 764 (for example, VREF1).In some examples, from time t4To time t5, voltage 766 is (for example, VDD) quilt It adjusts in voltage 764 (for example, VREF1) near, as shown in waveform 1210, signal 768 is in logic low and in logic Change between high level, and JFET 780 changes between disconnection and conducting.In some instances, from time t4To time t5, Electric current 796 is (for example, IJFET) in the maximum electricity that is equal to zero and can be provided equal to junction gate field effect transistor (JFET) 780 Stream is (for example, IJFET_MAX) between change, as shown in waveform 1230.In some examples, from time t4To time t5, electric current 796 Capacitor 732 is not being carried out charging and changed between charging to capacitor 732.
According to some embodiments, in time t5Place, signal 798 is (for example, VREP) signal 797 is become larger than (for example, VTH), As shown in waveform 1220.In some instances, in time t5Place, by comparator 784 in the received voltage of terminal 770 from voltage 764 (for example, VREF1) become voltage 765 (for example, VREF2).In some examples, in time t5Place, voltage 766 is (for example, VDD) It becomes larger than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 becomes patrolling from logic high Volume low level, and JFET 780 is in the signal 768 of logic low and goes off.In some instances, in time t5 Place, as shown in waveform 1230, electric current 796 is (for example, IJFET) can be provided from junction gate field effect transistor (JFET) 780 Maximum current is (for example, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
As shown in figure 12, according to some embodiments, electric current 796 is (for example, IJFET) average value be equal to controller 720 work Make electric current (for example, IIC), as shown in waveform 1230.
It emphasizes as described above and further herein, Figure 12 is only example, should not improperly restrict the scope of the claims. It will be appreciated by those of ordinary skill in the art that many variations, substitutions and modifications.For example, can waveform be changed in the following manner 1210,1220 and 1230: changing signal 797 (for example, VTH), voltage 764 is (for example, VREF1), voltage 765 is (for example, VREF2), knot The maximum current that type gate field effect transistor (JFET) 780 can provide is (for example, IJFET_MAX), and/or capacitor 732 electricity Capacitance.
In some embodiments, voltage 766 is (for example, VDD) voltage 765 will not be reduced to (for example, VREF2) under, and Voltage 766 is (for example, VDD) voltage 765 is kept above (for example, VREF2), for example, as shown in figure 13.In certain embodiments, electric Pressure 766 is (for example, VDD) voltage 764 is not risen to (for example, VREF1) on, and voltage 766 is (for example, VDD) keep below electricity Pressure 764 is (for example, VREF1), for example, as shown in figure 14.
Figure 13 is the simplified timing diagram of supply convertor 700 as shown in Figure 7 according to some embodiments of the present invention.It should Figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many variations, Substitutions and modifications.Waveform 1310 indicates the voltage 766 changed over time (for example, VDD), the expression of waveform 1320 changes over time Signal 798 is (for example, VREP), and waveform 1330 indicates the electric current 796 changed over time (for example, IJFET).For example, power supply becomes Parallel operation 700 is AC-DC buck converter, is worked using constant on-time with quasi-resonance (QR) mode, and signal 798 (for example, VREP) with voltage 762 (for example, VHV) proportional (for example, directly proportional).
According to some embodiments, in time t11Place, signal 798 is (for example, VREP) signal 797 is become larger than (for example, VTH), As shown in waveform 1320.In some instances, in time t11Place, by comparator 784 in the received voltage of terminal 770 from voltage 764 (for example, VREF1) become voltage 765 (for example, VREF2).In some examples, in time t11Place, voltage 766 is (for example, VDD) It becomes larger than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 becomes patrolling from logic high Volume low level, and JFET 780 is in the signal 768 of logic low and goes off.In some instances, in time t11 Place, as shown in waveform 1330, electric current 796 is (for example, IJFET) can be provided from junction gate field effect transistor (JFET) 780 Maximum current is (for example, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
According to some embodiments, from time t11To time t12, signal 798 is (for example, VREP) it is remained above 797 (example of signal Such as, VTH), as shown in waveform 1320.In some instances, from time t11To time t12, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 765 (for example, VREF2).In some examples, from time t11To time t12, voltage 766 (for example, VDD) be remained above by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 keeps being in logic low Level, and JFET 780 is remained open.In some instances, from time t11To time t12, electric current 796 is (for example, IJFET) protect It holds and is equal to zero, as shown in waveform 1330, and electric current 796 does not charge to capacitor 732.In some instances, from the time t11To time t12, voltage 766 is (for example, VDD) be remained above by comparator 784 the received voltage of terminal 770 (for example, VREF2), voltage 766 is (for example, VDD) reduce at any time, as shown in waveform 1310.In some examples, from time t11To the time t12, electric current 796 is (for example, IJFET) keep equal to zero, and due to the operating current of controller 720 (for example, chip) (for example, IIC), voltage 766 is (for example, VDD) reduce at any time.
According to some embodiments, in time t12Place, signal 798 is (for example, VREP) signal 797 is become smaller than (for example, VTH), As shown in waveform 1320.In some instances, in time t12Place, by comparator 784 in the received voltage of terminal 770 from voltage 765 (for example, VREF2) become voltage 764 (for example, VREF1).In some examples, in time t12Place, voltage 766 is (for example, VDD) It becoming smaller than by comparator 784 in the received voltage of terminal 770, signal 768 becomes logic high from logic low, and And JFET 780 is in the signal 768 of logic high and becomes being connected.In some instances, in time t12Place, such as waveform Shown in 1330, electric current 796 is (for example, IJFET) become junction gate field effect transistor (JFET) 780 from zero and can provide most High current is (for example, IJFET_MAX), and electric current 796 charges to capacitor 732.
According to some embodiments, from time t12To time t13, signal 798 is (for example, VREP) remain less than 797 (example of signal Such as, VTH), as shown in waveform 1320.In some instances, from time t12To time t13, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 764 (for example, VREF1).In some examples, from time t12To time t13, voltage 766 (for example, VDD) remain less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), signal 768 is kept in logically high Level, and JFET 780 is held on.In some instances, from time t12To time t13, electric current 796 is (for example, IJFET) protect It holds and is equal to the maximum current that can provide of junction gate field effect transistor (JFET) 780 (for example, IJFET_MAX), such as waveform 1330 It is shown, and electric current 796 charges to capacitor 732.In some instances, from time t12To time t13, 766 (example of voltage Such as, VDD) remain less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), voltage 766 is (for example, VDD) with Time increases, as shown in waveform 1310.
According to some embodiments, in time t13Place, signal 798 is (for example, VREP) signal 797 is remained less than (for example, VTH), As shown in waveform 1320.In some instances, in time t13Place, is remained by comparator 784 in the received voltage of terminal 770 Voltage 764 is (for example, VREF1).In some examples, in time t13Place, voltage 766 is (for example, VDD) become larger than by comparator 784 at terminal 770 received voltage 764 (for example, VREF1), signal 768 becomes logic low from logic high, and The signal 768 that JFET 780 is in logic low is gone off.In some instances, in time t13Place, such as waveform 1330 Shown, electric current 796 is (for example, IJFET) maximum current (example that can be provided from junction gate field effect transistor (JFET) 780 Such as, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
According to some embodiments, from time t13To time t14, signal 798 is (for example, VREP) remain less than 797 (example of signal Such as, VTH), as shown in waveform 1320.In some instances, from time t13To time t14, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 764 (for example, VREF1).In some examples, from time t13To time t14, voltage 766 (for example, VDD) voltage 764 is adjusted in (for example, VREF1) near, as shown in waveform 1310, signal 768 is being in logic low and place Change between logic high, and JFET 780 changes between disconnection and conducting.In some instances, from time t13It arrives Time t14, electric current 796 is (for example, IJFET) be equal to zero and be equal to junction gate field effect transistor (JFET) 780 and can provide Maximum current (for example, IJFET_MAX) between change, as shown in waveform 1330.In some examples, from time t13To the time t14, electric current 796 do not carrying out capacitor 732 charging and change between charging to capacitor 732.
As shown in figure 13, according to some embodiments, electric current 796 is (for example, IJFET) average value be equal to controller 720 work Make electric current (for example, IIC), as shown in waveform 1330.
Figure 14 is the simplified timing diagram of supply convertor 700 as shown in Figure 7 according to certain embodiments of the present invention.It should Figure is only example, should not improperly restrict the scope of the claims.It will be appreciated by those of ordinary skill in the art that many variations, Substitutions and modifications.Waveform 1410 indicates the voltage 766 changed over time (for example, VDD), the expression of waveform 1420 changes over time Signal 798 is (for example, VREP), and waveform 1430 indicates the electric current 796 changed over time (for example, IJFET).For example, power supply becomes Parallel operation 700 is AC-DC buck converter, is worked using constant on-time with quasi-resonance (QR) mode, and signal 798 (for example, VREP) with voltage 762 (for example, VHV) proportional (for example, directly proportional).
According to some embodiments, in time t21Place, signal 798 is (for example, VREP) signal 797 is become larger than (for example, VTH), As shown in waveform 1420.In some instances, in time t21Place, by comparator 784 in the received voltage of terminal 770 from voltage 764 (for example, VREF1) become voltage 765 (for example, VREF2).In some examples, in time t21Place, voltage 766 is (for example, VDD) It becomes larger than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 becomes patrolling from logic high Volume low level, and JFET 780 is in the signal 768 of logic low and goes off.In some instances, in time t21 Place, as shown in waveform 1430, electric current 796 is (for example, IJFET) can be provided from junction gate field effect transistor (JFET) 780 Maximum current is (for example, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
According to some embodiments, from time t21To time t22, signal 798 is (for example, VREP) it is remained above 797 (example of signal Such as, VTH), as shown in waveform 1420.In some instances, from time t21To time t22, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 765 (for example, VREF2).In some examples, from time t21To time t22, voltage 766 (for example, VDD) be remained above by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 keeps being in logic low Level, and JFET 780 is remained open.In some instances, from time t21To time t22, electric current 796 is (for example, IJFET) protect It holds and is equal to zero, as shown in waveform 1430, and electric current 796 does not charge to capacitor 732.In some instances, from the time t21To time t22, voltage 766 is (for example, VDD) be remained above by comparator 784 the received voltage of terminal 770 (for example, VREF2), voltage 766 is (for example, VDD) reduce at any time, as shown in waveform 1410.In some examples, from time t21To the time t22, electric current 796 is (for example, IJFET) keep equal to zero, and due to the operating current of controller 720 (for example, chip) (for example, IIC), so voltage 766 is (for example, VDD) reduce at any time.
According to some embodiments, in time t22Place, signal 798 is (for example, VREP) signal 797 is remained above (for example, VTH), As shown in waveform 1420.In some instances, in time t22Place, is remained by comparator 784 in the received voltage of terminal 770 Voltage 765 is (for example, VREF2).In some examples, in time t22Place, voltage 766 is (for example, VDD) become smaller than by comparator 784 at terminal 770 received voltage (for example, VREF2), signal 768 becomes logic high from logic low, and The signal 768 that JFET 780 is in logic high becomes being connected.In some instances, in time t22Place, such as waveform 1430 Shown, electric current 796 is (for example, IJFET) from zero become the maximum electricity that junction gate field effect transistor (JFET) 780 can provide Stream is (for example, IJFET_MAX), and electric current 796 charges to capacitor 732.
According to some embodiments, from time t22To time t23, signal 798 is (for example, VREP) it is remained above 797 (example of signal Such as, VTH), as shown in waveform 1420.In some instances, from time t22To time t23, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 765 (for example, VREF2).In some examples, from time t22To time t23, voltage 766 (for example, VDD) voltage 765 is adjusted in (for example, VREF2) near, as shown in waveform 1410, signal 768 is being in logic high and place Change between logic low, and JFET 780 changes between conducting and disconnection.In some instances, from time t22It arrives Time t23, electric current 796 is (for example, IJFET) being equal to, the maximum that junction gate field effect transistor (JFET) 780 can be provided is electric Stream is (for example, IJFET_MAX) and equal to zero between change, as shown in waveform 1430.In some examples, from time t22To the time t23, electric current 796 carrying out capacitor 732 to charge and change between not charging to capacitor 732.
According to some embodiments, in time t23Place, signal 798 is (for example, VREP) signal 797 is become smaller than (for example, VTH), As shown in waveform 1420.In some instances, in time t23Place, by comparator 784 in the received voltage of terminal 770 from voltage 765 (for example, VREF2) become voltage 764 (for example, VREF1).In some examples, in time t23Place, voltage 766 is (for example, VDD) It becomes smaller than by comparator 784 in the received voltage of terminal 770, signal 768 is in logic high, and 780 quilt of JFET Signal 768 in logic high is connected.In some instances, in time t23Place, as shown in waveform 1430,796 (example of electric current Such as, IJFET) it is equal to the maximum current that can provide of junction gate field effect transistor (JFET) 780 (for example, IJFET_MAX), and Electric current 796 charges to capacitor 732.
According to some embodiments, from time t23To time t24, signal 798 is (for example, VREP) remain less than 797 (example of signal Such as, VTH), as shown in waveform 1420.In some instances, from time t23To time t24, connect by comparator 784 in terminal 770 The voltage of receipts remains voltage 764 (for example, VREF1).In some examples, from time t23To time t24, voltage 766 (for example, VDD) remain less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), signal 768 is kept in logically high Level, and JFET 780 is held on.In some instances, from time t23To time t24, electric current 796 is (for example, IJFET) protect It holds and is equal to the maximum current that can provide of junction gate field effect transistor (JFET) 780 (for example, IJFET_MAX), such as waveform 1430 It is shown, and electric current 796 charges to capacitor 732.In some instances, from time t23To time t24, 766 (example of voltage Such as, VDD) remain less than by comparator 784 in the received voltage of terminal 770 (for example, VREF1), voltage 766 is (for example, VDD) with Time increases, as shown in waveform 1410.
According to some embodiments, in time t24Place, signal 798 is (for example, VREP) signal 797 is become larger than (for example, VTH), As shown in waveform 1420.In some instances, in time t24Place, by comparator 784 in the received voltage of terminal 770 from voltage 764 (for example, VREF1) become voltage 765 (for example, VREF2).In some examples, in time t24Place, voltage 766 is (for example, VDD) It becomes larger than by comparator 784 in the received voltage of terminal 770 (for example, VREF2), signal 768 becomes patrolling from logic high Volume low level, and JFET 780 is in the signal 768 of logic low and goes off.In some instances, in time t24 Place, as shown in waveform 1430, electric current 796 is (for example, IJFET) can be provided from junction gate field effect transistor (JFET) 780 Maximum current is (for example, IJFET_MAX) become zero, and electric current 796 does not charge to capacitor 732.
As shown in figure 14, according to some embodiments, electric current 796 is (for example, IJFET) average value be equal to controller 720 work Make electric current (for example, IIC), as shown in waveform 1430.
Certain embodiments of the present invention provides a kind of controller using high voltage supply, and additionally provides one kind and be used for The correlation technique of controller.In some instances, identical high voltage supply voltage, the controller and method can significantly be dropped Down to the partially loss of power as caused by high voltage supply.In some examples, for identical high voltage supply voltage, the control Device processed and method can be significantly reduced the temperature of controller and significantly improve system effectiveness.
Some embodiments of the present invention provide a kind of controller using high voltage supply, and additionally provide one kind and be used for The correlation technique of controller.In some examples, when high voltage supply voltage becomes to be above threshold value (for example, VTH) when, the controller Switch (for example, junction gate field effect transistor) can be disconnected with method to stop the charging to capacitor.In some examples In, when high voltage supply voltage gets lower than threshold value (for example, VTH) when, switch can be connected (for example, junction type in the controller and method Gate field effect transistor) to allow the charging to capacitor.
According to some embodiments, a kind of controller for supply convertor includes: first terminal, is configured as reception One terminal voltage；Second terminal is configured as receiving Second terminal voltage；Comparator is configured as receiving first threshold voltage With Second terminal voltage, and first threshold voltage and Second terminal voltage are based at least partially on to generate comparison signal；With And switch, it is configured as receiving first terminal voltage and comparison signal, which is additionally configured to be in first in comparison signal (for example, conducting) is closed when logic level to allow electric current to pass through switch outflow Second terminal；Wherein, comparator is also configured Are as follows: when first terminal voltage is less than second threshold voltage, the first reference voltage is received as first threshold voltage；And When one terminal voltage is greater than second threshold voltage, the second reference voltage is received as first threshold voltage；Wherein, first with reference to electricity Pressure is greater than the second reference voltage；Wherein, comparator is also configured to when first threshold voltage is greater than Second terminal voltage, raw At the comparison signal for being in the first logic level；And it when first threshold voltage is less than Second terminal voltage, generates in the The comparison signal of two logic levels；Wherein, the second logic level is different from the first logic level.For example, controller according at least to Fig. 7 is realized.
In some instances, the first logic level is logic high；And the second logic level is logic low.In In certain examples, switch is additionally configured to be opened (for example, disconnection) when comparison signal is in the second logic level not permit Perhaps electric current passes through switch outflow Second terminal.In some instances, switch includes transistor, which is configured as comparing Signal is switched on when being in the first logic level to allow electric current to flow out Second terminal by transistor.In some examples, brilliant Body pipe is additionally configured to be disconnected when comparison signal is in the second logic level to be not allow current through transistor outflow the Two-terminal.In some instances, transistor is junction gate field effect transistor.In some examples, Second terminal is coupled To capacitor, which is configured as receiving electric current from Second terminal and provides Second terminal voltage to Second terminal.
According to some embodiments, a kind of controller for supply convertor includes: first terminal, is configured as reception One terminal voltage；Second terminal is configured as receiving Second terminal voltage；First comparator is configured as receiving first threshold Voltage and comparator input voltage, and first threshold voltage and comparator input voltage are based at least partially on to generate first Comparison signal, first comparator are additionally configured to generate when first threshold voltage is greater than comparator input voltage and patrol in first The first comparison signal of level is collected, and is generated when first threshold voltage is less than comparator input voltage in the second logic electricity The first flat comparison signal, the second logic level are different from the first logic level；First switch is configured as reception first and compares Signal and second threshold voltage is exported, which is additionally configured to the output when the first comparison signal is in the first logic level First reference voltage is as second threshold voltage, and the second reference of output when the first comparison signal is in the second logic level Voltage is different from the first reference voltage as second threshold voltage, the second reference voltage；Second comparator is configured as reception Two threshold voltages and Second terminal voltage and second threshold voltage and Second terminal voltage are based at least partially on to generate Two comparison signals, the second comparator are additionally configured to generate when second threshold voltage is greater than Second terminal voltage and patrol in third The second comparison signal of level is collected, and is generated when second threshold voltage is less than Second terminal voltage and is in the 4th logic level The second comparison signal, the 4th logic level be different from third logic level；And second switch, it is configured as receiving first end Sub- voltage and the second comparison signal, second switch are additionally configured to be closed when the second comparison signal is in third logic level (for example, conducting) is to allow electric current to flow out Second terminal by second switch；Wherein, comparator input voltage and first terminal electricity Pressure is associated.For example, controller is realized according at least to Fig. 7.
In some instances, increase with the increase of first terminal voltage in comparator input voltage and with first The reduction of terminal voltage and when reducing, the first reference voltage is greater than the second reference voltage.In some examples, it is inputted in comparator When voltage reduces with the increase of first terminal voltage and increases with the reduction of first terminal voltage, first with reference to electricity Pressure is less than the second reference voltage.In some instances, the first logic level is identical with third logic level；And the second logic electricity Gentle 4th logic level is identical.In some examples, the first logic level is logic high；Second logic level is logic Low level；Third logic level is logic high；And the 4th logic level is in logic low.
In some instances, second switch is additionally configured to be opened when the second comparison signal is in four logic levels (for example, disconnection) is to be not allow current through second switch outflow Second terminal.In some examples, second switch includes crystal Pipe, the transistor are configured as being switched on when the second comparison signal is in third logic level to allow electric current to pass through transistor Flow out Second terminal.In some instances, transistor is additionally configured to the quilt when the second comparison signal is in four logic levels It disconnects to be not allow current through transistor outflow Second terminal.In some examples, transistor is that junction gate field-effect is brilliant Body pipe.In some instances, Second terminal is coupled to capacitor, which is configured as receiving electric current simultaneously from Second terminal Second terminal voltage is provided to Second terminal.
According to some embodiments, a kind of method for supply convertor includes: to receive first terminal voltage；Receive second Terminal voltage；Receive Second terminal voltage and first threshold voltage；It is based at least partially on Second terminal voltage and first threshold Voltage generates comparison signal；Receive first terminal voltage and comparison signal；And the first logic level is in comparison signal When, closure (for example, conducting) switch is to allow electric current to flow through switch；Wherein, Second terminal voltage and first threshold voltage are received It include: to receive the first reference voltage as first threshold voltage when first terminal voltage is less than second threshold voltage；And When first terminal voltage is greater than second threshold voltage, the second reference voltage is received as first threshold voltage；Wherein, the first reference Voltage is greater than the second reference voltage；Wherein, it is based at least partially on Second terminal voltage and first threshold voltage compares to generate Signal includes: to generate the comparison signal for being in the first logic level when first threshold voltage is greater than Second terminal voltage；And When first threshold voltage is less than Second terminal voltage, the comparison signal for being in the second logic level is generated；Wherein, the second logic Level is different from the first logic level.For example, this method is realized according at least to Fig. 7.
In some instances, the first logic level is logic high；And the second logic level is logic low.In In certain examples, this method further include: when comparison signal is in the second logic level, open (for example, disconnection) switch with not Electric current is allowed to flow through switch.In some instances, this method further include: electric current is received by capacitor；And pass through capacitor Second terminal voltage is provided.
According to some embodiments, a kind of method for supply convertor includes: to receive first terminal voltage；Receive second Terminal voltage；Receive first threshold voltage and comparator input voltage；And it is based at least partially on first threshold voltage and ratio The first comparison signal is generated compared with device input voltage.For example, being based at least partially on first threshold voltage and comparator input electricity Pressure come generate the first comparison signal include: first threshold voltage be greater than comparator input voltage when, generate be in the first logic First comparison signal of level；And when first threshold voltage is less than comparator input voltage, generate in the second logic electricity The first flat comparison signal, the second logic level are different from the first logic level.In some instances, this method further include: connect Receive the first comparison signal；And the first comparison signal is based at least partially on to export second threshold voltage.For example, at least partly Ground exported based on the first comparison signal second threshold voltage include: when the first comparison signal is in the first logic level, it is defeated The first reference voltage is as second threshold voltage out；And when the first comparison signal is in the second logic level, output second Reference voltage is different from the first reference voltage as second threshold voltage, the second reference voltage.In some examples, this method is also It include: to receive second threshold voltage and Second terminal voltage；And it is based at least partially on second threshold voltage and Second terminal Voltage generates the second comparison signal.For example, being based at least partially on second threshold voltage and Second terminal voltage to generate Two comparison signals include: to generate the second ratio in third logic level when second threshold voltage is greater than Second terminal voltage Compared with signal；And when second threshold voltage is less than Second terminal voltage, generates second in the 4th logic level and compare letter Number, the 4th logic level is different from third logic level.In some instances, this method further include: receive first terminal voltage With the second comparison signal；And when the second comparison signal is in third logic level, closure (for example, conducting) switch is to allow Electric current flows through switch.For example, comparator input voltage is associated with first terminal voltage.As an example, this method according at least to Fig. 7 is realized.
In some instances, increase with the increase of first terminal voltage in comparator input voltage and with first The reduction of terminal voltage and when reducing, the first reference voltage is greater than the second reference voltage.In some examples, it is inputted in comparator When voltage reduces with the increase of first terminal voltage and increases with the reduction of first terminal voltage, first with reference to electricity Pressure is less than the second reference voltage.In some instances, the first logic level is identical with third logic level；And the second logic electricity Gentle 4th logic level is identical.In some examples, the first logic level is logic high；Second logic level is logic Low level；Third logic level is logic high；And the 4th logic level is in logic low.In some instances, This method further include: when the second comparison signal is in four logic levels, open (for example, disconnection) switch not allow electric current Flow through switch.In some examples, this method further include: electric current is received by capacitor；And second end is provided by capacitor Sub- voltage.
For example, each of some or all of modules of various embodiments of the present invention be individually and/or at least Another block combiner uses one or more software modules, one or more hardware modules and/or software and hardware module One or more combination is to realize.In another example, each in some or all of modules of various embodiments of the present invention It is a be individually and/or at least another block combiner, in one or more circuits (for example, one or more analog circuit And/or one or more digital circuits) in realize.In yet another example, can combine various embodiments of the present invention and/or Example.
Although specific embodiments of the present invention have been described, it will be appreciated, however, by one skilled in the art that in the presence of being equal to The other embodiments of described embodiment.It should therefore be understood that the present invention is not limited by the specific embodiment shown, and It is only to be limited by scope of the appended claims.
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