阅读说明：本技术 一种基于fpga的lfm_bpsk复合调制信号实时产生方法 (A kind of real-time production method of LFM_BPSK multiplex modulated signal based on FPGA ) 是由 唐建 潘明海 胥伟 李益民 于 2019-08-08 设计创作，主要内容包括：本发明公开了一种基于FPGA的LFM_BPSK复合调制信号实时产生方法,包括如下步骤：(1)从ROM中读取线性调频信号调频率和每路输出数据数,生成LFM信号；(2)重复读取存储于ROM中的二进制数据,根据数据的相位值确定BPSK信号的符号,并形成数据序列；(3)将LFM信号和BPSK信号进行正交调制,得到LFM_BPSK复合调制信号。本发明中基带信号的频率范围、采样率可变,LFM信号的带宽、雷达发射脉冲宽度和用于相位编码的数据长度均可控,频域和时域仿真结果验证了算法的可行性。本发明的结论对射频目标模拟器设计具有重要的理论指导意义。(The invention discloses a kind of real-time production method of LFM_BPSK multiplex modulated signal based on FPGA includes the following steps: that (1) reads the road linear FM signal frequency modulation Shuai Hemei output data number from ROM, generates LFM signal；(2) binary data being stored in ROM is repeatedly read, the symbol of bpsk signal is determined according to the phase value of data, and form data sequence；(3) LFM signal and bpsk signal are subjected to orthogonal modulation, obtain LFM_BPSK multiplex modulated signal.The frequency range of baseband signal, variable sample rate in the present invention, the bandwidth of LFM signal, radar transmitted pulse width and data length for phase code are controllable, and frequency domain and time-domain simulation results demonstrate the feasibility of algorithm.Conclusion of the invention has important theory directive significance to the design of radio frequency target simulator.)

1. a kind of real-time production method of LFM_BPSK multiplex modulated signal based on FPGA, which comprises the steps of:

(1) road linear frequency-modulated parameter frequency modulation ShuaiμHe Mei output data number M is read from ROM, generates linear FM signal Trigonometric function coefficient cos [μ π (m Δ t)²)] and sin [π μ (m Δ t)²], wherein m=0,1,2 ... ... M-1, Δ t=1/f_s, f_s It is baseband signal samples rate；The trigonometric function coefficient of generation is stored in RAM respectively；

(2) it reads and is stored in binary data C to be encoded in ROM, data length L and every road output data number M, according to data Phase value determine the symbol of bpsk signal, and form data sequence cos [2 π f_IΔ t+ θ m)] and sin [2 π f_IΔ t+ θ (m)], Wherein m=0,1,2 ... ... M-1, Δ t are as previously mentioned, θ (m)=π d₂And d (m),₂(m)∈{0,1}；By the triangle letter of generation Number system number is stored in RAM respectively；

(3) LFM signal and bpsk signal are carried out positive intermodulation by the trigonometric function coefficient that LFM and bpsk signal are read from RAM System, obtains LFM_BPSK multiplex modulated signal

S (m)=exp [j (2 π f_IΔt+μπ(mΔt)²+θ(m))]。

2. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that FPGA includes sine and cosine functions table memory module, includes respectively the memory block 4096 × 16bit, for storing (2¹⁵-1)×cos The numerical value and (2 of (π/4096 n × 2)¹⁵- 1) numerical value of × sin (π/4096 n × 2), wherein n=0,1,2...4095；Step (1) (2) under the conditions of, respectively with μ π (m Δ t)²With 2 π f_IΔ t+ θ (m) searches trigono-metric system from the function table of the storage for address Number, address size 12bit.

3. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that Under the conditions of step (1) (2) (3), m keeps synchronous variation, and each clock pulses completes variation.

4. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that In step (1), the initial value of 8 tunnel real time data angle of LFM signal is

1st tunnel: Θ (0)=4 μ₀·2^-18

…

I-th tunnel: Θ (i-1)=(i+3) μ₀·2^-18

Wherein μ₀=2³³·(Δt)²μ, length 18bit are passed, i=0,1,2...7 under being calculated by host computer；Q_mA clock When the period, 8 circuit-switched data real-time angular of LFM signal is the 1st tunnel: Θ (8q_m- 8)=Θ (8q_m-16)+8μ₀(q_m-1)·2^-18

…

I-th tunnel: Θ (8q_m+ i-1)=Θ (8q_m+i-9)+8μ₀(q_m-1)·2^-18

Wherein m=8 × q_m+ i, i=0,1,2 ... 7, Θ (8q_m+ i-9) it is (q_m- 1) the i-th tunnel of LFM signal when a clock cycle The real-time angular variable quantity of real-time angular, i.e., two neighboring clock cycle each circuit-switched data differs Δ Θ (q_m)-ΔΘ(q_m- 1)=8 μ₀·2^-18。

5. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that In step (2), binary data C to be encoded can use 2bit~64bit, the corresponding desirable 1bit~6bit of data length L, and phase is compiled Code signal precision Δ jm is controllable, is 12bit, related to data length L and every road output data number M；Wherein, to greatly improve ground Location precision, if Δ jmb=Δ jm2²⁸/ 27 be 36bit, is passed under being calculated by host computer；

(21) Q component address generating method: address to 0 or 4096 need to judge that next signal periodic phase is 0 or π, if 0, then unchanged location incremental mode；If π, next signal period extra address increment since 2048 generates new address Code, address code 12bit；

(22) I component address generating method:

When the phase in current demand signal period is 0, if next signal period phase is π, address 3072 is changed to 1024, and add Address increment generates new address code；If next signal period phase is 0, then extra address increases on the basis of address 3072 Amount generates new address code, address code 12bit；

When the phase in current demand signal period is π, if next signal period phase is 0,3072 will be changed at address 1024, and attached Address increment is added to generate new address code；If next signal period phase is π, then extra address on the basis of address 1024 Increment generates new address code, address code 12bit.

6. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that In step (3), the generation formula of LFM_BPSK multiplex modulated signal is

7. the real-time production method of LFM_BPSK multiplex modulated signal based on FPGA as described in claim 1, which is characterized in that In step (3), LFM the and BPSK trigonometric function coefficient of generation is stored in RAM, and all RAM include 32 × 16bit memory, The RAM with a clock pulses storage and reads data；The input of multiplier, adder is 16bit, exports and is 32bit, the composite signal of the generation are 32bit.

Technical field

The present invention relates to signal generation technique field, especially a kind of LFM_BPSK multiplex modulated signal based on FPGA is real When production method.

Background technique

Currently, linear FM signal and phase-coded signal are widely used in components of modern Radar system.Its In, linear FM signal has a good distance resolution and radial velocity resolution ratio, and can with the same matched filter come The radar echo signal of different Doppler frequency shifts is handled, greatly simplifies radar echo signal processing system in this way.Phase is compiled Code signal has good anti-interference ability while meeting operating distance and resolving power.LFM_BPSK multiplex modulated signal The advantages of having both LFM signal and bpsk signal causes the concern of people suitable for complicated electromagnetic environment in recent years.

FPGA (online programmable logic array) is widely used in various Digital Signal Processing.It is real-time using fpga chip It is parallel to generate LFM_BPSK multiplex modulated signal, the processing speed of hardware is required to substantially reduce, the timing for improving design can By property.In the production method of traditional LFM signal and multiplex modulated signal, FPGA control DDS chip is read from internal storage Wave data is taken, higher to the resource requirement of FPGA internal storage, real-time and adaptivity are insufficient.Therefore, seek in real time Property it is high, adaptivity is strong and it is necessary to occupy the less multiplex modulated signal production method of FPGA internal storage resources.

Summary of the invention

Technical problem to be solved by the present invention lies in it is real to provide a kind of LFM_BPSK multiplex modulated signal based on FPGA When production method, solve the problems, such as to generate multidiameter delay LFM_BPSK multiplex modulated signal in real time with FPGA.

It is produced in real time in order to solve the above technical problems, the present invention provides a kind of LFM_BPSK multiplex modulated signal based on FPGA Generation method includes the following steps:

(1) road linear frequency-modulated parameter frequency modulation ShuaiμHe Mei output data number M is read from ROM, generates linear frequency modulation letter Number trigonometric function coefficient cos [μ π (m Δ t)²)] and sin [π μ (m Δ t)²], wherein m=0,1,2 ... M-1, Δ ,=1/ f_s, f_sIt is baseband signal samples rate；The trigonometric function coefficient of generation is stored in RAM respectively；

(2) it reads and is stored in binary data C to be encoded in ROM, data length L and every road output data number M, according to The phase value of data determines the symbol of bpsk signal, and forms data sequence cos [2 π f_IΔ t+ θ (m)] and sin [2 π f_IΔt+θ (m)], wherein m=0,1,2 ... M-1, Δ t are as previously mentioned, θ (m)=π d₂And d (m),₂(m) { 0,1 } ∈；By generation Trigonometric function coefficient is stored in RAM respectively；

(3) the trigonometric function coefficient that LFM and bpsk signal are read from RAM carries out LFM signal and bpsk signal orthogonal Modulation, obtains LFM_BPSK multiplex modulated signal

S (m)=exp [j (2 π f_IΔt+μπ(mΔt)²+θ(m))]。

Preferably, FPGA includes sine and cosine functions table memory module, includes respectively the memory block 4096 × 16bit, is used for Storage (2¹⁵- 1) numerical value and (2 of × cos (π/4096 n × 2)¹⁵- 1) numerical value of × sin (π/4096 n × 2), wherein n=0,1, 2...4095；Under the conditions of step (1) (2), respectively with μ π (m Δ t)²With 2 π f_IΔ t+ θ (m) is function of the address from the storage Table searches trigonometric function coefficient, address size 12bit.

Preferably, under the conditions of step (1) (2) (3), m keeps synchronous variation, and each clock pulses completes variation.

Preferably, in step (1), the initial value of 8 tunnel real time data angle of LFM signal is

1st tunnel: Θ (0)=4 μ₀·2^-18

...

I-th tunnel: Θ (i-1)=(i+3) μ₀·2^-18

Wherein μ₀=2³³·(Δt)²μ, length 18bit are passed, i=0,1,2...7 under being calculated by host computer；Q_mIt is a When the clock cycle, 8 circuit-switched data real-time angular of LFM signal is

1st tunnel: Θ (8q_m- 8)=Θ (8q_m-16)+8μ₀(q_m-1)·2^-18

...

I-th tunnel: Θ (8q_m+ i-1)=Θ (8q_m+i-9)+8μ₀(q_m-1)·2^-18

Wherein m=8 × q_m+ i, i=0,1,2 ... 7, Θ (8q_m+ i-9) it is (q_m- 1) LFM signal when a clock cycle The real-time angular variable quantity of i-th road real-time angular, i.e., two neighboring clock cycle each circuit-switched data differs Δ Θ (q_m)-ΔΘ(q_m- 1)=8 μ₀·2^-18。

Preferably, in step (2), binary data C to be encoded can use 2bit~64bit, and data length L is corresponding desirable 1bit~6bit, phase-coded signal precision Δ jm is controllable, is 12bit, related to data length L and every road output data number M； Wherein, to greatly improve address precision, if Δ jmb=Δ jm2²⁸/ 27 be 36bit, is passed under being calculated by host computer；

(21) Q component address generating method: address to 0 or 4096 need to judge that next signal periodic phase is 0 or π, If 0, then unchanged location incremental mode；If π, next signal period extra address increment since 2048 generates new Address code, address code 12bit；

(22) I component address generating method:

When the phase in current demand signal period is 0, if next signal period phase is π, address 3072 is changed to 1024, and Extra address increment generates new address code；If next signal period phase is 0, then on the basis of address 3072 additionally Location increment generates new address code, address code 12bit；

When the phase in current demand signal period is π, if next signal period phase is 0,3072 will be changed at address 1024, And extra address increment generates new address code；If next signal period phase is π, then added on the basis of address 1024 Address increment generates new address code, address code 12bit.

Preferably, in step (3), the generation formula of LFM_BPSK multiplex modulated signal is

Preferably, in step (3), LFM the and BPSK trigonometric function coefficient of generation is stored in RAM, and all RAM include 32 × 16bit memory, the RAM with a clock pulses storage and read data；The input of multiplier, adder is 16bit exports as 32bit, and the composite signal of the generation is 32bit.

The invention has the benefit that the frequency range of baseband signal, variable sample rate in the present invention, the band of LFM signal Wide, radar transmitted pulse width and data length for phase code are controllable；Use FPGA real-time multichannel parallel generation LFM_BPSK multiplex modulated signal significantly reduces the requirement to hardware memory resource, processing speed, conclusion pair of the invention The design of radio frequency target simulator has important theory directive significance.

Detailed description of the invention

Fig. 1 is method flow schematic diagram of the invention.

Fig. 2 be the bpsk signal of 64 ' h0 the present invention is based on the FPGA binary data to be encoded generated and bandwidth is The composite signal schematic diagram that 50MHz, the LFM signal modulation that time width is 100 μ s generate.

It is 64 ' ha3c6_bdf1_14ce_aa79 that Fig. 3, which is the present invention is based on the binary data to be encoded that FPGA is generated, Bpsk signal schematic diagram.

Fig. 4 is the BPSK that MATLAB of the present invention generates that binary data to be encoded is 64 ' hffff_ffff_ffff_ffff The composite signal theoretical value that the LFM signal modulation that signal and bandwidth are 50MHz, time width is 100 μ s generates emulates schematic diagram.

It is 64 ' hffff_ffff_ffff_ffff that Fig. 5, which is the present invention is based on the binary data to be encoded that FPGA is generated, The composite signal schematic diagram that the LFM signal modulation that bpsk signal and bandwidth are 50MHz, time width is 100 μ s generates.

Specific embodiment

As shown in Figure 1, a kind of real-time production method of LFM_BPSK multiplex modulated signal based on FPGA, including walk as follows It is rapid:

Step 1 reads the road linear frequency-modulated parameter frequency modulation ShuaiμHe Mei output data number M from ROM.8 tunnel of LFM signal The initial value of data real-time angular is

1st tunnel: Θ (0)=4 μ₀·2^-18

...

I-th tunnel: Θ (i-1)=(i+3) μ₀·2^-18

Wherein μ₀=2³³·(1/f_s)²μ, length 18bit are passed, f under being calculated by host computer_sIt is baseband signal samples Rate；I=0,1,2...7.Q_mWhen a clock cycle, 8 circuit-switched data real-time angular of LFM signal is

1st tunnel: Θ (8q_m- 8)=Θ (8q_m-16)+8μ₀(q_m-1)·2^-18

...

I-th tunnel: Θ (8q_m+ i-1)=Θ (8q_m+i-9)+8μ₀(q_m-1)·2^-18

Wherein m=8 × q_m+ i, q_m=2,3 ..., M, i=0,1,2 ... 7, Θ (8q_m+ i-9) it is (q_m- 1) a clock The real-time angular variable quantity of the i-th road of LFM signal real-time angular when the period, i.e., two neighboring clock cycle each circuit-switched data differs Δ Θ (q_m)-ΔΘ(q_m- 1)=8 μ₀·2^-18。

FPGA includes sine and cosine functions table memory module, includes respectively the memory block 4096 × 16bit, for storing (2¹⁵- 1) numerical value and (2 of × cos (π/4096 n × 2)¹⁵- 1) numerical value of × sin (π/4096 n × 2), wherein n=0,1,2...4095.

Being incremented by for each circuit-switched data angle is carried out with adder in the real-time calculating process of FPGA, with angle μ π (the m Δ t) of generation² As address, address size 12bit searches trigonometric function coefficient from the function table of the storage.By the trigonometric function of generation Coefficient is stored in RAM respectively, and RAM includes 32 × 16bit memory, with a clock pulses storage and reads data.

Step 2, reading are stored in binary data C (2bit~64bit) to be encoded in ROM, data length L (1bit ~6bit), address precision Δ jm (12bit) and every road output data number M, the symbol of bpsk signal is determined according to the phase value of data Number.Wherein, to greatly improve address precision, if Δ jmb=Δ jm2²⁸/ 27 be 36bit, is passed under being calculated by host computer.

(1) Q component address generating method: address to 0 or 4096 need to judge that next signal periodic phase is 0 or π, If 0, then unchanged location incremental mode；If π, next signal period extra address increment since 2048 generates new Address code, address code 12bit.

(2) I component address generating method:

When the phase in current demand signal period is 0, if next signal period phase is π, address 3072 is changed to 1024, and Extra address increment generates new address code；If next signal period phase is 0, then on the basis of address 3072 additionally Location increment generates new address code, address code 12bit.

When the phase in current demand signal period is π, if next signal period phase is 0,3072 will be changed at address 1024, And extra address increment generates new address code；If next signal period phase is π, then added on the basis of address 1024 Address increment generates new address code, address code 12bit.

Trigonometric function coefficient is searched from the function table of above-mentioned storage with address code.The trigonometric function coefficient of generation is deposited respectively Enter RAM, RAM includes 32 × 16bit memory, with a clock pulses storage and reads data.

Step 3, the trigonometric function coefficient that LFM and bpsk signal are read from RAM, LFM signal and bpsk signal are carried out Orthogonal modulation obtains LFM_BPSK multiplex modulated signal

S (m)=

{cos[μπ(mΔt)²)]·cos[2πf_IΔt+θ(m)]-sin[πμ(mΔt)²]·sin[2πf_IΔt+θ(m)]}

+j{sin[πμ(mΔt)²]·cos[2πf_IΔt+θ(m)]+cos[μπ(mΔt)²)]·sin[2πf_IΔt+θ (m)]}

=exp [j (2 π f_IΔt+μπ(mΔt)²+θ(m))]

It is emulated in the present invention using ISE/Modelsim+Matlab tool, when emulation changes binary data to be encoded Length and value change the frequency modulation rate and bandwidth of LFM signal, and frequency domain and time-domain-simulation demonstrate correctness of the invention, feasibility And validity.

Fig. 2 be based on the binary data to be encoded that FPGA is generated be 64 ' h0 bpsk signal and bandwidth be 50MHz, when The composite signal schematic diagram that the LFM signal modulation that width is 100 μ s generates.

Fig. 3 is the BPSK letter for being 64 ' ha3c6_bdf1_14ce_aa79 based on the binary data to be encoded that FPGA is generated Number schematic diagram.

Fig. 4 be MATLAB generate the bpsk signal that binary data to be encoded is 64 ' hffff_ffff_ffff_ffff and The composite signal theoretical value that the LFM signal modulation that bandwidth is 50MHz, time width is 100 μ s generates emulates schematic diagram.

Fig. 5 is the BPSK letter for being 64 ' hffff_ffff_ffff_ffff based on the binary data to be encoded that FPGA is generated Number and the composite signal schematic diagram that generates of bandwidth is 50MHz, time width is 100 μ s LFM signal modulation.

It can be seen from the figure that the frequency range of baseband signal of the present invention, variable sample rate, generate bandwidth, radar emission The variable LFM signal of pulse width, the controllable bpsk signal of data to be encoded length, value and LFM_BPSK complex modulated letter Number.