阅读说明：本技术 具有新型栅极电容拓扑结构的器件堆叠 (Device stack with novel gate capacitance topology ) 是由 雅罗斯瓦夫·亚当斯基 于 2018-04-02 设计创作，主要内容包括：描述了用于实际实现包括作为RF放大器工作的晶体管的堆叠的集成电路的系统、方法和设备。随着堆叠高度增加,用于提供在放大器的输出端处的RF电压在堆叠之上的期望分布的栅极电容器的电容值可以降低到接近该集成电路中存在的寄生/杂散电容值的值,这可能会使集成电路的实际实现变得困难。将堆叠中的一个晶体管的栅极处的RF栅极电压耦接至堆叠中的不同晶体管的栅极,可以允许不同晶体管的栅极电容器的电容值的增加,以根据期望分布在不同晶体管的栅极处获得RF电压。(Systems, methods, and devices are described for practical implementation of integrated circuits including stacks of transistors operating as RF amplifiers. As the stack height increases, the capacitance value of the gate capacitor used to provide the desired distribution of RF voltage at the output of the amplifier over the stack may decrease to a value close to the parasitic/stray capacitance value present in the integrated circuit, which may make practical implementation of the integrated circuit difficult. Coupling the RF gate voltage at the gate of one transistor in the stack to the gates of different transistors in the stack may allow for an increase in the capacitance value of the gate capacitors of the different transistors to obtain an RF voltage at the gates of the different transistors distributed as desired.)

1. a monolithic integrated circuit device, comprising:

a stack of a plurality of transistors arranged in a cascode configuration comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or greater than 2, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor; and

N gate capacitors, each of the N gate capacitors connected at a first terminal of each gate capacitor to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected at a second terminal of the at least one gate capacitor to a first terminal of a coupled gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected at a second terminal of each gate capacitor of the remaining gate capacitors to the reference voltage.

2. The monolithic integrated circuit device of claim 1, wherein:

The apparatus is configured to operate as a Radio Frequency (RF) amplifier that provides an amplified version of an RF signal at a gate of the input transistor to a gate of the output transistor, and

Each of the N gate capacitors is configured to control an RF voltage magnitude at the gate of the respective transistor based on an RF voltage at the drain of the respective transistor and a desired distribution of the RF voltage across the stack.

3. The monolithic integrated circuit device of claim 2, wherein the magnitude of the RF voltage at the gates of the respective transistors of the at least one gate capacitor is also controlled by the coupled gate capacitor.

4. The monolithic integrated circuit device of claim 2, wherein:

The coupled gate capacitor is configured to provide a portion of the RF voltage magnitude at the gate of the respective transistor,

The at least one gate capacitor is configured to provide a remaining portion of the RF voltage magnitude, an

The remainder of the RF voltage magnitude is inversely proportional to the capacitance value of the at least one gate capacitor.

5. The monolithic integrated circuit device of claim 4, further comprising an additional gate capacitor connected between the gate of a respective transistor of the at least one gate capacitor and the reference voltage.

6. The monolithic integrated circuit device of claim 1, wherein the integer N is equal to or greater than 5.

7. the monolithic integrated circuit device of claim 6, wherein a respective transistor of the at least one gate capacitor is the output transistor.

8. The monolithic integrated circuit device of claim 2, wherein the desired distribution of the RF voltage across the stack is a substantially equal division of the RF voltage across the stack.

9. the monolithic integrated circuit device of claim 2, wherein the desired distribution of the RF voltage across the stack is an unequal division of the RF voltage across the stack.

10. The monolithic integrated circuit device of claim 1, wherein the plurality of transistors are Metal Oxide Semiconductor (MOS) Field Effect Transistors (FETs) or Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistors (FETs).

11. The monolithic integrated circuit device of claim 10, wherein the plurality of transistors are fabricated using one of: a) silicon On Insulator (SOI) technology, and b) silicon on sapphire technology (SOS).

12. The monolithic integrated circuit device of claim 2, further comprising N resistors, each of the N resistors connected at a first terminal of each resistor to a first terminal of a respective gate capacitor of the N gate capacitors,

wherein the impedance of each resistor is adapted to substantially isolate the RF voltage at the gate of the respective transistor coupled to the first terminal of each transistor from the second terminal of each resistor.

13. The monolithic integrated circuit device of claim 1, wherein the plurality of transistors have the same dimensions.

14. the monolithic integrated circuit device of claim 1, wherein at least one transistor of the plurality of transistors is a different size than the remaining transistors of the plurality of transistors.

15. the monolithic integrated circuit device of claim 1, wherein:

The stack includes a plurality of unit cells arranged in a parallel configuration, each unit cell being a reduced-size replica of the stack, an

Each of the N gate capacitors is distributed over the plurality of unit cells.

16. a monolithic integrated circuit device, comprising:

A stack of N transistors arranged in a cascode configuration comprising an input transistor M1 and N-1 cascode transistors M2, M3, MN, N being an integer equal to or greater than 2, comprising an output transistor MN, the stack being configured to operate between a supply voltage provided at a drain of the output transistor MN and a reference voltage provided at a source of the input transistor M1; and

n-1 gate capacitors C2, C3, …, CN-1, each gate capacitor Ci of the N-1 gate capacitors being connected at a first terminal of each gate capacitor Ci to the gate of a respective transistor Mi of the N-1 cascode transistors, wherein at least one gate capacitor Ck of the N-1 gate capacitors associated with a transistor Mk is connected at a second terminal of the at least one gate capacitor Ck to a first terminal of a coupled gate capacitor Ck-1 of the N-l gate capacitors associated with a transistor Mk-1 adjacent to the transistor Mk, and the remaining gate capacitors C2, C3, …, Ck-2, Ck-1, Ck +1, …, CN of the N-l gate capacitors are connected at a second terminal of each gate capacitor of the remaining gate capacitors to the reference voltage .

17. A monolithic integrated circuit device, comprising:

A stack of a plurality of transistors arranged in a cascode configuration, including an input transistor and a plurality of cascode transistors;

a first gate capacitor connected between a gate of a first cascode transistor of the stacked plurality of cascode transistors and a reference voltage, the first gate capacitor configured to provide a first RF voltage at the gate of the first cascode transistor by means of coupling of the RF voltage at the source of the first cascode transistor; and

A second gate capacitor connected between a gate of a second cascode transistor of the stacked plurality of cascode transistors and a gate of the first cascode transistor, the second gate capacitor configured to couple the first RF voltage to the gate of the second cascode transistor and further to couple the RF voltage at the source of the second cascode transistor to the gate of the second cascode transistor to provide a second RF voltage at the gate of the second cascode transistor,

wherein the first and second RF voltages are based on a desired distribution of RF voltage at an output of the stack across a plurality of transistors of the stack.

18. A method for implementing a monolithic integrated circuit comprising a stack of a plurality of transistors arranged in a cascode structure, the method comprising:

Connecting a first gate capacitor between a gate of the stacked first cascode transistor and a reference voltage;

Coupling an RF voltage at a source of the first cascode transistor to a gate of the first cascode transistor based on the connecting, thereby obtaining a first RF voltage at the gate of the first cascode transistor;

Connecting a second gate capacitor between the gate of the stacked second cascode transistor and the gate of the first cascode transistor;

Coupling the first RF voltage to a gate of the second cascode transistor based on a connection of the second gate capacitor;

Further coupling an RF voltage at the source of the second cascode transistor to the gate of the second cascode transistor based on the connection of the second gate capacitor; and

based on the further coupling, a second RF voltage is obtained at the gate of the second cascode transistor.

19. The method of claim 18, wherein a number of cascode transistors in the stacked plurality of transistors is equal to or greater than 5.

20. The method of claim 18, further comprising:

Establishing an RF voltage at a gate of the second cascode transistor;

Reducing a capacitance value of the second gate capacitor based on the establishing and connection of the second gate capacitor between the gate of the second cascode transistor and the gate of the first cascode transistor, wherein a desired RF voltage is based on a desired distribution of RF voltage at the output of the stack over the plurality of transistors of the stack.

Technical Field

The present application relates generally to electronic circuits and more particularly to amplifiers using multiple stacked transistors operating in a cascode configuration and monolithic integration thereof.

Background

U.S. patent No. 7,248,120, cited above, discusses an integrated amplifier circuit using stacked transistors (e.g., FET transistors) that may be used to control signals that substantially exceed the voltage endurance capabilities of the individual transistors of the stack. Thus, when the individual transistors of the stack are operated within their voltage endurance capabilities, the stack of transistors may be operated according to a higher supply voltage to provide higher output power. The number of stacked transistors may be selected according to the supply voltage, the voltage endurance of the transistors, and the desired distribution (e.g., such as equal distribution) of the supply voltage over the stacked transistors. The biasing of the stacked transistors may provide a desired distribution of the supply voltage over the stacked transistors. Since the output RF signal generated by the stack in response to the input RF signal may have An (AC) voltage substantially greater than the (DC) supply voltage to the stack, U.S. patent No. 7,248,120 cited above uses a (bypass) gate capacitor at the gate of the stacked cascode transistor to enable the gate of the cascode transistor to "float" with the RF signal and thus maintain the distribution of the voltage of the output RF signal among the stacked transistors for safe operation of the transistors. As described in us patent No. 7,248,120, the capacitance value of the gate capacitor is inversely proportional to the position of the respective transistor in the stack; the gate capacitor of the stacked transistor has a reduced capacitance value as the transistor is closer to the output of the stack. As the number of transistors in the stack increases, the capacitance values of the gate capacitors associated with the transistors closer to the output of the stack can decrease to values that may be close to values corresponding to stray/parasitic capacitances in the physical layout of the amplifier circuit, rendering practical implementation of such circuits challenging. It is desirable to provide alternative stack topologies that allow for practical realization of large stack heights in integrated circuits that can operate as amplifiers.

Disclosure of Invention

According to a first aspect of the present disclosure, a monolithically integrated circuit device is presented, the monolithically integrated device comprising: a stack of a plurality of transistors arranged in a cascode configuration, an input transistor thereof and N cascode transistors including an output transistor, N being an integer equal to or greater than 2, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor; n gate capacitors, each gate capacitor of the N gate capacitors connected at a first terminal of the each gate capacitor to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected at a second terminal of the at least one gate capacitor to a first terminal of a coupled gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected at a second terminal of each gate capacitor of the remaining gate capacitors to a reference voltage.

According to a second aspect of the present disclosure, there is provided a monolithic integrated circuit device comprising: a stack of N transistors arranged in a cascode configuration comprising an input transistor M1 and N-1 cascode transistors M2, M3, …, MN comprising an output transistor MN, N being an integer equal to or greater than 2, the stack being configured to operate between a supply voltage provided at the drain of the output transistor MN and a reference voltage provided at the source of the input transistor M1; each gate capacitor Ci of the N-1 gate capacitors C2, C3, …, CN-1, N-1 gate capacitors is connected at a first terminal of said each gate capacitor Ci to the gate of a respective transistor Mi of the N-1 cascode transistors, wherein at least one gate capacitor Ck of the N-1 gate capacitors associated with the transistor Mk is connected at a second terminal of the at least one gate capacitor Ck to a first terminal of a coupling gate capacitor Ck-1 of the N-1 gate capacitors associated with a transistor Mk-1 adjacent to the transistor Mk, and the remaining gate capacitors C2, C3, …, Ck-2, Ck-1, Ck +1, …, CN of the N-1 gate capacitors are connected to a reference voltage at the second terminal of each of the remaining gate capacitors.

According to a third aspect of the present disclosure, a monolithic integrated circuit device is proposed, comprising: a stack of a plurality of transistors arranged in a cascode configuration, including an input transistor and a plurality of cascode transistors; a first gate capacitor connected between a gate of a first cascode transistor of the stacked plurality of cascode transistors and a reference voltage, the first gate capacitor configured to provide a first RF voltage at the gate of the first cascode transistor by means of coupling of the RF voltage at the source of the first cascode transistor; and a second gate capacitor connected between a gate of a second cascode transistor of the stacked plurality of cascode transistors and the gate of the first cascode transistor, the second gate capacitor configured to couple the first RF voltage to the gate of the second cascode transistor and also to couple the RF voltage at the source of the second cascode transistor to the gate of the second cascode transistor to provide a second RF voltage at the gate of the second cascode transistor, wherein the first RF voltage and the second RF voltage are based on a desired distribution of the RF voltage at the output of the stack over the stacked plurality of transistors.

according to a fourth aspect of the present disclosure, there is provided a method for implementing a monolithic integrated circuit comprising a stack of a plurality of transistors arranged in a cascode configuration, the method comprising: connecting a first gate capacitor between a gate of the stacked first cascode transistor and a reference voltage; based on the connection, coupling the RF voltage at the source of the first cascode transistor to the gate of the first cascode transistor, thereby obtaining a first RF voltage at the gate of the first cascode transistor; connecting a second gate capacitor between the gate of the stacked second cascode transistor and the gate of the first cascode transistor; coupling the first RF voltage to a gate of the second cascode transistor based on the connection of the second gate capacitor; further coupling the RF voltage at the source of the second cascode transistor to the gate of the second cascode transistor based on the connection of the second gate capacitor; and based on the further coupling, obtaining a second RF voltage at the gate of the second cascode transistor.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

drawings

the accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments of the present disclosure and, together with the description of the example embodiments, serve to explain the principles and implementations of the disclosure.

Fig. 1 shows a simplified schematic representation of a prior art Radio Frequency (RF) amplifier (100) using a transistor stack comprising a plurality of series-connected transistors (M1, …, M6), including an input transistor (M1), an output transistor M6, and a cascode transistor (M2, …, M6). The bias voltages (Vg 2bias, …, Vg6 bias) for the cascode transistors provide the desired distribution of the supply voltage Vbatt across the stacked transistors, while the gate capacitors (C2, …, C6) coupled to the gates of the cascode transistors (M2, …, M6) maintain the desired distribution of the RF voltage at the drain of the output transistor M6 across the stacked transistors.

Fig. 2 shows a simplified schematic representation of an RF amplifier (200) based on the prior art RF amplifier (100) of fig. 1, according to an embodiment of the present disclosure, wherein the gate capacitors of two adjacent transistors in a stack of six transistors are coupled to allow for a higher capacitance value of the gate capacitors while maintaining a desired distribution of the RF voltage at the drain of the output transistor M6 between the stacked transistors. In the exemplary embodiment depicted in fig. 2, the gate capacitor C6 of the output transistor M6 is coupled to the gate capacitor C5 of the transistor M5.

Fig. 3 shows a simplified schematic representation of an RF amplifier (300) based on the embodiment of fig. 2, according to an embodiment of the present disclosure, wherein the gate capacitors of adjacent transistors in a transistor stack comprising n transistors are coupled to allow a higher capacitance value of the gate capacitors, while maintaining a desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked n transistors. In the exemplary embodiment depicted in FIG. 3, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-1) of transistor M (n-1), which in turn is coupled to the gate capacitor C (n-2) of transistor M (n-2).

Fig. 4A shows a simplified schematic representation of an exemplary implementation (400A) of the RF amplifier (100) depicted in fig. 1, the RF amplifier (100) being extended to n stacked transistors (M1, M2, …, Mn) instead of six. As can be seen in fig. 4A, the RF amplifier (100) can include a plurality (k) of unit cells (401, 402, …, 40k) coupled in a parallel configuration, each unit cell including a reduced-size transistor stack including reduced-size transistors (e.g., transistors M11, M21, …, Mn1 of unit cell 401). The reduced size transistor stack may be considered a reduced size replica of the transistor stack (M1, M2, …, Mn). The downsized transistors can each be regarded as a transistor unit element; each transistor (M1, M2.., Mn) of the stack is represented by k parallel transistor cells (e.g., M1 ═ Mn1// Mn 2//.// Mnk). Gate capacitors (C2, C3, …, Cn) to the gates of the stacked transistors (M1, M2,. cndot., Mn) are distributed among the unit cells (401, 402, …, 40 k). For example, gate capacitors Cn to the gates of the output transistors Mn are distributed among capacitors (Cn1, Cn2, …, Cnk), and the capacitors (Cn1, Cn2, …, Cnk) are respectively coupled to the transistor unit elements (Mn1, Mn2, …, Mnk) of the output transistors Mn, where Cn ═ Cn1// Cn2// ·///Cnk.

Fig. 4B shows a simplified schematic representation of an exemplary implementation (400B) of the RF amplifier (200) depicted in fig. 2, the RF amplifier (200) being extended to n stacked transistors (M1, M2, …, Mn) instead of six. This representation is similar to that described with respect to fig. 4B with respect to the prior art RF amplifier (100). As can be seen in fig. 4B, the gate capacitors Cn and C (n-1) are coupled to each other by means of their distributed capacitors (Cn1, Cn2, …, Cnk) and (C (n-1)1, C (n-1)2, …, C (n-1) k), wherein the distributed capacitor pairs (Cn1, C (n-1)1), (Cn2, C (n-1)2),., (Cnk, C (n-1) k) are coupled.

Fig. 5A shows a simplified schematic representation of an RF amplifier (400A) based on the prior art RF amplifier (100) of fig. 1, according to an embodiment of the present disclosure, wherein the gate capacitors of three adjacent transistors in a stack of six transistors are coupled to allow for a higher capacitance value of the gate capacitors while maintaining a desired distribution of the RF voltage at the drain of the output transistor M6 between the stacked transistors. In the exemplary embodiment depicted in fig. 5A, the gate capacitor C6 of the output transistor M6 is coupled to the gate capacitor C5 of the transistor M5, which in turn is coupled to the gate capacitor C4 of the transistor M4.

Fig. 5B shows a simplified schematic representation of an RF amplifier (500B) based on the prior art RF amplifier (100) of fig. 1, according to an embodiment of the present disclosure, wherein the gate capacitors of five adjacent transistors in a stack of six transistors are coupled to allow for a higher capacitance value of the gate capacitors while maintaining a desired distribution of the RF voltage at the drain of the output transistor M6 over the stacked transistors. In the exemplary embodiment depicted in fig. 5B, the gate capacitor C6 of the output transistor M6 is coupled to the gate capacitor C5 of the transistor M5, in turn to the gate capacitor C4 of the transistor M4, in turn to the gate capacitor C3 of the transistor M3, in turn to the gate capacitor C2 of the transistor M2.

Fig. 5C shows a simplified schematic representation of an RF amplifier (500C) based on the embodiment of fig. 3, according to an embodiment of the present disclosure, wherein the gate capacitors of adjacent transistors in a transistor stack comprising n transistors are coupled to allow a higher capacitance value of the gate capacitors, while maintaining a desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked n transistors. In the exemplary embodiment depicted in FIG. 5C, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-1) of transistor M (n-1), which in turn is coupled to the gate capacitor C (n-2) of transistor M (n-2). In addition, the gate capacitor C3 of the transistor M3 is coupled to the gate capacitor C2 of the transistor M2.

fig. 6A, 6B, 6C and 6D show graphs representing simulated performance of the prior art RF amplifier (100) of fig. 1 and the RF amplifier (200) of the present disclosure according to fig. 2. Such analog performance is based on the distribution of the RF voltage at the drain of output transistor M6 over the stacked transistors (fig. 6A for RF amplifier 100 and fig. 6B for RF amplifier 200) and the output power (dBm) response and Power Added Efficiency (PAE) of the RF amplifier relative to the input power (dBm) to the amplifier (fig. 6C for RF amplifier 100 and fig. 6D for RF amplifier 200).

Fig. 7 shows a simplified schematic representation of an RF amplifier (700) based on the embodiment of fig. 3, wherein the gate capacitors of non-adjacent transistors in a transistor stack comprising n transistors are coupled to allow a higher capacitance value of the gate capacitors, while maintaining a desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked n transistors, according to an embodiment of the present disclosure. In the exemplary embodiment depicted in FIG. 7, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-2) of the transistor M (n-2).

Fig. 8 shows a simplified schematic representation of an RF amplifier (800) based on the embodiment of fig. 7, according to an embodiment of the present disclosure, wherein the gate capacitors of non-adjacent transistors in a transistor stack comprising n transistors are coupled to allow a higher capacitance value of the gate capacitors while maintaining a desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked n transistors. In the exemplary embodiment depicted in FIG. 8, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-2) of the transistor M (n-2), and the gate capacitor C (n-1) of the output transistor M (n-1) is coupled to the gate capacitor C3 of the transistor M3.

Fig. 9 shows a simplified schematic representation of an RF amplifier (900) based on the embodiment of fig. 3, wherein the gate capacitors of the transistors in the transistor stack comprising n transistors are coupled to allow a higher capacitance value of the gate capacitors, while maintaining a desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked n transistors, according to an embodiment of the present disclosure. In the exemplary embodiment depicted in FIG. 9, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-1) of the transistor M (n-1), which in turn is coupled to the gate capacitor C (n-2) of the transistor M (n-2). An additional gate capacitor C' (n-1) coupled to the gate of transistor M (n-1) may be used to further adjust the gate capacitance at the gate of transistor M (n-1) in order to provide the desired effective voltage at the gate.

Fig. 10 is a flow diagram (1000) illustrating steps of a method of implementing a monolithic integrated circuit including a stack of multiple transistors arranged in a cascode configuration, according to an embodiment of the present disclosure.

like reference numbers and designations in the various drawings indicate like elements.

Detailed Description

Fig. 1 shows a simplified schematic representation of a prior art Radio Frequency (RF) amplifier (100), the RF amplifier (100) using a transistor stack arranged in a cascode configuration, the transistor stack comprising a plurality of series-connected transistors (M1, …, M6) including an input transistor (M1), an output transistor M6 and a cascode transistor (M2, …, M6). Power to the stack is provided via a supply voltage Vbatt coupled through inductor L10 to output transistor M6, and with reference to a reference potential Gnd coupled to the source of input transistor M1. The input signal RFin supplied to the input transistor M1 through the dc blocking capacitor C1 is amplified by the stack and supplied to the drain of the output transistor M6, and supplied to the load RL through the dc blocking capacitor C20. The gain of the transistor stack (M1, M2, …, M6) may be provided by the transconductance of the input transistor M1, based on the bias of the input transistor, including the gate bias voltage Vglbias provided to the gate node Vgl of the input transistor M1. In particular, the voltage at the gate node Vg1 sets the Desired (DC) bias current through the stack.

With further reference to FIG. 1, for a given semiconductor technology, the greater the supply voltage Vbatt, the greater the number of transistors in the stack required to support the supply voltage Vbatt, and the semiconductor technology establishes the voltage endurance (e.g., with respect to breakdown voltage) of the transistors. The cascode transistors (M2, …, M6) are biased by bias voltages Vg2bias, …, Vg6bias provided to gate nodes Vg2, …, Vg6 of the cascode transistors. The bias voltages Vg2bias, …, Vg6bias are adapted to provide a desired distribution of the (DC) voltage at the drain node Vd6 of the output transistor M6 over the stacked transistors without an input RF signal RFin to the input transistor M1. In other words, such bias voltages Vg2bias, …, Vg6bias are adapted to distribute the voltage provided by the supply voltage Vbatt between the stacked transistors (M1, M2, …, M6). While in most cases it is desirable that the distributions be equal distributions, other unequal (e.g., asymmetric) distributions based on design and performance goals are also possible. More information regarding the biasing of the stack including the input transistor M1 and the cascode transistors (M2, …, M6) may be found, for example, in the above-referenced U.S. patent No. 7,248,120 and published U.S. application No. 2015/0270806a1, the entire disclosure of which is incorporated herein by reference. As used herein, the withstand voltage may refer to a maximum value of a desired voltage between any two terminals (e.g., source, drain, gate) of a transistor based on the desired performance of the transistor and the breakdown voltage of the transistor. It should be understood by those skilled in the art that although a transistor may operate near the breakdown voltage, the closer the transistor operates near the breakdown voltage, the more statistically the transistor is susceptible to damage (e.g., shorter life expectancy). Accordingly, the withstand voltage may be defined as a voltage that is less than the breakdown voltage of the transistor, which may provide a desired life expectancy and/or performance of the transistor.

With continued reference to fig. 1, when an input RF signal RFin is applied to the gate of the input transistor M1, a corresponding RF voltage (i.e., AC voltage) component appears at the drain nodes Vd1, Vd2, ·, Vd6, with an increasing amplitude at the higher nodes. Such RF voltages at the drain nodes Vd1, Vd2, …, Vd6 can be coupled to the gate nodes Vg2, Vg3, …, Vg6 through gate-source capacitances Cgs2, Cgs3, …, Cgs6, the values of which are a function of the semiconductor technology and the size of the respective transistors stacked. It should be noted that the transistors (M1, M2, …, M6) may not necessarily be of the same semiconductor technology and the same size, as these parameters may vary depending on the desired design goals and performance of the RF amplifier (100). Resistors (R1, R2, …, R6) are used to isolate the bias circuit generating bias voltages Vglbias, Vg2bias, …, Vg6bias from the RF voltages present at the gate nodes Vg1, Vg2, …, Vg 6. It should also be noted that the cascode transistors (M2, … M6) may have non-negligible gate-drain capacitance. Such gate-drain capacitance may undergo miller multiplication, which can effectively make such capacitance larger. However, the Cgs capacitance and any capacitance from the gate of the cascode transistor to ground set the impedance seen into the cascode transistor and the voltage at the source node to a first magnitude. In practice, a small adjustment may be required to compensate for the Cgd effect in order to obtain the desired voltage at the gate node.

Since the input RF signal RFin to the RF amplifier (100) of fig. 1 is amplified by the stack, a corresponding amplified RF signal appears at the drain node Vd6, and the RF voltage amplitude of the drain node Vd6 having AC and DC components may be twice as large as the supply voltage Vbatt. The gate capacitors C2, …, C6 allow the voltages at the gate nodes Vg2, ·, Vg6 to float, i.e., for the stack to operate more efficiently, to vary with the RF signal at the respective drain nodes Vd2, …, Vd6, thereby allowing control of the voltage drop between the stacked transistors and preventing excessive stress (e.g., voltage exceeding the withstand voltage) on any transistor of the stack. In particular, and as described in the above-referenced U.S. patent No. 7,248,120, which is incorporated herein by reference in its entirety, the capacitance values of the gate capacitors C2, …, C6 are configured to: by controlling the magnitude of the coupled RF voltage at the gate nodes Vg2, …, Vg6 via the respective gate-source capacitances Cgs2, …, Cgc6, a desired distribution of the RF voltage at the drain node Vd6 over the stacked transistors M1, M2, …, M6 is maintained, such as, for example, an equal or substantially equal voltage distribution (division) between the transistors M1, M2, …, M6.

To provide a desired voltage distribution (e.g., an equal voltage distribution) of the RF voltage at the drain node Vd6 over the stack of the RF amplifier (100) of fig. 1, the capacitance values of the gate capacitors C2, …, C6 become progressively smaller (e.g., inversely proportional to the position of the respective transistors in the stack) and may become sufficiently small at the top of the stack such that their values may be comparable to the parasitic/stray capacitance of the respective circuit layout of the stack. The progressively smaller gate capacitors may provide progressively larger voltage swings at the gate nodes Vg2,..... times, Vg6 of transistors M2, …, M6 to act in concert with the progressively larger voltage swings at the drain nodes Vd1, …, Vd6 of transistors M1, …, M6 to ensure a desired voltage profile (e.g., equal voltage division between transistors M1, …, M6). For example, the RF voltage at the drain node Vd5 drives the series connected capacitors C6 and Cgs 6. To increase the RF voltage swing at the gate node Vg6, the capacitance value of gate capacitor C6 may be made small relative to the capacitance value of capacitor Cgs 6.

In the exemplary case where the overall size of the RF amplifier (100) of fig. 1 is 20mm, where the transistors M1, …, M6 each have a gate length of 0.11 μ M, the capacitance value of C6 may be of the order of 1.5pF for an equal voltage distribution over the transistors M1, …, M6. This low capacitance value is comparable to the parasitic/stray capacitance of the layout of the RF amplifier circuit. Those skilled in the art will appreciate that the overall size of the RF amplifier (100) may be related to the number k of unit cells (401, 402, …, 40k) of the transistor stack M1.., M6 as described later in fig. 4A and 4B. According to an exemplary embodiment of the present disclosure, the capacitance value of the gate capacitor C2,.., C6 for a given desired distribution may be set with the aid of an optimization-capable circuit simulation software tool. During normal operation of the RF amplifier circuit, simulation targets may be set to achieve a desired voltage distribution, e.g., equal voltage division. While the capacitance value of such a gate capacitor may be pre-calculated for a given voltage distribution, when such extracted parasitic/stray capacitances are taken into account, simulations using the extracted parasitic/stray capacitances and re-optimization of the capacitance value of the gate capacitor may still be required.

as the capacitance value of the gate capacitor of the stacked upper transistors (e.g., M5, M6) described in fig. 1 approaches the parasitic/stray capacitance, the design of the stack for the desired voltage distribution may become more difficult and less predictable, and in some cases, even infeasible, as the parasitic/stray capacitance may have a value greater than the gate capacitance. Various stacking topologies (e.g., fig. 2 and the previous and following descriptions) in accordance with the present teachings allow for larger gate capacitance values for a given desired voltage distribution and a given semiconductor technology and stacked transistor size as compared to the prior art structure of fig. 1. This in turn allows for a greater stack height for a greater output power of the RF amplifier, or the use of a greater number of smaller sized transistor devices (e.g., having a smaller withstand voltage) for a given output power of the RF amplifier.

Fig. 2 shows a simplified schematic representation of an RF amplifier (200) based on the prior art RF amplifier (100) of fig. 1, wherein the desired distribution of the RF voltage at the drain Vd6 of the output transistor M6 over the stacked transistors M1, M2, …, M6 may be provided using gate capacitors C2, C3, …, C6 of larger capacitance values when compared to the structure depicted in fig. 1, according to an embodiment of the present disclosure. Similar to the structure depicted in fig. 1, the stacked structure depicted in fig. 2 may be used for any equal or unequal desired voltage distribution and use of transistors according to the same or different semiconductor technologies and/or dimensions.

in order to provide a desired voltage distribution over the stack, the voltage swing at the gate nodes Vg2, · Vg6 of the transistors M2, …, M6 may be progressively larger to act in concert with the progressively larger voltage swings at the drain nodes Vd1, …, Vd6 of the transistors M1, …, M6, in accordance with the RF amplifier (200) according to the present disclosure, described with continued reference to fig. 2. Control of the voltage swing at the gate node of the stacked transistors may be provided by the ratio of the capacitance of the gate capacitor to the capacitance of the respective gate-source capacitor (e.g., proportional to Cgsn/Cg).

As can be seen in fig. 2, the voltage swing at the gate nodes (Vg2, Vg3, Vg4) of the stacked lower transistors (M2, M3, M4) is provided by the ratio of the corresponding capacitance pairs (C2, Cgs2), (C3, Cgs3), (C4, Cgs4), which determine the level of coupling of the drain voltage (Vd1, Vd2, Vd3) to the gate nodes (Vg2, Vg3, Vg4) (C2, Cgs2), (C3, Cgs3), (C4, Cgs 4). However, as can be seen in fig. 2, by adding the voltage swing provided at the gate node Vg5 to the gate node Vg6, the voltage swing at the upper gate node Vg6 becomes larger, thus reducing the required coupling level of the drain voltage Vd5 to the gate node Vg6 for a given desired voltage swing at the gate node Vg 6. In other words, by adding the voltage at the gate node Vg5 to the gate node Vg6, a larger gate capacitor C6 may be used at the gate node Vg6 to provide the desired voltage swing. Similarly, the coupling of the two gate nodes (Vg5, Vg6) via the two gate capacitors (C5, C6) also increases the voltage swing at the gate node Vg5, and thus a larger gate capacitor C5 may be used for a given desired voltage swing at the gate node Vg 5. As used herein, the gate capacitor C5 may be referred to as a "coupled gate capacitor," which gate capacitor C5 is connected to the gate node Vg5 and is coupled to the gate node Vg6 via its connection to the gate capacitor C6.

For the stacked upper transistors (M5, M6), the gate capacitor topology according to the present disclosure described in fig. 2 may allow the use of larger gate capacitors (C5, C6) while providing a desired distribution of the RF voltage at the drain node of the output transistor (e.g., M6) over the stacked transistors (M1, M2, …, M6), the stack having a capacitance value substantially larger than the parasitic/stray capacitance of the respective circuit layout. Higher stack heights may thus be allowed to be achieved in accordance with the teachings of the present disclosure, wherein, as depicted in fig. 3, the stack height n may be any integer value greater than 2, such as 3, 4, 5, 6, 7, 8,9, and so forth. As the stack height n increases, it may be desirable to apply the present teachings to more than two upper transistors of the stack. According to an exemplary embodiment of the RF amplifier (200) of fig. 2, where n is 6, for equal distribution of the RF voltage at the drain node Vd6, gate capacitance values (30.0pF, 7.51pF, 4.08pF, 5.37pF, 8.25pF) of the gate capacitors (C2, C3, C4, C5, C6) may be provided instead of the gate capacitance values (30.1pF, 7.99pF, 3.93pF, 2.62pF, 1.93pF) provided for the prior art structure described in fig. 1. When compared to the prior art structure of fig. 1, one skilled in the art will appreciate the substantially larger capacitance values of the upper gate capacitors (C5, C6) in the structure according to the present disclosure depicted in fig. 2.

Fig. 3 shows a simplified schematic representation of an RF amplifier (300) based on the RF amplifier (200) of fig. 2, wherein a plurality of n transistors (M1, M2,. ·, Mn) are used in a cascode stacked configuration, according to an embodiment of the present disclosure. The desired distribution of the RF voltage at the drain Vdn of the output transistor Mn in the stacked transistors M1, M2, …, Mn may be provided by the gate capacitors C2, C3, …, Cn of larger capacitance values, when compared to the structure based on the structure described in fig. 1. The stacked structure depicted in fig. 3 may be used for any equal or unequal desired voltage distribution and with transistors according to the same or different semiconductor technology and/or dimensions.

As can be seen in fig. 3, for a given desired distribution of the RF voltage at the drain node Vdn of the output transistor Mn over the stacked transistors (M1, M2, …, Mn), a larger gate capacitance value of the gate capacitor can be allowed by a corresponding increased voltage swing at any of the gate nodes (Vg (n-2), Vg (n-1), Vgn) coupled to the gate capacitor (C (n-2), C (n-1), Cn) of the upper transistor (M (n-2), M (n-1), Mn) of the stack (M1, M2,. ·, Mn), as described with respect to the capacitors (C5, C6) of fig. 2. As depicted in fig. 4A and 4B, where the cascode stack includes a plurality (k) of unit cells, such larger capacitance values (C1, C2, …, Cn) may be distributed over the plurality of unit cells (401, 402, …, 40k) while maintaining the capacitance values (e.g., Cn1, Cn2, …, Cnk) coupled to the gate of each of the plurality of unit cells to a value greater than the value of the parasitic/stray capacitance corresponding to the circuit layout of the unit cell.

fig. 4A is a simplified schematic representation showing an exemplary implementation (400A) of the RF amplifier (100) depicted in fig. 1, the RF amplifier (100) being extended to n stacked transistors (M1, M2, …, Mn), where n may be any integer greater than 2. As can be seen in fig. 4A, the RF amplifier (100) may include a plurality (k) of unit cells (401, 402, …, 40k) coupled in a parallel configuration, each unit cell (e.g., 401) including a reduced size transistor stack including reduced size transistors (e.g., transistors M11, M21, …, Mn1 of unit cell 401). The downsized transistors can each be regarded as a transistor unit element; each transistor (M1, M2, …, Mn) of the stack is represented by k parallel transistor cells (e.g., M1 ═ Mn1// Mn2// ·/Mnk). Although not shown in fig. 4A, it is readily understood by those skilled in the art that each transistor unit cell (e.g., Mn1, Mn2, …, Mnk of transistor Mn) may inherently include a gate-source capacitance that is a function of the respective semiconductor technology of each transistor unit cell, where the sum of these gate-source capacitances (i.e., the parallel equivalent) constitutes the gate-source capacitance Cgsn of transistor M1 depicted in fig. 3. Gate capacitors (C2, C3, …, Cn) coupled to the gates of the stacked transistors (M1, M2, …, Mn) are distributed over the unit cells (401, 402, …, 40 k). For example, the gate capacitors Cn coupled to the gates of the output transistors Mn are distributed over capacitors (Cn1, Cn2, …, Cnk), and the capacitors (Cn1, Cn2, …, Cnk) are respectively coupled to the transistor unit cells (Mn1, Mn2, …, Mnk) of the output transistors Mn, wherein Cn1// Cn 2////// Cnk.

With further reference to fig. 4A, it is readily understood by those skilled in the art that the distribution of the gate capacitors (C2, C3, …, Cn) over the unit cells (401, 402, …, 40k) can reduce the impact of parasitic/stray capacitance on the capacitance value of such gate capacitors by reducing the trace length between the gate capacitors and the gates of the associated transistors in the plurality of unit cells. However, as described above, as the stack height increases (a greater value of n), the gate capacitance value of the upper transistor of the stack (e.g., Mn, M (n-1),. for example.) may be reduced for a given desired distribution, and thus the effect of this reduction may be further amplified by the need to distribute the gate capacitors over multiple unit cells. According to an embodiment of the present disclosure, it follows that the capacitance value of the gate capacitor (Cn, C (n-1)),. of the upper transistor (Mn, M (n-1)),. of the stack (M1, M2, …, Mn) may be increased by coupling the gate voltages of adjacent transistors in the stack via coupling of the gate capacitors in a manner similar to that described above with respect to the gate capacitor (C5, C6) of fig. 2. By increasing the capacitance value of such a gate capacitor, the correspondingly distributed gate capacitance value may have a value larger than the parasitic/stray capacitance described above. For example, as shown in fig. 4B, the coupling of the gate capacitors (C (n-1), Cn) provides additional voltage swing at the gate nodes (Vg (n-1), Vgn) via the coupling of the respective distribution capacitors, and thus allows for a greater total capacitance value coupled to such gate nodes, wherein the total capacitance value is provided via the distribution capacitances (Cn1, Cn2, …, Cnk) associated with the gate capacitors Cn and the distribution capacitances (C (n-1)1, C (n-1)2, …, C (n-1) k) associated with the gate capacitor C (n-1). It should be noted that although, in the exemplary embodiment of the present disclosure described in accordance with fig. 4B, the gate capacitor C (n-1) j of each of the k unit elements M (n-1) (j ═ 1 to k) forming the transistor M (n-1) is shown as being coupled to the respective gate capacitor of each unit element Mnj forming the transistor Mn, other exemplary embodiments are possible in which only some, but not all, such capacitors are coupled between the respective unit elements of the transistors M (n-1) and Mn.

the gate capacitor topology according to the present disclosure allows for a practical implementation of a cascode stack of increased height. Although the stacked upper transistor may benefit most from the present teachings because the gate capacitance value is progressively reduced with higher (closer to the output transistor) positions of the stacked transistors, it should be noted that the present teachings may be equally applied to other cascode transistors of the stack as described in the exemplary structures in accordance with the present disclosure of fig. 5A, 5B, and 5C. The exemplary gate topology described in fig. 5A couples the gate capacitors (C4, C5, C6) of the upper three transistors (M4, M5, M6) of the stack to provide additional voltage swing at the gate nodes (Vg4, Vg5, Vg6) for an increase in the gate capacitance values of the gate capacitors. Similarly, the example gate topology described in fig. 5B couples the gate capacitors (C2, C3, C4, C5, C6) of all the cascode transistors (M2, M3, M4, M5, M6) of the stack to provide additional voltage swing at the gate nodes (Vg2, Vg3, Vg4, Vg5, Vg6) for an increase in the gate capacitance value of the gate capacitors. Finally, the exemplary gate topology depicted in fig. 5C couples the gate capacitors (Cn, C (n-1), C (n-2)) of the upper three transistors (Mn, M (n-1), M (n-2)) and the gate capacitors (C2, C3) of the bottom two (cascode) transistors (M2, M3) of the stack to provide additional voltage swings at the gate nodes (Vgn, Vg (n-1), Vg (n-2)) and (Vg2, Vg3) for an increase in the gate capacitance value of the gate capacitors. Such different configurations as depicted in fig. 5A, 5B, and 5C may address practical implementation issues where unequal RF voltage distributions may be required between stacked transistors, for example, when stacked transistors have different withstand voltages and/or are designed for different performance.

With further reference to the structure described in fig. 5C, a practical implementation of a respective integrated circuit resulting in a plurality of connected gate capacitors may take into account the height n of the stack, the gate length of each transistor of the stack (which defines the respective gate-source capacitance), and the amount of parasitic/stray capacitance expected in the layout of the integrated circuit. Further considerations may be based on the desired distribution of the RF voltage at the top of the stack (output transistor) over the stacked transistors. For example, for a stack with a height n-6, transistor device size of 10.8mm and 130nm semiconductor process, it may be necessary to connect at least one gate capacitor C6 of the stacked upper transistor M6 according to the topology of the present disclosure as depicted in fig. 2 to increase the capacitance value beyond the parasitic/stray capacitance of the intended circuit layout. In an exemplary case, this may result in the capacitance value of C6 being equal to 8.25pF instead of the value 1.93pF for the prior art structure of fig. 1. For a stack height n-7, the gate capacitors (C6, C7) of the upper two transistors (M6, M7) of the stack may need to be connected according to the present teachings as described in fig. 5A to increase their capacitance values beyond the parasitic/stray capacitance of the intended circuit layout and make the implementation of the stack more practical. In an exemplary case, this may result in the respective capacitance values of C6 and C7 being equal to 11.43pF and 5.42pF, rather than the respective values of 1.45pF and 1.07pF for the prior art structure of fig. 1.

Fig. 6A, 6B, 6C and 6D show graphs representing simulated performance of a prior art RF amplifier (100) and RF amplifier (200) according to the present disclosure. This analog performance is based on the distribution of the RF voltage at the drain of output transistor M6 over the stacked transistors (fig. 6A for RF amplifier 100 and fig. 6B for RF amplifier 200) and the output power response (dBm) and Power Added Efficiency (PAE) of the RF amplifier relative to the input power (dBm) of the amplifier (fig. 6C and 6D, where PAE is denoted by DE). As can be seen in fig. 6A and 6B, the biasing of the transistor stacks of the two RF amplifiers (100, 200) provides substantially the same partial voltage (Vds1, Vds2, …, Vds6) with different gate capacitance values as described above, wherein the low gate capacitance values of the RF amplifiers (100) may cause practical implementation difficulties of the respective integrated circuits. Similarly, as can be seen in graph 6C (associated with RF amplifier 100) and in fig. 6D (associated with RF amplifier 200), the response output power (denoted Pout _ dBm) and PAE (denoted DE) of the two RF amplifiers (100, 200) are substantially the same. Such performance data indicates that the gate topology according to the present teachings can enable higher stack implementations based on RF amplifiers to be made practical without sacrificing performance.

Although various stacking topologies in accordance with the present teachings discussed above illustrate the coupling of gate capacitors of stacked adjacent transistors, these exemplary embodiments should not be considered limiting to the present disclosure, as other topologies for coupling non-adjacent stacked gate capacitors are also contemplated, such as shown in fig. 7 and 8. The coupling of the gate capacitor can thus be performed freely and based on design and performance objectives. Thus, a combination of coupled gate capacitors of adjacent transistors and non-adjacent transistors is possible. For example, as shown in FIG. 7, the gate capacitor Cn of the output transistor Mn is coupled to the gate capacitor C (n-2) of the transistor M (n-2) and not to the gate capacitor C (n-1) of the adjacent transistor M (n-1). Based on the desired increase in the RF voltage swing at the upper gate node Vgn, the voltage swing of the lower gate node (e.g., Vg (n-2)) may be provided by coupling the associated gate capacitors (e.g., Cn and C (n-2)). Fig. 8 shows a stacking topology based on the stacking topology shown in one of fig. 7, wherein the coupling of the gate capacitors C (n-1) and C3 is provided in addition to the coupling between the gate capacitors Cn and C (n-2) to increase the RF voltage swing at the gate node Vg (n-1) and the RF voltage swing at the gate node Vg3, and thus increase the capacitance value of the gate capacitor C (n-1) based on the desired distribution of the RF voltage at the drain of the output transistor Mn over the stacked transistors.

It should be noted that although in most cases the stray/parasitic capacitances may be associated with respective uncontrollable and/or lowest possible capacitance values (e.g. inherent design/implementation), it is also possible to control the value of such capacitances to further control the gate voltage for a desired distribution of the RF voltage at the drain of the stacked output transistors. Thus, the gate capacitor may be considered to be associated with a combination of additional capacitors and controlled/uncontrolled stray/parasitic capacitances. Referring to FIG. 9, an additional gate capacitance, e.g., C' (n-1), may be provided to the gate of the transistor (e.g., M (n-1)) of the transistor stack (M1, …, Mn) to further adjust the gate capacitor at the gate of the transistor (e.g., M (n-1)) to provide a desired effective RF voltage at the gate. As mentioned above, such additional capacitance may be provided by any means known to those skilled in the art, including via controlled stray/parasitic capacitance. Although an additional capacitance is shown as being provided to the gate of transistor M (n-1), those skilled in the art will appreciate that similar additional capacitance may be added to any gate of the stacked cascode transistors (M2, M3, …, Mn) depending on the requirements of the design performance and objectives.

Fig. 10 is a flow chart (1000) illustrating various steps of a method for implementing a monolithic integrated circuit comprising a stack of multiple transistors arranged in a cascode configuration, according to an embodiment of the present disclosure. As can be seen in the flowchart (1000), the method comprises: connecting a first gate capacitor between the gate of the stacked first cascode transistor and a reference voltage (step 1010); based on the connection, coupling the RF voltage at the source of the first cascode transistor to the gate of the first cascode transistor, thereby obtaining a first RF voltage at the gate of the first cascode transistor (step 1020); connecting a second gate capacitor between the gate of the stacked second cascode transistor and the gate of the first cascode transistor (step 1030); coupling the first RF voltage to the gate of the second cascode transistor based on the connection of the second gate capacitor (step 1040); further coupling the RF voltage at the source of the second cascode transistor to the gate of the second cascode transistor based on the connection of the second gate capacitor (step 1050); and based on the further coupling, obtaining a second RF voltage at the gate of the second cascode transistor (step 1060).

The embodiments described herein are exemplified by N-type mosfet (nmos) transistor devices, which, as shown in the above figures, serve as the primary conductive elements of the RF amplifiers (e.g., 100, 200). Such devices may be part of a stack, wherein a plurality of such devices are connected in series so as to operate as a cascode, for example as shown in fig. 1 and 2. One of ordinary skill in the art will readily apply the inventive concepts disclosed herein to other types of semiconductor devices (e.g., P-type MOSFET devices). For example, in the case of a stack of P-type mosfet (pmos) devices, a supply voltage (e.g., Vbatt) may be coupled to the input transistors of the stack and a reference voltage coupled to the output transistors of the stack. In another example, the stack may include a PMOS device and an NMOS device, where the PMOS device is between supply and output and the NMOS device is from output to reference (similar to a push-pull configuration), where either of the PMOS and NMOS transistors may use the gate capacitance topology described above. Such a topology may equally apply to differential amplifiers using stacked transistors.

Embodiments may also be applied to extended drain devices, such as Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices and other gate transistors or devices, in accordance with the present invention. Such FET devices may include Metal Oxide Semiconductor (MOS) Field Effect Transistors (FETs), Complementary Metal Oxide Semiconductor (CMOS) FETs, and in particular MOSFETs and CMOSFETs and bulk CMOS fabricated on silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) substrates, according to various embodiments of the present disclosure.

Those skilled in the art will readily appreciate that SOI MOSFET devices (e.g., M1, M2, …, Mn) may be formed as a thin layer of silicon overlying an insulating layer of an SOI substrate. Accordingly, and as is known in the art, SOI MOSFET devices may be referred to as thin film SOI MOSFETs, with thin film referring to the thin silicon layer. It should be noted that various embodiments according to the present disclosure, which will be described below, may be implemented in thin film SOI MOSFET devices. More detailed descriptions of such SOI MOSFET devices may be found, for example, in the above-referenced U.S. application No. 14/945,323, U.S. application No. 15/078,930, and U.S. patent No. 8,987,792B2, the entire disclosures of which are incorporated herein by reference.

The term "MOSFET" as used in this disclosure means any Field Effect Transistor (FET) having an insulated gate and comprising a metal or metal-like insulator semiconductor structure. The term "metal" or "metal-like" includes at least one conductive material (e.g., aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

As should be apparent to one of ordinary skill in the art, various embodiments of the present invention may be implemented to meet a wide variety of specifications. Unless otherwise noted above, the selection of appropriate component values is a matter of design choice, and various embodiments of the present invention may be implemented in any suitable IC technology, including but not limited to MOSFET structures, or in hybrid or discrete circuit form. Embodiments of the integrated circuit may be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, the invention may be implemented in other transistor technologies, for example, bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above inventive concepts are particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes having similar characteristics. The fabrication of CMOS on SOI or SOS enables low power consumption, high ability to withstand high power signals resulting from the stack of FETs during operation, good linearity, and high frequency operation (beyond about 10GHz, especially above about 20 GHz).

Depending on the particular specification and/or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), the voltage levels may be adjusted or the polarity of the voltages and/or logic signals reversed. The processing capabilities of the component voltages, currents and powers can be adjusted as desired, for example, by adjusting the size of the device, connecting "stacked" components (especially FETs) in series to withstand greater voltages and/or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities and/or provide additional functionality of the disclosed circuits without significantly altering the functionality of the disclosed circuits.

A number of embodiments of the invention have been described. It will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus may be performed in a different order than that described. Furthermore, some of the steps described above are optional. Various activities described with respect to the methods described above can be repeatedly performed in serial or parallel fashion.

It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims. (Note that the additional labeling of claim elements is for ease of reference and does not in itself indicate a required ordering or enumeration of elements; furthermore, these labels may be reused in dependent claims to reference additional elements and not considered a sequence of mutually contradictory labels in the beginning.