阅读说明：本技术 隔离型nldmos器件及其制造方法 (Isolated NLDMOS device and manufacturing method thereof ) 是由 段文婷 刘冬华 于 2021-07-07 设计创作，主要内容包括：本发明公开了一种隔离型NLDMOS器件,在P型半导体衬底上形成有一个第一深阱离子注入区和多个第二深阱离子注入区以及P型阱；第一深阱离子注入区和最靠近漏区的第二深阱离子注入区之间具有第一间距；第一深阱离子注入区和各第二深阱离子注入区经过热推进后会整体连通并形成N型深阱；由P型阱的第二侧面到漏区之间的N型深阱组成漂移区；各第二深阱离子注入区之间具有第二间距且各第二深阱离子注入区形成的整体结构将P型阱包围；通过设置第二间距来降低N型深阱对P型阱的P型浓度的影响并使P型阱的P型净掺杂浓度增加。本发明还公开了一种隔离型NLDMOS器件的制造方法。本发明能提高器件的击穿电压,同时保证对体区和半导体衬底之间的良好隔离效果。(The invention discloses an isolated NLDMOS device.A first deep well ion implantation area, a plurality of second deep well ion implantation areas and a P-type well are formed on a P-type semiconductor substrate; a first distance is reserved between the first deep trap ion implantation region and a second deep trap ion implantation region closest to the drain region; the first deep trap ion injection region and each second deep trap ion injection region are integrally communicated after being thermally pushed to form an N-type deep trap; a drift region is formed by the N-type deep well between the second side face of the P-type well and the drain region; a second distance is formed between the second deep well ion implantation regions, and the P-type well is surrounded by an integral structure formed by the second deep well ion implantation regions; the influence of the N-type deep well on the P-type concentration of the P-type well is reduced and the P-type net doping concentration of the P-type well is increased by setting the second distance. The invention also discloses a manufacturing method of the isolated NLDMOS device. The invention can improve the breakdown voltage of the device and simultaneously ensure good isolation effect between the body region and the semiconductor substrate.)

1. An isolated NLDMOS device, which is characterized in that:

forming an N-type doped first deep well ion implantation area, a plurality of N-type doped second deep well ion implantation areas and a P-type well on a P-type semiconductor substrate;

a source region consisting of an N + region is formed on the surface of the P-type well;

a drain region consisting of an N + region is formed on the surface of the first deep well ion implantation region;

a gate structure is formed on the surface of the P-type well, the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, and the first side surfaces of the source region and the gate structure are self-aligned;

a first distance is reserved between the first deep trap ion implantation region and the second deep trap ion implantation region closest to the drain region;

the first deep trap ion injection region and each second deep trap ion injection region are integrally communicated after being thermally pushed to form an N-type deep trap;

a drift region is formed by the N-type deep well between the second side face of the P-type well and the drain region;

a second distance is reserved between the second deep well ion implantation regions, and the P-type well is surrounded by an integral structure formed by the second deep well ion implantation regions;

the influence of the N-type deep well on the P-type concentration of the P-type well is reduced by setting the second distance, and the P-type net doping concentration of the P-type well is increased, so that the depletion capability of the N-type deep well in the drift region is enhanced, and the breakdown voltage is improved.

2. The isolated NLDMOS device of claim 1, wherein: the first deep trap ion implantation area and each second deep trap ion implantation area have the same process conditions.

3. The isolated NLDMOS device of claim 1, wherein: the number of the second deep trap ion implantation regions is more than 2.

4. The isolated NLDMOS device of claim 3, wherein: the second deep well ion implantation region closest to the first side face of the P-type well is required to coat the first side face of the P-type well;

the second deep well ion implantation region closest to the second side of the P-well needs to wrap the second side of the P-well.

5. The isolated NLDMOS device of claim 3, wherein: the N-type deep well realizes the isolation between the P-type well and the semiconductor substrate, and the size of the second distance ensures that the punch-through voltage of a parasitic PNP among the P-type well, the N-type deep well and the semiconductor substrate meets the requirement value.

6. The isolated NLDMOS device of claim 5, wherein: the first spacing also affects the punch-through voltage of the parasitic PNP, and the second spacing is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first spacing, and the larger the second spacing, the larger the breakdown voltage of the device.

7. The isolated NLDMOS device of claim 1, wherein: the semiconductor substrate includes a silicon substrate.

8. The isolated NLDMOS device of claim 1, wherein: a drift region field oxide is further arranged in the drift region, and the drain region and a second side surface of the drift region field oxide are self-aligned;

the second side of the gate structure also extends onto the drift region field oxide.

9. The isolated NLDMOS device of claim 8, wherein: a body contact region composed of a P + region is further formed on the surface of the P-type well;

and a second field oxide is arranged between the body contact region and the source region.

10. A manufacturing method of an isolated NLDMOS device is characterized by comprising the following steps:

step one, carrying out N-type deep well ion implantation to form a first deep well ion implantation area and a plurality of second deep well ion implantation areas on a P-type semiconductor substrate;

a first distance is reserved between the first deep trap ion implantation region and the second deep trap ion implantation region closest to the drain region;

a second distance is reserved between the second deep trap ion implantation regions;

step two, carrying out thermal propulsion to integrally communicate the first deep trap ion implantation area with each second deep trap ion implantation area and form an N-type deep trap;

step three, performing P-type ion implantation to form a P-type trap;

the P-type well is surrounded by an integral structure formed by the second deep well ion implantation regions;

forming a gate structure on the surface of the P-type well, wherein the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate;

fifthly, performing N + ion implantation to form a source region and a drain region, wherein the source region is formed on the surface of the P-type well, and the drain region is formed on the surface of the first deep well ion implantation region;

the source region and the first side of the gate structure are self-aligned;

a drift region is formed by the N-type deep well between the second side face of the P-type well and the drain region;

the influence of the N-type deep well on the P-type concentration of the P-type well is reduced by setting the second distance, and the P-type net doping concentration of the P-type well is increased, so that the depletion capability of the N-type deep well in the drift region is enhanced, and the breakdown voltage is improved.

11. The method of fabricating an isolated NLDMOS device of claim 10 wherein: the number of the second deep trap ion implantation regions is more than 2.

12. The method of fabricating an isolated NLDMOS device of claim 11 wherein: the second deep well ion implantation region closest to the first side face of the P-type well is required to coat the first side face of the P-type well;

the second deep well ion implantation region closest to the second side of the P-well needs to wrap the second side of the P-well.

13. The method of fabricating an isolated NLDMOS device of claim 11 wherein: the N-type deep well realizes the isolation between the P-type well and the semiconductor substrate, and the size of the second distance ensures that the punch-through voltage of a parasitic PNP among the P-type well, the N-type deep well and the semiconductor substrate meets the requirement value.

14. The method of fabricating an isolated NLDMOS device of claim 13 wherein: the first spacing also affects the punch-through voltage of the parasitic PNP, and the second spacing is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first spacing, and the larger the second spacing, the larger the breakdown voltage of the device.

15. The method of fabricating an isolated NLDMOS device of claim 10 wherein: the semiconductor substrate includes a silicon substrate.

16. The method of fabricating an isolated NLDMOS device of claim 10 wherein: after the second step is finished, a step of forming field oxygen is also included, wherein the field oxygen comprises drift region field oxygen and second field oxygen;

the drift region field oxide is arranged in the drift region, the drain region and the second side surface of the drift region field oxide are self-aligned, and the second side surface of the gate structure also extends to the drift region field oxide;

and fifthly, after the step five is finished, P + ion implantation is carried out to form a body contact region, the body contact region is formed on the surface of the P-type well, and the second field oxygen is arranged between the body contact region and the source region at intervals.

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an isolated NLDMOS device; the invention also relates to a manufacturing method of the isolated NLDMOS device.

Background

In the conventional non-isolated NLDMOS, there is no isolation structure between a body region (body) composed of a P-type well and a P-type semiconductor substrate, so that the body region and a source region composed of an N + region formed in the body region can be connected only to the same potential as that of the semiconductor substrate, i.e., 0V potential. NLDMOS stands for N-type LDMOS.

An N-type deep well is adopted for isolation between the body region of the isolation type NLDMOS and the P-type semiconductor substrate, so that the body region and the source region can be connected with different voltages from the semiconductor substrate, the body region and the source region can float between 0V potential and power supply voltage, and the isolation type NLDMOS can work on a high-voltage side.

Fig. 1 is a schematic structural diagram of a conventional isolated PLDMOS device; in the existing isolated NLDMOS device, a first N-doped deep well ion implantation region 202a, a second N-doped deep well ion implantation region 202b and a P-type well 204 are formed on a P-type semiconductor substrate 201.

A source region 207a of N + region is formed on the surface of the P-well 204.

A drain region 207b composed of an N + region is formed on the surface of the first deep well ion implantation region 202 a.

A gate structure is formed on the surface of the P-type well 204, the gate structure is formed by overlapping a gate dielectric layer 205 and a polysilicon gate 206, and the source region 207a is self-aligned to the first side surface of the gate structure.

The first deep well ion implantation region 202a and the second deep well ion implantation region 202b have a space therebetween.

The first deep well ion implantation region 202a and the second deep well ion implantation region 202b are integrally connected after being thermally advanced, and form an N-type deep well 202.

A drift region is formed by the N-type deep well 202 from the second side of the P-well 204 to the drain region 207 b.

The second deep well ion implantation region 202b surrounds the P-well 204.

The semiconductor substrate 201 is typically a silicon substrate.

A drift region field oxide 203 is further disposed in the drift region, and the drain region 207b is self-aligned with a second side of the drift region field oxide 203.

The second side of the gate structure also extends onto the drift region field oxide 203.

A body contact region 208 composed of a P + region is also formed on the surface of the P-well 204.

The body contact region 208 and the source region 207a are spaced apart by a second field oxide 203 a.

The body contact regions 208 and the tops of the source regions 207a are connected to the source electrode patterned by the front metal layer 120 through the corresponding contact holes 209.

The top of the drain region 207b is connected to the drain electrode patterned by the front metal layer 120 through the corresponding contact hole 209.

The top of the polysilicon gate 206 is connected to a gate (not shown) patterned by the front metal layer 120 through a corresponding contact hole 209.

The breakdown voltage of the device shown in fig. 1 is determined by the depletion region of the PN junction formed between the P-type well 204 and the drift region, and the stronger the depletion capability of the P-type well 204 to the drift region, the greater the breakdown voltage.

The P-well 204 is surrounded by the N-type deep well 202 to achieve isolation between the P-well 204 and the semiconductor substrate 201. In the conventional structure shown in fig. 1, the second deep well ion implantation region 202b directly surrounds the P-type well 204, which reduces the P-type net doping concentration of the P-type well 204, that is, the concentration of the drift region relative to the P-type well 204 is relatively high, so that the depletion capability of the drift region is reduced, and finally, the breakdown voltage of the device is reduced.

Disclosure of Invention

The invention aims to provide an isolated NLDMOS device which can improve the breakdown voltage of the device and ensure good isolation effect between a body region and a semiconductor substrate. Therefore, the invention also provides a manufacturing method of the isolated NLDMOS device.

In order to solve the above technical problem, in the isolated NLDMOS device provided by the present invention, an N-doped first deep well ion implantation region, a plurality of N-doped second deep well ion implantation regions, and a P-type well are formed on a P-type semiconductor substrate.

And a source region consisting of an N + region is formed on the surface of the P-type well.

And the drain region consisting of the N + region is formed on the surface of the first deep well ion implantation region.

And a gate structure is formed on the surface of the P-type trap, the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, and the source region is self-aligned to the first side surface of the gate structure.

The first deep well ion implantation region and the second deep well ion implantation region closest to the drain region have a first spacing therebetween.

The first deep trap ion implantation area and each second deep trap ion implantation area are integrally communicated after being thermally pushed, and an N-type deep trap is formed.

And a drift region is formed by the N-type deep well between the second side surface of the P-type well and the drain region.

And a second distance is reserved between the second deep well ion implantation regions, and the P-type well is surrounded by an integral structure formed by the second deep well ion implantation regions.

The influence of the N-type deep well on the P-type concentration of the P-type well is reduced by setting the second distance, and the P-type net doping concentration of the P-type well is increased, so that the depletion capability of the N-type deep well in the drift region is enhanced, and the breakdown voltage is improved.

In a further improvement, the process conditions of the first deep well ion implantation region and each of the second deep well ion implantation regions are the same.

In a further improvement, the number of the second deep well ion implantation regions is more than 2.

In a further improvement, the second deep well ion implantation region closest to the first side of the P-well needs to wrap the first side of the P-well.

The second deep well ion implantation region closest to the second side of the P-well needs to wrap the second side of the P-well.

The further improvement is that the N-type deep well realizes the isolation between the P-type well and the semiconductor substrate, and the size requirement of the second distance ensures that the punch-through voltage of the parasitic PNP among the P-type well, the N-type deep well and the semiconductor substrate meets the requirement value.

In a further improvement, the first pitch also affects the punch-through voltage of the parasitic PNP, and the second pitch is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first pitch, and the larger the second pitch, the larger the breakdown voltage of the device.

In a further refinement, the semiconductor substrate comprises a silicon substrate.

In a further improvement, a drift region field oxide is further arranged in the drift region, and the drain region and the second side surface of the drift region field oxide are self-aligned.

The second side of the gate structure also extends onto the drift region field oxide.

In a further improvement, a body contact region composed of a P + region is formed on the surface of the P-type well;

and a second field oxide is arranged between the body contact region and the source region.

In order to solve the technical problem, the manufacturing method of the isolated NLDMOS device provided by the invention comprises the following steps:

step one, carrying out N-type deep well ion implantation to form a first deep well ion implantation area and a plurality of second deep well ion implantation areas on the P-type semiconductor substrate.

The first deep well ion implantation region and the second deep well ion implantation region closest to the drain region have a first spacing therebetween.

And a second distance is reserved between the second deep trap ion implantation regions.

And secondly, carrying out thermal propulsion to integrally communicate the first deep trap ion implantation region with each second deep trap ion implantation region and form an N-type deep trap.

And step three, performing P-type ion implantation to form a P-type well.

The P-type well is surrounded by the whole structure formed by the second deep well ion implantation regions.

And fourthly, forming a gate structure on the surface of the P-type trap, wherein the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate.

And fifthly, performing N + ion implantation to form a source region and a drain region, wherein the source region is formed on the surface of the P-type well, and the drain region is formed on the surface of the first deep well ion implantation region.

The source region and the first side of the gate structure are self-aligned.

And a drift region is formed by the N-type deep well between the second side surface of the P-type well and the drain region.

The influence of the N-type deep well on the P-type concentration of the P-type well is reduced by setting the second distance, and the P-type net doping concentration of the P-type well is increased, so that the depletion capability of the N-type deep well in the drift region is enhanced, and the breakdown voltage is improved.

In a further improvement, the number of the second deep well ion implantation regions is more than 2.

In a further improvement, the second deep well ion implantation region closest to the first side of the P-well needs to wrap the first side of the P-well.

The second deep well ion implantation region closest to the second side of the P-well needs to wrap the second side of the P-well.

The further improvement is that the N-type deep well realizes the isolation between the P-type well and the semiconductor substrate, and the size requirement of the second distance ensures that the punch-through voltage of the parasitic PNP among the P-type well, the N-type deep well and the semiconductor substrate meets the requirement value.

In a further improvement, the first pitch also affects the punch-through voltage of the parasitic PNP, and the second pitch is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first pitch, and the larger the second pitch, the larger the breakdown voltage of the device.

In a further refinement, the semiconductor substrate comprises a silicon substrate.

In a further improvement, the second step further comprises a step of forming field oxide after the second step is completed, the field oxide comprises drift region field oxide and second field oxide,

the drift region field oxide is arranged in the drift region, the drain region and a second side surface of the drift region field oxide are self-aligned, and the second side surface of the gate structure also extends to the drift region field oxide.

And fifthly, after the step five is finished, P + ion implantation is carried out to form a body contact region, the body contact region is formed on the surface of the P-type well, and the second field oxygen is arranged between the body contact region and the source region at intervals.

The invention divides the ion injection area for forming the N-type deep well into a plurality of sections, and comprises a first deep well ion injection area and a plurality of second deep well ion injection areas, the tops of the plurality of second deep well ion injection areas can be overlapped with the P-type well, and the ion injection area is different from the deep well ion injection area which is overlapped with the P-type well and is a single ion injection area in the prior art.

In addition, because the first distance is also arranged between the first deep well ion implantation area and the second deep well ion implantation area, under the condition of the first distance, the isolation between the body area formed by the P-type well and the semiconductor substrate can be simultaneously influenced by the first distance, and at the moment, the isolation effect between the body area and the semiconductor substrate can not be realized by reasonably arranging the second distance, so that the invention can also ensure that the good isolation effect is realized between the body area and the semiconductor substrate, namely the punch-through voltage of the parasitic PNP among the P-type well, the N-type deep well and the semiconductor substrate can meet the required value.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

fig. 1 is a schematic structural diagram of a conventional isolated NLDMOS device;

fig. 2 is a schematic structural diagram of an isolated PLDMOS device according to an embodiment of the present invention;

fig. 3A-3D are schematic device structures at various steps of a method for manufacturing an isolated PLDMOS device in accordance with an embodiment of the present invention;

fig. 4A is a graph of drain voltage and drain current of a conventional isolated NLDMOS device;

fig. 4B is a graph of drain voltage and drain current of an isolated NLDMOS device in accordance with an embodiment of the present invention.

Detailed Description

Fig. 2 is a schematic structural diagram of an isolated PLDMOS device according to an embodiment of the present invention; in the isolated NLDMOS device according to the embodiment of the present invention, an N-doped first deep well ion implantation region 102a, a plurality of N-doped second deep well ion implantation regions 102b, and a P-type well 104 are formed on a P-type semiconductor substrate 101.

A source region 107a of N + region is formed on the surface of P-well 104.

A drain region 107b of N + region is formed on the surface of the first deep well ion implantation region 102 a.

A gate structure is formed on the surface of the P-type well 104, the gate structure is formed by overlapping a gate dielectric layer 105 and a polysilicon gate 106, and the source region 107a is self-aligned with the first side surface of the gate structure.

The first deep well ion implantation region 102a and the second deep well ion implantation region 102b closest to the drain region 107b have a first spacing therebetween.

The first deep well ion implantation region 102a and each of the second deep well ion implantation regions 102b are integrally connected after being thermally advanced, and form an N-type deep well 102.

A drift region is formed by the N-type deep well 102 from the second side of the P-well 104 to the drain region 107 b.

The second deep well ion implantation regions 102b have a second distance therebetween, and the P-well 104 is surrounded by the whole structure formed by the second deep well ion implantation regions 102 b.

The influence of the N-type deep well 102 on the P-type concentration of the P-type well 104 is reduced and the P-type net doping concentration of the P-type well 104 is increased by setting the second distance, so that the depletion capability of the N-type deep well 102 on the drift region is enhanced, and the breakdown voltage is improved.

In the embodiment of the present invention, the first deep well ion implantation region 102a and each second deep well ion implantation region 102b have the same process conditions, so that the first deep well ion implantation region 102a and each second deep well ion implantation region 102b can be formed by using the same ion implantation, and the process cost can be saved.

The number of the second deep well ion implantation regions 102b is 2. In other embodiments can also be: the number of the second deep well ion implantation regions 102b is 3 or more.

The second deep well ion implantation region 102b closest to the first side of the P-well 104 needs to wrap the first side of the P-well 104.

The second deep well ion implantation region 102b closest to the second side of the P-well 104 needs to wrap the second side of the P-well 104.

The N-type deep well 102 realizes isolation between the P-type well 104 and the semiconductor substrate 101, and the size of the second distance is required to ensure that punch-through voltage of a parasitic PNP between the P-type well 104, the N-type deep well 102 and the semiconductor substrate 101 meets a required value.

The first spacing also affects the punch-through voltage of the parasitic PNP, and the second spacing is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first spacing, and the larger the second spacing, the larger the breakdown voltage of the device.

The semiconductor substrate 101 includes a silicon substrate.

A drift region field oxide 103 is further disposed in the drift region, and the drain region 107b is self-aligned with a second side of the drift region field oxide 103.

The second side of the gate structure also extends onto the drift region field oxide 103.

A body contact region 108 composed of a P + region is also formed on the surface of the P-well 104.

A second field oxide 103a is spaced between the body contact region 108 and the source region 107 a.

The body contact regions 108 and the tops of the source regions 107a are connected to source electrodes patterned by a front metal layer 110 through corresponding contact holes 109.

The top of the drain region 107b is connected to a drain electrode patterned by the front metal layer 110 through a corresponding contact hole 109.

The top of the polysilicon gate 106 is connected to a gate (not shown) patterned by a front metal layer 110 through a corresponding contact hole 109.

In the embodiment of the present invention, the ion implantation region forming the N-type deep well 102 is divided into a plurality of segments, and includes a first deep well ion implantation region 102a and a plurality of second deep well ion implantation regions 102b, the tops of the plurality of second deep well ion implantation regions 102b overlap with the P-type well 104, and the deep well ion implantation region overlapping with the P-type well 104 in the prior art is a single ion implantation region, which is different from the deep well ion implantation region overlapping with the P-type well 104 in the prior art.

In addition, because the first distance is also provided between the first deep well ion implantation region 102a and the second deep well ion implantation region 102b, under the condition of the first distance, the isolation between the body region formed by the P-type well 104 and the semiconductor substrate 101 can be simultaneously influenced by the first distance, and at this time, the isolation effect between the body region and the semiconductor substrate 101 cannot be achieved by reasonably setting the second distance, so that the embodiment of the invention can also ensure that the good isolation effect is provided between the body region and the semiconductor substrate 101, that is, the punch-through voltage of the parasitic PNP between the P-type well 104, the N-type deep well 102 and the semiconductor substrate 101 can meet the required value.

As shown in fig. 4A, it is a drain voltage and drain current curve 301 of the conventional isolated NLDMOS device shown in fig. 1, where the abscissa is the drain voltage and the ordinate is the logarithm of the drain current, i.e., Id; fig. 4B shows a drain voltage and drain current curve 302 of an isolated NLDMOS device according to an embodiment of the present invention. Comparing the curves 302 and 301, it can be seen that the embodiment of the invention can improve the breakdown voltage of the device by more than 5V.

Fig. 3A to 3D are schematic views of device structures in the steps of the method for manufacturing an isolated PLDMOS device according to the embodiment of the present invention; the manufacturing method of the isolated NLDMOS device comprises the following steps:

step one, as shown in fig. 3A, ion implantation is performed on the N-type deep well 102 to form a first deep well ion implantation region 102a and a plurality of second deep well ion implantation regions 102b on the P-type semiconductor substrate 101.

The first deep well ion implantation region 102a and the second deep well ion implantation region 102b closest to the drain region 107b have a first spacing therebetween.

The second deep well ion implantation regions 102b have a second distance therebetween.

In the method of the embodiment of the present invention, the number of the second deep well ion implantation regions 102b is 2. In other embodiments the method can also be: the number of the second deep well ion implantation regions 102b is 3 or more.

The semiconductor substrate 101 includes a silicon substrate.

Step two, as shown in fig. 3A, performing thermal drive to connect the first deep well ion implantation region 102a and each second deep well ion implantation region 102b integrally and form an N-type deep well 102.

In the method of the embodiment of the invention, after the second step is completed, the method further comprises a step of forming field oxide, wherein the field oxide comprises a drift region field oxide 103 and a second field oxide 103a,

the drift region field oxide 103 is disposed in the drift region.

Step three, as shown in fig. 3C, P-type ion implantation is performed to form a P-well 104. The forming area of the P-type well 104 is defined by a photolithography process, and P-type ion implantation of the P-type well 104 is performed after the photolithography definition.

The second deep well ion implantation regions 102b form an integral structure surrounding the P-well 104.

In the method of the embodiment of the present invention, the second deep well ion implantation region 102b closest to the first side of the P-type well 104 needs to cover the first side of the P-type well 104.

The second deep well ion implantation region 102b closest to the second side of the P-well 104 needs to wrap the second side of the P-well 104.

And fourthly, as shown in fig. 3D, forming a gate structure on the surface of the P-type well 104, wherein the gate structure is formed by overlapping a gate dielectric layer 105 and a polysilicon gate 106.

The gate dielectric layer 105 is usually an oxide layer. After the growth of the gate dielectric layer 105 is completed, depositing polysilicon; and then, carrying out photoetching definition and etching to form the gate structure.

The second side of the gate structure also extends onto the drift region field oxide 103.

Step five, as shown in fig. 2, N + ion implantation is performed to form a source region 107a and a drain region 107b, the source region 107a is formed on the surface of the P-type well 104, and the drain region 107b is formed on the surface of the first deep well ion implantation region 102 a.

The source region 107a is self-aligned to the first side of the gate structure.

The drain region 107b and the second side of the drift region field oxide 103 are self-aligned.

A drift region is formed by the N-type deep well 102 from the second side of the P-well 104 to the drain region 107 b.

The influence of the N-type deep well 102 on the P-type concentration of the P-type well 104 is reduced and the P-type net doping concentration of the P-type well 104 is increased by setting the second distance, so that the depletion capability of the N-type deep well 102 on the drift region is enhanced, and the breakdown voltage is improved.

In the method according to the embodiment of the present invention, the N-type deep well 102 implements isolation between the P-type well 104 and the semiconductor substrate 101, and the size of the second distance is required to ensure that punch-through voltage of a parasitic PNP between the P-type well 104, the N-type deep well 102, and the semiconductor substrate 101 meets a required value.

The first spacing also affects the punch-through voltage of the parasitic PNP, and the second spacing is set under the condition that the punch-through voltage of the parasitic PNP is ensured to be determined by the first spacing, and the larger the second spacing, the larger the breakdown voltage of the device.

And after the fifth step, performing P + ion implantation to form a body contact region 108, wherein the body contact region 108 is formed on the surface of the P-well 104, and the second field oxide 103a is spaced between the body contact region 108 and the source region 107 a.

Then also comprises the following steps:

forming an interlayer film, a contact hole 109 and a front metal layer 110, and patterning the front metal layer 110 to form a source electrode, a drain electrode and a grid electrode.

The body contact regions 108 and the tops of the source regions 107a are connected to source electrodes patterned by a front metal layer 110 through corresponding contact holes 109.

The top of the drain region 107b is connected to a drain electrode patterned by the front metal layer 110 through a corresponding contact hole 109.

The top of the polysilicon gate 106 is connected to a gate (not shown) patterned by a front metal layer 110 through a corresponding contact hole 109.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.