阅读说明：本技术 读出电路及图像传感器 (Readout circuit and image sensor ) 是由 徐新楠 于 2021-08-27 设计创作，主要内容包括：本公开实施例提供了一种读出电路及图像传感器,所述读出电路包括：像素阵列,包括多行和多列的像素单元；列计数器,适于获取所述像素阵列中特定列上多行像素单元的对应像素信号；所述列计数器在获取特定列上多行像素单元的对应像素信号的行合并像素信号之后进行复位。所述读出电路在对获取到的图像信息进行像素信号合并读出的过程中,无需提前缓存至少一行像素信号,可以有效减少图像传感器中用来进行像素信号存储的芯片面积。(The disclosed embodiment provides a readout circuit and an image sensor, wherein the readout circuit comprises: a pixel array including a plurality of rows and a plurality of columns of pixel units; a column counter adapted to acquire corresponding pixel signals of a plurality of rows of pixel units on a particular column of the pixel array; the column counter is reset after acquiring row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel units on a specific column. The read-out circuit does not need to cache at least one row of pixel signals in advance in the process of carrying out pixel signal combination read-out on the acquired image information, and the area of a chip used for storing the pixel signals in the image sensor can be effectively reduced.)

1. A sensing circuit, comprising:

a pixel array including a plurality of rows and a plurality of columns of pixel units;

a column counter adapted to acquire corresponding pixel signals of a plurality of rows of pixel units on a particular column of the pixel array;

the column counter is reset after acquiring row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel units on a specific column.

2. The readout circuit of claim 1, wherein the plurality of rows of pixel cells on the particular column are two adjacent rows of pixel cells on the particular column.

3. The readout circuit of claim 1, wherein the plurality of rows of pixel cells on the particular column are two rows of pixel cells spaced apart on the particular column.

4. A sensing circuit of claim 1, further comprising: and the column latch is suitable for latching row merging pixel signals obtained by the column counters on corresponding columns, and latches after the column counters acquire the row merging pixel signals and before the column counters are reset.

5. The sensing circuit of claim 4, further comprising: and the time sequence control module is suitable for generating a reset signal to control the reset of the column counter and is also suitable for generating a latch signal to control the opening of the column latch.

6. The sensing circuit of claim 4, further comprising: an address decoder adapted to read out row-merged pixel signals in the column latches.

7. An image sensor, comprising:

a pixel array including a plurality of rows and a plurality of columns of pixel units;

a column counter adapted to obtain row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel cells on a particular column of the pixel array;

an address decoder adapted to read out the row-merged pixel signals; and

and the digital circuit is suitable for receiving the row combination pixel signals read by the address decoder and combining a plurality of columns of the row combination pixel signals through the digital circuit.

8. The image sensor of claim 7, wherein an order in which said address decoder reads out said row-merged pixel signals is related to a column address provided by said digital circuitry.

9. The image sensor of claim 7, wherein the plurality of rows of pixel cells on the particular column are two adjacent rows of pixel cells on the particular column; and the multiple columns of the row combination pixel signals are pixel signals of two adjacent columns in the row combination pixel signals.

10. The image sensor of claim 7, wherein the plurality of rows of pixel cells on the particular column are two rows of pixel cells spaced apart on the particular column; the multiple columns of the row-merged pixel signals are two columns of pixel signals spaced apart in the row-merged pixel signals.

11. The image sensor of claim 7, wherein the column counters are reset after acquiring row-merged pixel signals for a plurality of rows of pixel cells on the particular column.

12. The image sensor of claim 11, further comprising: and the column latch is suitable for latching row merging pixel signals obtained by the column counters on corresponding columns, and latches after the column counters acquire the row merging pixel signals and before the column counters are reset.

13. The image sensor of claim 12, further comprising: and the time sequence control module is suitable for generating a reset signal to control the reset of the column counter and is also suitable for generating a latch signal to control the opening of the column latch.

14. An image sensor, comprising:

the sensing circuit of any of claims 1-6, the sensing circuit comprising an address decoder; and

and the digital circuit is suitable for receiving the row combination pixel signals read by the address decoder and carrying out column combination on multiple columns of the row combination pixel signals through the digital circuit.

15. The image sensor of claim 14, wherein the order in which said address decoder reads out said row-merged pixel signals is related to the column addresses provided by the received digital circuitry.

16. The image sensor of claim 14, wherein the plurality of columns of row combined pixel signals are two adjacent columns of pixel signals in the row combined pixel signals.

17. The image sensor of claim 14, wherein the plurality of columns of row combined pixel signals are two columns of pixel signals spaced apart in the row combined pixel signals.

18. An image sensor, comprising:

a mode selection module adapted to select a readout mode, the readout mode comprising a binning mode in which the image sensor comprises a readout circuit according to any of claims 1 to 6, the readout circuit comprising an address decoder.

19. The image sensor of claim 18, further comprising: and the digital circuit is suitable for receiving the row combination pixel signals read out by the address decoder in the combination mode and carrying out column combination on multiple columns of the row combination pixel signals through the digital circuit.

20. The image sensor of claim 18, wherein an order in which said address decoder reads out said row-merged pixel signals is related to a column address provided by said digital circuitry.

21. The image sensor of claim 19, wherein the plurality of columns of row combined pixel signals are two adjacent columns of pixel signals in the row combined pixel signals.

22. The image sensor of claim 19, wherein the plurality of columns of row combined pixel signals are two columns of pixel signals spaced apart in the row combined pixel signals.

Technical Field

The disclosure relates to the technical field of integrated circuits, in particular to a reading circuit and an image sensor.

Background

A Complementary Metal Oxide Semiconductor (CMOS) image sensor has the advantages of simple process, easy integration with other devices, small volume, light weight, low power consumption, low cost, and the like, and therefore, with the development of image sensing technology, the CMOS image sensor is widely applied to various electronic products.

In some specific cases, the CMOS image sensor needs to read out pixel signals in combination; however, the current CMOS image sensor needs to buffer at least one row of pixel signals when performing pixel signal combination reading, which increases the chip area. Therefore, a new readout circuit and image sensor are needed.

Disclosure of Invention

In order to solve the problems in the prior art, embodiments of the present disclosure provide a readout circuit and an image sensor, which can reduce a chip area.

To solve the above technical problem, an embodiment of the present disclosure provides a readout circuit, including: a pixel array including a plurality of rows and a plurality of columns of pixel units; a column counter adapted to acquire corresponding pixel signals of a plurality of rows of pixel units on a particular column of the pixel array; the column counter is reset after acquiring row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel units on a specific column.

In some embodiments, the plurality of rows of pixel cells on the particular column is two adjacent rows of pixel cells on the particular column.

In some embodiments, the plurality of rows of pixel cells on the particular column is two rows of pixel cells spaced apart on the particular column.

In some embodiments, the readout circuit further comprises: and the column latch is suitable for latching row merging pixel signals obtained by the column counters on corresponding columns, and latches after the column counters acquire the row merging pixel signals and before the column counters are reset.

In some embodiments, the readout circuit further comprises: and the time sequence control module is suitable for generating a reset signal to control the reset of the column counter and is also suitable for generating a latch signal to control the opening of the column latch.

In some embodiments, the readout circuit further comprises: an address decoder adapted to read out row-merged pixel signals in the column latches.

The disclosed embodiments also provide an image sensor, including: a pixel array including a plurality of rows and a plurality of columns of pixel units; a column counter adapted to obtain row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel cells on a particular column of the pixel array; an address decoder adapted to read out the row-merged pixel signals; and the digital circuit is suitable for receiving the row combination pixel signals read out by the address decoder and combining a plurality of columns of the row combination pixel signals through the digital circuit.

In some embodiments, the order in which the row-merged pixel signals are read out by the address decoder is related to the column addresses provided by the digital circuitry.

In some embodiments, the plurality of rows of pixel cells on the particular column are two adjacent rows of pixel cells on the particular column; and the multiple columns of the row combination pixel signals are pixel signals of two adjacent columns in the row combination pixel signals.

In some embodiments, the plurality of rows of pixel cells on the particular column is two rows of pixel cells spaced apart on the particular column; the multiple columns of the row-merged pixel signals are two columns of pixel signals spaced apart in the row-merged pixel signals.

In some embodiments, the column counter is reset after acquiring row merged pixel signals for a plurality of rows of pixel cells on the particular column.

In some embodiments, the image sensor further comprises: and the column latch is suitable for latching row merging pixel signals obtained by the column counters on corresponding columns, and latches after the column counters acquire the row merging pixel signals and before the column counters are reset.

In some embodiments, the image sensor further comprises: and the time sequence control module is suitable for generating a reset signal to control the reset of the column counter and is also suitable for generating a latch signal to control the opening of the column latch.

The disclosed embodiments also provide an image sensor, including: the sensing circuit of any preceding embodiment, the sensing circuit comprising an address decoder; and the digital circuit is suitable for receiving the row combination pixel signals read out by the address decoder and carrying out column combination on multiple columns of the row combination pixel signals through the digital circuit.

In some embodiments, the order in which the row-merged pixel signals are read out by the address decoder is related to the column addresses provided by the digital circuitry.

In some embodiments, the plurality of columns of the row-merged pixel signals are two adjacent columns of pixel signals in the row-merged pixel signals.

In some embodiments, the plurality of columns of row combined pixel signals are two columns of pixel signals spaced apart in the row combined pixel signals.

The disclosed embodiments also provide an image sensor, including: a mode selection module adapted to select a readout mode, the readout mode including a binning mode in which the image sensor comprises the readout circuit of any of the above embodiments, the readout circuit comprising an address decoder.

In some embodiments, the image sensor further comprises: and the digital circuit is suitable for receiving the row combination pixel signals read out by the address decoder in the combination mode and carrying out column combination on multiple columns of the row combination pixel signals through the digital circuit.

In some embodiments, the order in which the row-merged pixel signals are read out by the address decoder is related to the column addresses provided by the digital circuitry.

In some embodiments, the plurality of columns of the row-merged pixel signals are two adjacent columns of pixel signals in the row-merged pixel signals.

In some embodiments, the plurality of columns of row combined pixel signals are two columns of pixel signals spaced apart in the row combined pixel signals.

Compared with the prior art, the technical scheme of the embodiment of the disclosure has the following beneficial effects:

according to the readout circuit provided by the embodiment of the disclosure, the column counter resets after acquiring row combination pixel signals of pixel signals corresponding to multiple rows of pixel units on a specific column, the pixel signals of different rows of pixel units to be combined are directly combined in the column counter, and the pixel signals of the pixel units on the previous row are not required to be stored in the digital circuit, so that the data amount stored in the digital circuit can be greatly reduced, and further the chip area is reduced.

According to the image sensor provided by the embodiment of the disclosure, each column of the pixel array in the readout circuit is provided with the column counter, so that when pixel signals need to be merged and read, the pixel signals of the pixel units in different rows can be merged in the readout circuit of the image sensor; and then, different columns in the row combination pixel signals can be subjected to row-column combination in a digital circuit of the image sensor, so that the pixel signals of a plurality of rows and columns of pixel units can be combined, and the area of a chip for storing the pixel signals in the digital circuit can be effectively reduced.

According to the image sensor provided by the embodiment of the disclosure, selection is performed among different modes, direct reading of pixel signals or combination output of the pixel signals can be realized, and the requirements of different application scenes can be met.

Drawings

FIG. 1 is a block diagram of a readout circuit according to an embodiment of the disclosure;

FIG. 2 is a timing diagram of row-merging readout of a monochrome pixel array according to an embodiment of the present disclosure;

FIG. 3 is a block diagram of a readout circuit and a digital circuit in an image sensor according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a 4-row 6-column black-and-white pixel array according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a row-by-column readout sequence of row-merged pixel signals of a 4-row 6-column black-and-white pixel array according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a merged readout sequence of a 4-row 6-column black-and-white pixel array 2x2 according to an embodiment of the disclosure;

FIG. 7 is a timing diagram illustrating row merging readout of a color pixel array according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a 4 row 8 column Bayer pixel array according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of a row-by-row and column-by-column pixel signal interval column readout sequence for a 4-row and 8-column Bayer pixel array according to an embodiment of the disclosure;

fig. 10 is a schematic diagram of a 4 row 8 column Bayer pixel array 2x2 merged readout sequence according to an embodiment of the disclosure.

Detailed Description

As described in the background art, under the specific application requirement, the pixel signals need to be merged and read, but the current pixel merging and reading scheme needs to buffer the pixel signals of at least one row of pixel units in advance when merging, which increases the chip area.

The embodiment of the disclosure provides a readout circuit and an image sensor, which can realize non-cache combination of pixel signals of pixel units in different rows and columns, thereby saving the area of a chip.

In order to make the objects, technical solutions and effects of the present disclosure clearer and clearer, the present disclosure is further described in detail below with reference to the accompanying drawings and preferred embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the disclosure and do not limit the scope of the disclosure.

The disclosed embodiments provide a readout circuit, which includes: a pixel array including a plurality of rows and a plurality of columns of pixel units; a column counter adapted to acquire corresponding pixel signals of a plurality of rows of pixel units on a particular column of the pixel array; the column counter is reset after acquiring row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel units on a specific column.

Fig. 1 is a specific embodiment, and details of a readout circuit provided in the embodiment of the present disclosure are described below.

With particular reference to fig. 1, the readout circuit comprises: the pixel array 101, the column comparator 102, the column counter 103, the column latch 104, and the address decoder 105, wherein the column comparator 102, the column counter 103, and the column latch 104 are all multiple, for example, the number of the column comparators 102, the column counters 103, and the column latch 104 is the same as the number of columns of the pixel array 101. The pixel array 101 includes a plurality of rows and a plurality of columns of pixel units; the column comparator 102 is adapted to compare an analog pixel signal of a pixel unit on a specific column selected by a row on the specific column in the pixel array 101 with a reference signal, and convert the analog pixel signal into a digital pixel signal to be output to the column counter 103, in the following detailed description, the "pixel signal" is used to represent the digital pixel signal output by the column comparator 102 to the pixel unit of the column counter 103; the column counter 103 is adapted to obtain corresponding pixel signals of multiple rows of pixel units on a specific column in the pixel array 101, and combine the pixel signals of multiple rows of pixel units on the specific column; the column latch 104 is adapted to latch the row-merged pixel signal obtained by the column counter 103 on the corresponding column upon receiving a latch signal; the address decoder 105 is adapted to serially read out the row-merged pixel signal in each of the column latches 104 to a subsequent circuit for processing between two times of the latch signals.

In some embodiments, the column comparator has a positive input adapted to receive a reference signal and a negative input adapted to receive an analog pixel signal of a particular selected row of the pixel array.

In the embodiment shown in fig. 1, the reference signal is a ramp signal having a fixed slope and generated by a ramp signal generator 107.

In the embodiment shown in fig. 1, the readout circuit further comprises a timing control module 108: the timing control module 108 is adapted to generate a reset signal to control the resetting of the column counter 103, and the timing control module 108 is further adapted to generate the latch signal to control the opening of the column latch 104.

As described above, the column counter acquires row-merged pixel signals of corresponding pixel signals of a plurality of rows of pixel units on a specific column; then, as shown in fig. 2, when the row-merged pixel signal of a specific row exists in each of the column counters, the timing control module generates the latch signal to control each of the column latches to store the row-merged pixel signal in the corresponding column counter; and then, the time sequence control module generates the reset signal to reset each column counter to prepare for next row combination.

In the embodiment shown in fig. 1, the timing control module 108 may also control the row selection module 109 to gate a particular row. In some other embodiments, the timing control module may further control the ramp signal generator to generate a reference signal.

In some embodiments, the different rows of pixel units for merging may be two adjacent rows of pixel units, that is, the rows of pixel units on the specific column are two adjacent rows of pixel units on the specific column. In some other embodiments, the different rows of pixel cells that effect the merging may also be two spaced rows of pixel cells.

In some embodiments, when the row-merged pixel signal stored in the column latch is read out by the address decoder, row merging and storage of pixel signals of other rows may be performed simultaneously in each of the column comparators, the column counters, and the column latches of the readout circuit; in other words, during the readout of the row-merged pixel signals of the first two rows of pixel units, the row merging and storage of the pixel signals of the following two rows of pixel units are also performed at the same time. The specific processes of performing the analog-to-digital conversion and storing are described in detail above, and are not described herein again.

The embodiment of the present disclosure further provides an image sensor, and the image sensor provided by the embodiment of the present disclosure is described in detail below with reference to fig. 3 as a specific embodiment.

With particular reference to fig. 3, the image sensor comprises: the pixel array 101, the column comparator 102, the column counter 103, the column latch 104, the address decoder 105, and the digital circuit 106, wherein the digital circuit 106 is configured to receive the row-merged pixel signal read by the address decoder 105, and perform column merging on multiple columns of the row-merged pixel signal through the digital circuit 106. The readout circuit formed by the pixel array 101, the column comparator 102, the column counter 103, the column latch 104, and the address decoder 105 is described above in detail, and is not repeated here.

After the row-merged pixel signal is stored in the column latch 104 of the corresponding column, the address decoder 105 serially reads out the row-merged pixel signal in each column latch 104 to the digital circuit 106 according to the acquired column address. The digital circuit 106 combines the two row-merged pixel signals every time it reads two of the row-merged pixel signals; specifically, after row combination is completed, each latch 104 stores a row-combined pixel signal of a corresponding column, the digital circuit 106 reads out one column of the row-combined pixel signals from each latch 104 through the address decoder 105 and stores the read row-combined pixel signals in the digital circuit 106, and after the digital circuit 106 reads out another column of the row-combined pixel signals again, the two row-combined pixel signals are combined in a column manner inside the digital circuit, for example, a two-column row-combined pixel signal can be combined through an adder, so that 2 × 2 combination of pixel signals is realized.

In some embodiments, the different column and row combined pixel signals implementing column combination may be two adjacent columns of pixel signals, i.e. the multiple columns of the row combined pixel signals are two adjacent columns of pixel signals in the row combined pixel signals. In some other embodiments, the different column row combined pixel signals that implement column combining may also be two columns of pixel signals that are spaced apart.

In some embodiments, the order in which the row-merged pixel signals are read out by the address decoder is related to the column addresses provided by the digital circuitry.

As an example, a readout sequence for performing 2 × 2 merged readout of pixel signals for a certain pixel array is schematically shown in fig. 4-6. Fig. 4 shows a schematic diagram of a black and white pixel array of 4 rows and 6 columns. When the row combination of the pixel signals is carried out, the time sequence control module sends a row selection signal to control the row selection module to gate the first row. In other embodiments, other rows of pixel cells may be gated.

Then, converting the analog pixel signals of the first row of pixel units into digital pixel signals of the selected row through each column comparator and each column counter, and storing the digital pixel signals in the column counters of the corresponding columns; hereinafter, the digital pixel signal is represented by "pixel signal". Then, the timing control module controls the row selection module to gate a second row, and pixel signals of pixel units of the second row are stored in the column counters of the corresponding columns by the same method; in other words, the second row pixel signals are counted in each column counter based on the pixel signals of the first row pixel units, so that row-combined pixel signals are stored in each column counter; after the pixel signals of two rows of pixel units are combined, the time sequence control module sends latch signals to enable each latch to store the row combined pixel signals of the corresponding column; and then, the time sequence control module generates a reset signal to reset each row counter, and preparation is made for each row counter to store pixel signals of a row corresponding to the next row of pixel units.

Then, the address decoder reads out the row-merged pixel signals to a digital circuit column by column according to the received column addresses, and the sequence of reading out the row-merged pixel signals of the black-and-white pixel array with 4 rows and 6 columns, which are subjected to row merging, column by column is shown in fig. 5; in the process of reading out column by column, column combination can be carried out on the row combination pixel signals; when column combination is performed, column combination of the two row-combined pixel signals is performed inside the digital circuit every time the digital circuit reads out two row-combined pixel signals, and the readout order of the pixel signals after column combination is completed is as shown in fig. 6. In the above-described disclosed embodiment, the row-merged pixel signals subjected to column merging are two adjacent columns of row-merged pixel signals, thereby implementing 2 × 2 merging of the pixel signals of the black-and-white pixel array.

In the above embodiment, the combination by the readout circuit is the combination between the pixel signals of two rows and two columns of pixel units, thereby realizing the 2 × 2 combination of the pixel signals. In some other embodiments, the combination of the pixel signals of the pixel units of multiple rows and multiple columns can also be performed, so as to realize the combination of the pixel signals of the pixel units of n rows and n columns. The way of combining the rows of pixel signals of a plurality of rows of pixel units is the same as the way of combining the rows of pixel signals of two rows of pixel units, and the way of combining the columns of row-combined pixel signals is the same as the way of combining the columns of two columns of row-combined pixel units, which is not described herein again.

In some embodiments, when the image to be subjected to pixel combination is a color image, since the color filter array in the image sensor takes two rows as a cycle more, the timing control module may control the row selection module to gate two rows of pixel units at intervals to perform combination of corresponding column pixel signals when performing color combination.

In some embodiments, when performing 2 × 2 merging of pixel signals for color images, the merging readout timing of the color pixel array is as shown in fig. 7, and after two rows of same-channel pixel signals are stored in each column counter, the timing control module generates latch signals to turn on the latches so as to store the row-merged pixel signals in the column latches of the corresponding column; and then, the time sequence control module generates a reset signal to control each column counter to reset so as to prepare for storing the pixel signals of the pixel units in the next row. The merging and readout timing of the color pixel array is similar to that of the black and white pixel array, and is not repeated herein.

In one embodiment, the color filters are in a Bayer format, and a readout sequence of 2 × 2 merged readout of pixel signals is performed on a 4-row 8-column Bayer array, as shown in fig. 8-10. Fig. 8 shows a Bayer array having 4 rows and 8 columns, and the arrangement of color filters is determined by two rows in one period. When the pixel signals are combined, the timing sequence control module controls the row selection module to gate the first row of pixel units, and the pixel signals of the first row of pixel units are stored in the column counters of each corresponding column after passing through each column comparator and each column counter, similar to a black-and-white pixel array; then, gating a third row of pixel units with the same filter arrangement rule as the first row of pixel units, and storing pixel signals of the third row of pixel units in each column counter in the same method, wherein when the third row of pixel signals are stored in each column counter, the pixel signals of the first row of pixel units are also stored in each column counter, namely the third row of pixel signals are counted in the column counters of the corresponding columns based on the first row of pixel signals, so that row combination pixel signals of the first row and the third row of pixel units are stored in each column counter; then, the time sequence control module sends a latch signal to each column latch, so that each column latch stores the row merging pixel signal of the corresponding column; and when the row merging pixel signals of the corresponding columns are stored in the column latches, the timing control module generates reset signals to reset the column counters.

When pixel signals of a color image are combined, the readout circuit provided by the embodiment of the disclosure can gate two rows of pixel units at intervals to perform row combination of pixel signals of the same channel in each column counter, and does not need to buffer the pixel signals of a plurality of rows of pixel units, so that the area for storing the pixel signals in a digital circuit can be reduced, and the chip area is reduced.

For the row-merged pixel signal stored in each of the column latches, the address decoder gates the column latch corresponding to the column address according to the received column address; reading all row-merged pixel signals in each column latch into a digital circuit in the order of the gated column latches; in the digital circuit, column combination of two column row-combined pixel signals may be performed.

In color applications, the readout sequence of the row-merged pixel unit is shown in fig. 9, after an address decoder reads out a first column of row-merged pixel signals, the first column of pixel signals are stored in a digital circuit, then the address decoder reads out a third column of row-merged pixel signals, and then the first column and the third column of row-merged pixel signals are directly subjected to column merging in the digital circuit, so that 2x2 merging of pixel signals of the same channel of a color pixel array can be realized, and a schematic diagram of the 2x2 merging readout sequence of a Bayer array with 4 rows and 8 columns is shown in fig. 10.

When reading out the row-merged pixel signal which completes the row merging of the pixel signals of the same channel, the address decoder may control the gate interval columns so that the row-merged pixel signal read out by the address decoder second and the row-merged pixel signal read out first are the same channel signals, and 2 × 2 pixel merging of a color image may be implemented by storing one row-merged pixel signal in the digital circuit without additionally storing one row-merged pixel signal, thereby reducing a chip area for storing the pixel signals.

In some other embodiments, if the color filter array has a period of multiple rows and multiple columns, the timing control module may also control the row selection module to gate rows and columns with the same interval as the filter arrangement rule when performing color combination.

An embodiment of the present disclosure further provides an image sensor, where the image sensor includes a mode selection module adapted to select a readout mode of a readout circuit, where the readout mode includes a merge mode, and in the merge mode, the image sensor includes the readout circuit according to any of the above embodiments, and the readout circuit includes an address decoder.

In some embodiments, the image sensor further comprises: and the digital circuit is used for receiving the row combination pixel signals read by the address decoders in the combination mode and carrying out column combination on a plurality of columns of the row combination pixel signals in the digital circuit. In some embodiments, the order in which the address decoder reads out row merged pixel signals is related to the column addresses provided by the digital circuitry received. In some specific embodiments, the row-combined pixel signals subjected to column combination may be two adjacent columns of pixel signals in the row-combined pixel signals. In some other embodiments, the row-combined pixel signals that are column-combined may be two columns of pixel signals that are spaced apart in the row-combined pixel signals.

In some embodiments, the readout mode includes a merge mode and a non-merge mode. In the merging mode, when the pixel signals of a row of pixel units exist in each row of counters, the time sequence control module does not generate latch signals and reset signals; and when row merging pixel signals of two rows of pixel units exist in each column counter, the timing sequence control module generates the latch signal and the reset signal to control the latching of the column latch and the resetting of the column counter. In the non-binning mode, for example, when the pixel signals of one row of pixel units are stored in each column counter, the timing control module generates a latch signal to control each corresponding column latch to store the pixel signals of one row of pixel units, and then the timing control module generates a reset signal to reset each column counter to prepare for storing the pixel signals of the next row of pixel units.

In some embodiments, the mode selection module includes a register in the timing control module. The register marks a merging mode and a non-merging mode, and the time sequence control module enters different modes through the marks of the register. In the readout circuit described in the above embodiment, the timing control module is in the merge mode.

While the foregoing embodiments have been described in some detail and with reference to specific details of the disclosure, it is to be understood that these embodiments are merely illustrative and not restrictive, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the disclosure, which is defined by the claims appended hereto.