阅读说明：本技术 基于查找表的聚焦离子束友好型填充单元设计 (Lookup table based focused ion beam friendly filler cell design ) 是由 M·K·C·雅普 A·纳卡莫托 于 2019-08-02 设计创作，主要内容包括：本发明公开了一种集成电路,该集成电路包括多个逻辑功能电路,该多个逻辑功能电路设置在该集成电路上并且通过金属互连线互连以形成逻辑网络。多个可配置逻辑功能电路也设置在该集成电路上,每个可配置逻辑功能电路设置在该集成电路上的相应区域上并且不通过该金属互连线互连以形成该逻辑网络。(An integrated circuit includes a plurality of logic function circuits disposed thereon and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits are also disposed on the integrated circuit, each configurable logic function circuit disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.)

1. An integrated circuit, the integrated circuit comprising:

a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network;

a plurality of configurable logic function circuits, each configurable logic function circuit disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.

2. The integrated circuit of claim 1, wherein the configurable logic function circuits each comprise a multiplexer-based look-up table (LUT).

3. The integrated circuit of claim 2, wherein each multiplexer-based LUT comprises a plurality of inputs.

4. The integrated circuit of claim 3, wherein each multiplexer-based LUT comprises four inputs.

5. The integrated circuit of claim 2, wherein each multiplexer-based LUT comprises a plurality of select inputs and outputs.

6. The integrated circuit of claim 2, wherein each input of the plurality of inputs of each multiplexer-based LUT is connected to a metal line in the integrated circuit.

7. The integrated circuit of claim 6, wherein the each of the plurality of inputs of each multiplexer-based LUT is connected to a metal line in the integrated circuit through an inter-metal via.

8. The integrated circuit of claim 6, wherein the metal line is electrically connected to a voltage rail.

9. The integrated circuit of claim 6, wherein the voltage rail is a VSS voltage rail.

10. A method for performing a repair logic design error in an integrated circuit, the integrated circuit including a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network, the method comprising:

providing a plurality of configurable logic function circuits on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and having an input and an output, the inputs and the outputs not forming part of the logic network formed by the plurality of logic function circuits;

identifying the logic design error by the logic type and location on the integrated circuit of the logic function circuit in which the design error is located;

identifying the location of at least one metal interconnect conductor that must be severed to correct the logic design error;

directing a focused ion beam to the location of the at least one metal interconnect conductor and severing the at least one metal interconnect conductor;

identifying configurable logic circuitry on the integrated circuit;

configuring the identified configurable logic circuit to perform a logic function that corrects the logic design error for the logic type; and

connecting the identified configurable logic circuit into the logic network to correct the design error.

11. The method of claim 10, wherein identifying configurable logic circuits on the integrated circuit comprises identifying configurable logic circuits having locations closest to the logic function circuit where the design error is located.

12. The method of claim 10, wherein:

the identified configurable logic circuit comprises a multiplexer-based LUT having a plurality of LUT inputs; and

configuring the identified configurable logic circuit to perform a logic function that corrects the logic design error for the logic type includes selectively connecting the plurality of LUT inputs to define the performed logic function.

13. The method of claim 12, wherein selectively connecting the plurality of LUT inputs to define the performed logic function comprises:

selectively disconnecting at least one of the plurality of inputs from a first metal line electrically connected to a first voltage rail; and

reconnecting the disconnected one of the plurality of inputs to a second metal line electrically connected to a second voltage rail.

14. The method of claim 13, wherein selectively disconnecting an input of the plurality of inputs from a first metal line electrically connected to a first voltage rail comprises using a focused ion beam to break an inter-metal via connecting the input of the plurality of inputs to the first metal line.

15. The method of claim 13, wherein:

selectively disconnecting an input of the plurality of inputs from a first metal line electrically connected to a first voltage rail comprises selectively disconnecting at least one input of the plurality of inputs from a first metal line electrically connected to a VDD voltage rail; and

reconnecting the disconnected one of the plurality of inputs to a second metal line electrically connected to a second voltage rail includes reconnecting the disconnected one of the plurality of inputs to a second metal line electrically connected to a VSS voltage rail.

16. The method of claim 12, wherein:

the multiplexer-based LUT has at least one select input and one output; and

connecting the identified configurable logic circuit into the logic network to correct the design error comprises connecting the multiplexer-based LUT into the logic network in place of the severed at least one metal interconnect conductor.

Background

Focused Ion Beam (FIB) technology is increasingly being used in the semiconductor industry. One example of the use of such techniques is in circuit "editing," which allows designers to cut metal traces or add metal interconnects within an integrated circuit die. FIB circuit editing employs a finely focused gallium (Ga +) ion nanoscale resolution beam that has been used to image, etch, and deposit materials on integrated circuit dies with high precision. The FIB process allows the designer to cut and connect circuits within the field device. High energy Ga + ion beams can mill through conductors and various types of gases can be used to enhance milling accuracy or to more efficiently deposit conductive and dielectric materials. For example, materials such as tungsten, platinum, and silicon dioxide may be precisely deposited by using appropriate gas chemistries.

To perform circuit editing, the FIB tool is coupled to a CAD navigation system for locating the region of interest. The FIB circuit editing process uses the design file to navigate to the area of interest, allowing subsurface features to be located and ensuring correct editing occurs.

Typical FIB integrated circuit editing applications include debugging and optimizing devices in production, exploring and validating design changes, prototyping new devices without mask set manufacturing and manufacturing runs, scaling repairs, and preventing or at least minimizing time-to-market delays.

In complex integrated circuit designs, it is common to discover functional failures at the post-silicon stage. Logic function repair typically requires at least metal rework, and in some cases full substrate rework. Designers often view FIBs as the best effort to avoid layout mask rework and employ layout mask rework for complex faults that require logic cell insertion.

Post-silicon stage editing via FIB has limited flexibility because it is destructive in nature. Common successful FIB editing is limited to simple reconnections and logical functions are rarely successfully added to repair or change existing logical functions.

For silicon post repair, the industry currently provides a method of spare gate spray and/or gate array fill cells. These typically require changing the metal interconnect mask used to define the interconnect pattern of one or more metal layers to add new logic cells to the silicon, i.e., metal remaking.

Disclosure of Invention

According to one aspect of the invention, an integrated circuit includes a plurality of logic function circuits disposed thereon and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits are also disposed on the integrated circuit, each configurable logic function circuit disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.

According to an aspect of the invention, the configurable logic function circuits each comprise a multiplexer-based look-up table (LUT) having a plurality of inputs. The number of inputs may be four inputs.

According to an aspect of the invention, each multiplexer-based LUT comprises a plurality of select inputs and outputs.

According to an aspect of the invention, each of the plurality of inputs of each multiplexer-based LUT is connected to a voltage rail in the integrated circuit. According to an aspect of the invention, the voltage rail is a VSS voltage rail.

According to an aspect of the invention, there is provided a method for performing a repair of a logic design error in an integrated circuit comprising a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. The method comprises the following steps: providing a plurality of configurable logic function circuits on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and having an input and an output, the input and the output not forming part of the logic network formed by the plurality of logic function circuits; identifying the logic design error by the logic type and location of the logic function circuit on the integrated circuit where the design error is located; identifying the location of at least one metal interconnect conductor that must be severed to correct the logic design error; directing a focused ion beam to the location of the at least one metal interconnect conductor and severing the at least one metal interconnect conductor; identifying configurable logic circuits on the integrated circuit; configuring the identified configurable logic circuit to perform a logic function that corrects the logic design error for the logic type; and connecting the identified configurable logic circuit into the logic network to correct the design error.

Drawings

The invention will be explained in more detail below with reference to embodiments and the accompanying drawings, in which:

FIG. 1 is a block diagram showing a portion of an integrated circuit die including several logic circuit blocks interconnected to form a logic network and having unoccupied white space remaining on the integrated circuit die between some of the logic circuit blocks;

FIG. 2A is a block diagram of a logic circuit in the form of a LUT that may be included in the layout of the integrated circuit of FIG. 1 to occupy an area of empty space on the integrated circuit die;

FIG. 2B is a block diagram of the logic circuit of FIG. 2 that has been configured using FIB techniques to implement an XOR gate;

FIG. 3 is a block diagram illustrating a portion of the integrated circuit die of FIG. 1 further including the number of logic circuits of FIG. 2A included in the white space on the integrated circuit die, in accordance with an aspect of the present invention;

FIG. 4 is a block diagram illustrating a portion of the integrated circuit die of FIG. 3 in which one of the logic circuits of FIG. 2A has been configured using FIB techniques in accordance with an aspect of the present invention and connected to a logic network to correct errors in the logic network implemented in the logic circuit block; and is

Fig. 5 is a flow chart illustrating an exemplary circuit error correction method in accordance with an aspect of the present invention.

Detailed Description

Those of ordinary skill in the art will realize that the following description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily occur to those skilled in the art.

Referring first to fig. 1, a block diagram of a portion 10 of an integrated circuit formed on a semiconductor die includes several logic function circuits 12 a-12 n. The logic function circuits 12a to 12n are interconnected to form a logic network. The metal interconnects between logic function circuits 12 a-12 n are defined by one or more metal masks that are applied to the integrated circuits during fabrication processes known in the art of semiconductor wafer fabrication.

Those of ordinary skill in the art will appreciate that the number of logic function circuits 12 a-12 n may take a variety of forms, and may be, for example, combinational logic function circuits such as simple gates, inverters, look-up tables (LUTs), or may be sequential logic function circuits such as flip-flops, latches, counters or other sequential logic elements. Such skilled persons will also appreciate that the particular interconnect metal routing shown as connecting between individual ones of the logic function circuits 12 a-12 n is entirely arbitrary and is intended to convey the concept of the present invention and is not intended to represent interconnects forming any particular logic network.

Also depicted in fig. 1, a region of "white space" is present on the integrated circuit die. As used herein, a region of "white space" on an integrated circuit die is a region where there is no bottom diffusion in the substrate or no gate region or metal interconnect in a layer above the substrate. Up to about 70% of the area of the integrated circuit die is typically occupied by diffusion in the substrate or by gate regions and metal interconnect lines in layers above the substrate, leaving at least 30% of the area of the integrated circuit die as empty space.

According to an aspect of the invention, logic elements are placed into the empty spaces during layout design, thereby at least partially filling the empty spaces with logic elements. While these logic elements may take a variety of forms, a particularly useful logic element is a multiplexer-based LUT, as it can be configured to implement many different logic functions. Examples of such LUTs are depicted in fig. 2A and 2B. The LUT 16 shown in fig. 2A and 2B is a four input multiplexer based LUT having inputs 18, 20, 22 and 24. The LUT 16 has an a select input 26 and a B select input 28 and an output 30. The respective a and B select inputs 26, 28 and outputs 30 are electrically isolated from (i.e., not electrically connected to) other logic function circuitry on the integrated circuit die. Both the VDD rail 32 and the VSS rail 34 form intersections with the inputs 18, 20, 22 and 24. VDD rail 32 and VSS rail 34 are shown as being formed from metal interconnect lines on one metal interconnect layer (shown as metal interconnect layer M2), and inputs 18, 20, 22, and 24 are shown as being formed from metal interconnect lines on another metal interconnect layer (shown as metal interconnect layer M1). The skilled person will understand that the choice of metal layers for these lines is somewhat arbitrary.

LUT 16 in fig. 2A is shown in an initial state in which inputs 18, 20, 22 and 24 are all tied to VSS rail 34 through metal vias 36, 38, 40 and 42, respectively. There are no active devices under the area indicated by the dashed line 44. This allows the use of the FIB to change the state of the LUT inputs without damaging the underlying circuit structure due to the destructive nature of the FIB process.

The present invention enables post-silicon logic modification via direct silicon editing. Fig. 2B shows the same LUT 16 after metal vias 38 and 40 (shown in dashed lines 38 and 40 in fig. 2B) have been broken using FIB techniques to disconnect LUT inputs 20 and 22 from VSS rail 34 and form intermetallic connections 46 and 48 between LUT inputs 20 and 22 and VDD rail 32.

In the particular LUT 16 shown in fig. 2A and 2B, these exemplary connection variations configure the LUT 16 as an exclusive or gate for the inputs appearing on the a select input 26 and the B select input 28. Those of ordinary skill in the art will appreciate that the configuration shown in fig. 2B is for illustrative purposes only, and that any available combination of voltages presented to the various inputs of LUT 16 will result in any available logic function that LUT 16 may be configured to perform.

As will be appreciated by those of ordinary skill in the art, the availability of these "spare" white space logic elements (such as LUTs 16) allows for extensive fault repair in an integrated circuit without having to reconfigure one or more metal interconnect mask layers. Fig. 3 is a block diagram of a portion 50 of an integrated circuit formed on a semiconductor die that includes several logic function circuits 12 a-12 n. The logic function circuits 12a to 12n are interconnected to form a logic network, as shown in the block diagram of fig. 1.

In the block diagram of portion 50 of the integrated circuit die of fig. 3, at least some of the prior art "white space" areas 14a and 14b are instead occupied by LUTs 16a and 16b (such as those shown in fig. 2A) in their initial state in which inputs 18, 20, 22 and 24 are all tied to VSS rail 34 through metal vias 36, 38, 40 and 42, respectively.

The arrangement of fig. 3 provides new fault repair capabilities. The cost of post-silicon fail-over is reduced by allowing the formation of logic cells by unblanking and reconnecting that have the flexibility to lower level failures during FIB editing, allowing the repair in silicon to be confirmed without layout mask rework. Using the multiplexer-based LUT approach of the present invention, the fill design can dedicate die area to the FIB to edit the connections of the multiplexer-based LUT input lines to the respective VDD/VSS intersections to define the desired logic function for fault repair. Connections to multiplexer-based LUT select inputs 26 and 28 and output 30 may be made using known FIB reconnection techniques.

The logic insertion fault repair of the present invention may be quite local, depending on the distribution and size of the white space on the die of any particular integrated circuit design.

Referring again to FIG. 3, an illustrative and non-limiting example of a circuit design failure for which repair can be made using the present invention is presented. In the example shown in fig. 3, metal interconnect line segment 52 is used to connect output 54 of logic cell 12e to input 56 of logic cell 12 c. Assuming that during post-silicon design debugging, this direct connection has been found to be erroneous, and the logic intended to be implemented is that the input 56 of logic cell 12c is considered to be driven by the exclusive-or combination of the output 54 of logic cell 12e and the output 58 of logic cell 12 i.

Without the availability of LUTs 16a in the white space regions 14a, not only does one or more metal interconnect layers need to be redefined by metal mask changes, but additional xor gates may also need to be incorporated into the circuit design. By using the arrangement of the present invention, such fault repair can be performed quickly and relatively easily, as shown with reference to fig. 4.

Fig. 4 is a block diagram of a portion 50 of an integrated circuit formed on a semiconductor die illustrating that fault repair may be performed using the present invention. In fig. 4, vias 38 and 40 (most easily seen in fig. 2B) have been FIB broken and indicated by the remaining dashed circles where they were, to delete the connection to the VSS rail 34, and both inputs 20 and 22 of LUT 16a have been connected to VDD rail 32 using FIB techniques, as indicated by filled circles 46 and 48. This input reconnection configures LUT 16a as an exclusive or gate, as described with reference to fig. 2B.

As shown in fig. 4, conventional FIB techniques are used to break metal interconnect line segments 52 (now shown in dashed lines 52). FIB techniques are used to form new metal interconnect line segments. A first new metal interconnect line segment 60 is formed to establish a connection between the output 54 of logic cell 12e and the a-select input 26 of LUT 16 a. A second new metal interconnect line segment 62 is formed to establish a connection between the output 58 of logic cell 12i and the B select input 28 of LUT 16 a. A third new metal interconnect line segment 64 is formed to establish a connection between the output 30 of the LUT 16a and the input 56 of the logic cell 12 c.

Referring now to FIG. 5, a flow chart illustrates an exemplary circuit error correction method 70 in accordance with an aspect of the present invention. The method begins at reference numeral 72.

At reference numeral 74, a design failure is identified. At reference numeral 76, the logic function to be inserted is identified and the die location of the connection to be severed is located.

At reference numeral 78, the die locations of available configurable logic function circuits are determined. It is not required that the selected available configurable logic function circuits be in fact the most recent and that other available configurable logic function circuits may be used without exceeding the range. At reference numeral 80, the FIB system is directed to the determined location of the available configurable logic function circuitry. At reference numeral 82, the FIB system is engaged to configure the logic functions of the identified available configurable logic function circuits.

At reference numeral 84, the FIB system is directed to the determined location of the identified connection to be severed. At reference numeral 86, the FIB system is engaged to sever the identified connection. At reference numeral 88, a path is defined for new metal interconnect lines needed to connect the inputs/outputs of the available configurable logic function circuitry. At reference numeral 90, the FIB system is bonded to form a new metal interconnect line. The method ends at reference numeral 92.

Those of ordinary skill in the art will appreciate that the order of the sequence of steps for defining the functions of the white space logic elements and the sequence of steps for severing unnecessary connections and defining and forming new connections to and from the available configurable logic function circuits and the inputs and outputs of the existing logic networks in the integrated circuit die is not critical.

The present invention has the advantage that it provides a high probability of adding functional logic changes using FIB, enabling editing on a functionally failed silicon die without the need for metal remake/reflow. The present invention allows for the verification of fault repair before incurring the expense of providing a modified metal mask and manufacturing new silicon.

Although the present invention has been described with reference to an integrated circuit employing a mask-defined logic network, those skilled in the art will appreciate that the present design techniques may be applied to post-silicon fail-over editing using any digital/mixed signal design of ASIC place and route implementation methods.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. Accordingly, the invention is not limited except as by the spirit of the appended claims.