阅读说明：本技术 模拟数字转换器、传感器系统以及测试系统 (Analog-to-digital converter, sensor system and test system ) 是由 小畑幸嗣 中顺一 中塚淳二 芳野大树 永井正昭 于 2020-03-13 设计创作，主要内容包括：提供一种能够谋求测试处理的时间的缩短的模拟数字(AD)转换器、传感器系统以及测试系统。AD转换器(1)具备输入部(3)、AD变换部(2)、第1输出部(41)、以及第2输出部(42)。输入部(3)被输入从传感器(101)输出的模拟信号。AD变换部(2)对模拟信号进行数字变换并生成第1数字数据以及第2数字数据。第1输出部(41)将第1数字数据输出到控制电路(200)。第2输出部(42)在第1输出部(41)输出第1数字数据之前,将第2数字数据输出到测试控制部(301)。测试控制部(301)在测试模式下,基于第2数字数据判定包含传感器(101)的传感器系统(100)是否为异常状态。(Provided are an analog-digital (AD) converter, a sensor system, and a test system, wherein the time for a test process can be shortened. The AD converter (1) is provided with an input unit (3), an AD conversion unit (2), a 1 st output unit (41), and a 2 nd output unit (42). The input unit (3) receives an analog signal output from the sensor (101). An AD conversion unit (2) performs digital conversion on the analog signal to generate 1 st digital data and 2 nd digital data. A1 st output unit (41) outputs the 1 st digital data to the control circuit (200). The 2 nd output unit (42) outputs the 2 nd digital data to the test control unit (301) before the 1 st output unit (41) outputs the 1 st digital data. A test control unit (301) determines whether or not a sensor system (100) including a sensor (101) is in an abnormal state based on the 2 nd digital data in a test mode.)

1. An analog-digital converter is provided with:

an input unit to which an analog signal output from the sensor is input;

an analog-to-digital conversion unit that performs digital conversion on the analog signal to generate 1 st digital data and 2 nd digital data;

a 1 st output unit that outputs the 1 st digital data to a control circuit; and

a 2 nd output unit that outputs the 2 nd digital data to a test control unit before the 1 st output unit outputs the 1 st digital data,

the test control unit determines whether or not a sensor system including the sensor is in an abnormal state based on the 2 nd digital data in a test mode.

2. The analog-to-digital converter of claim 1,

the 2 nd digital data has a smaller number of bits than the 1 st digital data.

3. The analog-to-digital converter of claim 1 or 2,

the analog-digital conversion unit includes: a 1 st analog-to-digital converter and a 2 nd analog-to-digital converter connected in series; and a digital filter for filtering the digital data and the digital data,

the 2 nd analog-to-digital converter is disposed at a front stage of the 1 st analog-to-digital converter and generates the 2 nd digital data,

said 1 st analog-to-digital converter is a delta sigma analog-to-digital converter,

the digital filter generates the 1 st digital data by performing a filtering process on an output of the 1 st analog-to-digital converter.

4. The analog-to-digital converter of claim 3,

the 2 nd analog-to-digital converter is a successive comparison analog-to-digital converter.

5. The analog-to-digital converter of claim 3,

the 2 nd analog-to-digital converter is a flash type analog-to-digital converter.

6. The analog-to-digital converter of claim 1 or 2,

the analog-digital conversion section has an analog-digital converter and a digital filter,

the analog-to-digital converter generates the 2 nd digital data which is a multi-bit digital data and outputs the generated data to the 2 nd output unit and the digital filter,

the digital filter generates the 1 st digital data by performing a filtering process on an output of the analog-to-digital converter.

7. The analog-to-digital converter of claim 6,

the analog-to-digital converter is a noise-shaped successive-comparison AD converter or a multi-bit delta sigma analog-to-digital converter.

8. A sensor system is provided with:

an analog-to-digital converter as claimed in any one of claims 1 to 7; and

the sensor is provided.

9. A test system is provided with:

the sensor system of claim 8; and

the test control part.

Technical Field

The present disclosure relates generally to an analog-to-digital converter (AD converter), and a sensor system and a test system using the AD converter, and more particularly to an AD converter that digitally converts an analog signal, and a sensor system and a test system using the AD converter.

Background

Conventionally, a noise shaping (noise shaping) type successive approximation AD converter (AD converter) is known which maintains low power consumption of the successive approximation AD converter and achieves high resolution as in the Δ Σ type AD converter (see, for example, patent document 1).

The noise shaping successive approximation AD converter of patent document 1 is configured by adding an integration circuit to a normal successive approximation AD converter. In the noise-shaping successive comparison AD converter of patent document 1, the residual voltage of a capacitor DAC (digital-to-analog converter) after the successive comparison operation is performed to LSB (least significant bit) is integrated and fed back to the next sample, thereby obtaining noise shaping characteristics in the output data.

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2017-147712

Disclosure of Invention

In order to achieve high resolution of output data in an AD converter, the AD converter requires a long time for digital conversion processing such as a digital filter of a noise shaping AD converter, and thus the latency (1 latency) is increased. Therefore, when a test process for determining whether or not the sensor system is in an abnormal state is performed using the output data of the AD converter, the test process may take a long time.

The present disclosure has been made in view of the above circumstances, and an object thereof is to provide an AD converter capable of shortening the time of a test process, and a sensor system and a test system using the AD converter.

An AD converter according to an embodiment of the present disclosure includes an input unit, an AD conversion unit, a 1 st output unit, and a 2 nd output unit. The input unit receives an analog signal output from the sensor. The AD conversion unit performs digital conversion on the analog signal to generate 1 st digital data and 2 nd digital data. The 1 st output section outputs the 1 st digital data to the control circuit. The 2 nd output unit outputs the 2 nd digital data to the test control unit before the 1 st output unit outputs the 1 st digital data. In the test mode, the test control unit determines whether or not the sensor system including the sensor is in an abnormal state based on the 2 nd digital data.

A sensor system according to an aspect of the present disclosure includes: an AD converter according to one embodiment of the present disclosure; and a sensor.

A test system according to an embodiment of the present disclosure includes: a sensor system according to one embodiment of the present disclosure; and a test control section.

The present disclosure has an effect of shortening the time of the test processing.

Drawings

Fig. 1 is a block diagram of a sensor system and a test system including an AD converter according to an embodiment of the present disclosure.

Fig. 2 is an explanatory diagram of an operation of the AD converter according to the embodiment of the present disclosure.

Fig. 3 is a block diagram of a sensor system and a test system including the AD converters according to modification 1 and modification 2 of the embodiment of the present disclosure.

Detailed Description

The embodiments and modifications described below are merely examples of the present disclosure, and the present disclosure is not limited to the embodiments and modifications. In addition to the embodiment and the modification, various modifications may be made in accordance with design and the like without departing from the scope of the technical idea of the present disclosure.

(embodiment mode)

(1) Structure of the product

Fig. 1 shows a block diagram of a sensor system 100 and a test system 300 including an AD converter 1 (AD: Analog to Digital) according to the present embodiment.

The AD converter 1 of the present embodiment is used at an analog front end (sensor processing circuit 10) of the sensor system 100, and performs digital conversion on an analog signal from the sensor 101.

The sensor processing circuit 10 includes an AD converter 1 and an amplifier 11, and performs signal processing on a signal from the sensor 101 and outputs the signal to the control circuit 200.

The sensor system 100 includes a sensor 101 and a sensor processing circuit 10.

The test system 300 includes the sensor system 100 and a test control unit 301. The test control unit 301 determines whether or not the sensor system 100 is in an abnormal state based on the output data of the AD converter 1.

The sensor 101 is configured to detect a physical quantity of a measurement target or a change amount thereof. The sensor 101 outputs an analog signal including a voltage value corresponding to the detection result or a change in capacitance value of the capacitor to the sensor processing circuit 10. That is, the sensor 101 functions as a signal output unit that outputs an analog signal. The sensor processing circuit 10 performs digital conversion on an analog signal output from the sensor 101 and outputs the signal to the control circuit 200.

In the present embodiment, the sensor system 100 is applied to a mobile body such as an automobile, as an example. The sensor 101 is an acceleration sensor that detects the acceleration of the moving body as a measurement target. The Control circuit 200 that receives the detection result of the sensor 101 is an ECU (Electronic Control Unit) mounted on the vehicle. These are examples, and the sensor 101 is not limited to an acceleration sensor, and may be a gyro sensor, a pressure sensor, a motion sensor, or the like. Further, the sensor system 100 may be applied to a device different from a mobile body such as an automobile.

The sensor processing circuit 10 is an analog front end that performs signal processing on an analog signal from the sensor 101 and outputs the signal to the control circuit 200.

The sensor processing circuit 10 includes an AD converter 1 and an amplifier 11.

The amplifier 11 is configured to amplify an analog signal from the sensor 101. The amplifier 11 receives an analog signal output from the sensor 101. The amplifier 11 amplifies the amplitude at a predetermined amplification factor when the input analog signal is a voltage, or amplifies the change in capacitance value at a predetermined amplification factor after converting the change in capacitance value into a change in voltage or current and outputs the change to the AD converter 1 connected to the subsequent stage when the analog signal is a change in capacitance value.

The AD converter 1 includes an AD converter 2, an input unit 3, a 1 st output unit 41, and a 2 nd output unit 42, converts the amplitude of an analog signal into digital data of a predetermined number of bits, and outputs the digital data to the control circuit 200 and the test control unit 301. In the present embodiment, the AD converter 1 is configured to output 21-bit digital data (1 st digital data) to the control circuit 200 and 9-bit digital data (2 nd digital data) to the test control unit 301, as an example. The number of bits of the 1 st digital data and the 2 nd digital data is an example, and is not limited to this value.

The input section 3 is electrically connected to the amplifier 11. The input unit 3 receives an analog signal output from the sensor 101 via the amplifier 11.

The AD converter 2 includes a 1 st AD converter 21, a 2 nd AD converter 22, and a digital filter 23. The 1 st AD converter 21 and the 2 nd AD converter 22 are cascade-connected (series-connected), and the 2 nd AD converter 22 is provided at the front stage of the 1 st AD converter 21.

The 2 nd AD converter 22 is a Successive Approximation AD converter (SAR). The 2 nd AD converter 22 is provided with a capacitance DA converter (DA: Digital to Analog). The capacitance DA converter has a plurality of capacitors (capacitance elements). One end of each capacitor is electrically connected to the input unit 3, and the other end is selectively electrically connected to either one of the 1 st voltage source and the 2 nd voltage source. The output voltages of the 1 st voltage source and the 2 nd voltage source are different from each other.

The 2 nd AD converter 22 generates digital data (2 nd digital data) having a plurality of bits by sequentially repeating the comparison operation between the amplitude voltage of the analog signal and the voltage generated by the capacitance DA converter. Specifically, the AD converter 2 includes a comparator and a successive approximation control circuit. The comparator compares an input voltage (amplitude of the analog signal) input to the input unit 3 with a comparison reference voltage. Then, the successive comparison control circuit generates a successive comparison control signal of the next bit based on the comparison result of the comparator and outputs the successive comparison control signal to the capacitance DA converter. Each capacitor of the capacitance DA converter selectively electrically connects the other end to either one of the 1 st voltage source and the 2 nd voltage source in accordance with the successive comparison control signal. The 2 nd AD converter 22 repeats the sequential comparison operation to generate digital data of a plurality of bits. In the present embodiment, the 2 nd AD converter 22 generates 9-bit 2 nd digital data as an example.

The 1 st AD converter 21 is a Δ Σ type AD converter. The 1 st AD converter 21 has a subtractor, an integrator, a quantizer, and a DA converter, and performs Δ Σ modulation. The subtractor is a differential amplifier, and a residual voltage (equivalent to quantization noise) of the capacitance DA converter after the successive comparison operation in the 2 nd AD converter 22 and a reference signal are input thereto. The subtractor subtracts the reference signal from the residual voltage. The integrator cumulatively adds the operation results in the subtractor. The quantizer compares the operation result of the integrator with a reference signal to determine a digital value of 1 bit. The result of this quantizer is output to the digital filter 23 and the DA converter at the subsequent stage. The DA converter is a 1-bit DA converter, and determines a reference signal to be fed back and output to the subtractor based on the result of the quantizer.

The 1 st AD converter 21 may be a high-order Δ Σ AD converter including a plurality of subtractors and integrators. The higher the order, the more the quantization noise can be shifted to the high frequency side, and the conversion accuracy can be improved.

The digital filter 23 performs a filtering process on the output of the 1 st AD converter 21. As the filtering process, the digital filter 23 has a band limiting function and a decimation (interval extraction) function. The output of the 1 st AD converter 21, which is a Δ Σ AD converter, contains noise-shaped high-frequency noise based on quantization noise, and the data rate is higher than the original sampling frequency due to oversampling. Accordingly, the digital filter 23 reduces high frequency noise by the band limiting function, and reduces the data rate by the decimation function. The digital filter 23 generates digital data of a plurality of bits by performing a filtering process on the 1-bit output of the 1 st AD converter 21. In the present embodiment, as an example, the digital filter 23 performs filtering processing on the output of the 1 st AD converter 21 to generate 21-bit digital data (1 st digital data) in which the 9-bit 2 nd digital data generated by the 2 nd AD converter 22 is the upper bit.

The 1 st output section 41 has an output port for outputting the 21 st digital data of bits generated by the digital filter 23. The 1 st output section 41 outputs the 1 st digital data to the control circuit 200. The control circuit 200 controls an external device to be controlled based on the 1 st digital data obtained by digitally converting the analog signal output from the sensor 101.

The 2 nd output section 42 has an output port for outputting the 9 nd bit 2 nd digital data generated by the 2 nd AD converter 22. The 2 nd output unit 42 outputs the 2 nd digital data to the test control unit 301.

The test control section 301 determines whether or not the sensor system 100 is in an abnormal state based on the 2 nd digital data. Specifically, the test control unit 301 includes a determination unit 302 and a signal output unit 303. The test control unit 301 has a test mode as an operation mode. When the operation mode is the test mode, the test control unit 301 transmits a test signal from the signal output unit 303 to the sensor 101. Upon receiving the test signal, the sensor 101 outputs an analog signal having an amplitude corresponding to the test signal. The analog signal output from the sensor 101 is AD-converted into 2 nd digital data by the AD converter 1, and output to the determination unit 302. The determination unit 302 compares the received 2 nd digital data with a reference value (reference range) corresponding to the test signal output from the signal output unit 303, thereby determining whether or not the sensor system 100 is in an abnormal state. If the sensor 101 and the AD converter 1 are in a normal state, the 2 nd digital data corresponding to the test signal is output to the test control unit 301. When at least one of the sensor 101 and the AD converter 1 is in an abnormal state, the 2 nd digital data is a value that deviates from the reference value (reference range). In this case, the determination unit 302 determines that the sensor system 100 is in an abnormal state.

Here, the 1 st digital data is generated by Δ Σ modulation by the 1 st AD converter 21 and filter processing by the digital filter 23 after the 2 nd AD converter 22 completes generation of the 2 nd digital data of 9 bits. That is, after the 2 nd digital data is generated, the 1 st digital data is generated. Therefore, the 2 nd output unit 42 outputs the 2 nd digital data to the test control unit 301 before the 1 st output unit 41 outputs the 1 st digital data. That is, the latency (delay time) of the 2 nd digital data is smaller than the latency (delay time) of the 1 st digital data.

In addition, instead of the independent test mode, the test signal may be superimposed on the sensor 101 in the normal operation to perform the test of the sensor system 100.

(example of operation)

An operation example of the AD converter 1 according to the present embodiment will be described with reference to fig. 2.

Here, the AD conversion processing for the amplitude of the analog signal output from the sensor 101 that received the test signal to the input unit 3 at the time point t0 will be described.

The 2 nd AD converter 22 of the AD converter 2 repeats the successive comparison operation. At a time point t1, the 2 nd AD converter 22 completes generation of the 2 nd digital data of 9 bits. The 2 nd output unit 42 outputs the 9 nd-bit 2 nd digital data generated by the 2 nd AD converter 22 to the test control unit 301. Strictly speaking, a time difference due to signal processing or the like of the 2 nd output unit 42 occurs between the time when the 2 nd digital data is generated by the 2 nd AD converter 22 and the time when the 2 nd digital data is output by the 2 nd output unit 42, but the time difference is small and is therefore ignored here.

Further, at a time point t1, the 1 st AD converter 21 starts Δ Σ modulation. Further, the digital filter 23 starts the filtering process of the output of the 1 st AD converter 21.

At a time point t2, the digital filter 23 completes the filtering process. That is, the generation of the 2 nd digital data of 9 bits generated by the 2 nd AD converter 22 as the 1 st digital data of 21 bits of the upper bits is completed. The 1 st output unit 41 outputs the generated 21 st digital data to the control circuit 200. Strictly speaking, a time difference due to signal processing or the like of the 1 st output unit 41 occurs between the time when the 1 st digital data is generated by the digital filter 23 and the time when the 1 st digital data is output by the 1 st output unit 41, but the time difference is negligible here.

In this way, the AD converter 1 of the present embodiment outputs the 2 nd digital data to the test control unit 301 before outputting the 1 st digital data to the control circuit 200. The 2 nd digital data has a lower resolution (number of bits) than the 1 st digital data, but has a smaller latency. That is, in the AD converter 1 of the present embodiment, since the 1 st digital data with high resolution and the 2 nd digital data with small latency can be output, both high resolution and low latency of the output data can be achieved.

In the present embodiment, the AD converter 1 outputs the 1 st digital data with high resolution to the control circuit 200, and outputs the 2 nd digital data with low latency to the test control unit 301. Therefore, the control circuit 200 can control the external device to be controlled based on the 1 st digital data having a high resolution, and thus can achieve high accuracy in controlling the external device. Further, since the 2 nd digital data with a small waiting time is input to the test control unit 301, the time for the test process of determining whether or not the sensor system 100 is in an abnormal state can be shortened.

In the present embodiment, the 1 st AD converter 21 and the 2 nd AD converter 22 are connected in series, and the 2 nd digital data used for the test processing corresponds to the upper bit of the 1 st digital data output to the control circuit 200. Therefore, in the test process performed by the test control unit 301, it is possible to determine whether or not the 2 nd AD converter 22 is normal.

(modification example)

A modified example of the AD converter 1 according to the present embodiment will be described below.

(modification 1)

The AD converter 1 according to modification 1 will be described with reference to fig. 3.

Note that the same components as those of the AD converter 1 according to the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

In the above example, the AD converter 1 is an AD converter in which the AD converter unit 2 has a plurality of AD converters, but is not limited thereto.

As shown in fig. 3, the AD converter 2 may be provided with a single AD converter 24. The AD converter 24 of the present modification is a noise shaping type successive approximation AD converter. The 1 st AD converter 21 (see fig. 1) is a single-bit Δ Σ AD converter, and is configured to generate 1-bit digital data by Δ Σ modulation and output the data to the digital filter 23. On the other hand, the AD converter 24 generates digital data having a noise shaping characteristic of a plurality of bits (for example, 9 bits). The AD converter 24 outputs the generated 9-bit digital data as 2 nd digital data to the 2 nd output unit 42 and the subsequent digital filter 23.

The 2 nd output unit 42 outputs the 2 nd digital data generated by the AD converter 24 to the test control unit 301.

The digital filter 23 generates 21-bit digital data (1 st digital data) by performing filter processing on the 9-bit digital data (2 nd digital data) generated by the AD converter 24. The 1 st output unit 41 outputs the 1 st digital data generated by the digital filter 23 to the control circuit 200.

That is, in the present modification, the 2 nd output unit 42 outputs the 2 nd digital data before the filtering process by the digital filter 23 to the test control unit 301. Therefore, the 2 nd output unit 42 can output the 2 nd digital data to the test control unit 301 before the 1 st output unit 41 outputs the 1 st digital data. That is, the latency (delay time) of the 2 nd digital data is smaller than the latency (delay time) of the 1 st digital data.

(modification 2)

The AD converter 1 according to modification 2 will be described with reference to fig. 3.

Note that the same components as those of the AD converter 1 according to the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

In the above example, the AD converter 1 is an AD converter in which the AD converter unit 2 has a plurality of AD converters, but is not limited thereto.

As shown in fig. 3, the AD converter 2 may be provided with a single AD converter 24. The AD converter 24 of the present modification is a multi-bit Δ Σ AD converter. The 1 st AD converter 21 (see fig. 1) is a single-bit Δ Σ AD converter, and is configured to generate 1-bit digital data by Δ Σ modulation and output the data to the digital filter 23. On the other hand, the AD converter 24 generates digital data of a plurality of bits (for example, 4 bits) by Δ Σ modulation. The AD converter 24 outputs the generated 4-bit digital data as 2 nd digital data to the 2 nd output unit 42 and the subsequent digital filter 23.

The 2 nd output unit 42 outputs the 2 nd digital data generated by the AD converter 24 to the test control unit 301.

The digital filter 23 generates 21-bit digital data (1 st digital data) by performing filter processing on the 4-bit digital data (2 nd digital data) generated by the AD converter 24. The 1 st output unit 41 outputs the 1 st digital data generated by the digital filter 23 to the control circuit 200.

That is, in the present modification, the 2 nd output unit 42 outputs the 2 nd digital data before the filtering process by the digital filter 23 to the test control unit 301. Therefore, the 2 nd output unit 42 can output the 2 nd digital data to the test control unit 301 before the 1 st output unit 41 outputs the 1 st digital data. That is, the latency (delay time) of the 2 nd digital data is smaller than that of the 1 st digital data.

(other modification example)

In the above example, the 2 nd AD converter 22 (see fig. 1) is a successive approximation AD converter, but the present invention is not limited to this, and an AD converter of another AD conversion architecture may be used. For example, the 2 nd AD converter 22 may be a flash type AD converter.

The flash AD converter includes a plurality of resistors and a plurality of comparators. The plurality of resistors are connected in series between a reference power supply that outputs a reference voltage and a circuit ground, and generate a plurality of reference divided voltages that divide the reference voltage into a plurality of voltages. The plurality of reference divided voltages correspond to the plurality of comparators one to one. Each comparator compares the corresponding reference divided voltage with the amplitude of the analog signal input to the input unit 3. The flash type AD converter generates 2 nd digital data based on the output of each comparator. In a flash type AD converter, the time required for digital conversion processing can be shortened as compared with a successive approximation type AD converter.

The 2 nd AD converter 22 may be an AD converter having an AD conversion architecture different from that of the successive approximation AD converter and the flash AD converter. For example, the 2 nd AD Converter 22 may be a pipeline (pipe line) type AD Converter, a single slope (single slope) type AD Converter, a double integration type AD Converter, a TDC type AD Converter (TDC: Time to Digital Converter), a cyclic AD Converter, an incremental AD Converter, or the like. The 2 nd AD converter 22 may be a Δ Σ type AD converter having the same AD conversion structure as the 1 st AD converter 21.

The 1 st AD converter 21 may be a successive approximation AD converter, a flash AD converter, a pipeline AD converter, a single slope AD converter, a double integration AD converter, a TDC AD converter, a cyclic AD converter, an incremental AD converter, or the like.

In the above example, the 1 st AD converter 21 and the 2 nd AD converter 22 are connected in series, but the 1 st AD converter 21 and the 2 nd AD converter 22 may be connected in parallel.

The AD converter unit 2 is not limited to two AD converters, and may be configured to include three or more AD converters.

The digital filter 23 can be omitted as appropriate depending on the type of AD converter provided in the AD converter 2.

(conclusion)

An AD converter (1) according to claim 1 is provided with an input unit (3), an AD conversion unit (2), a 1 st output unit (41), and a 2 nd output unit (42). The input unit (3) receives an analog signal output from the sensor (101). An AD conversion unit (2) performs digital conversion on the analog signal to generate 1 st digital data and 2 nd digital data. A1 st output unit (41) outputs the 1 st digital data to the control circuit (200). The 2 nd output unit (42) outputs the 2 nd digital data to the test control unit (301) before the 1 st output unit (41) outputs the 1 st digital data. A test control unit (301) determines whether or not a sensor system (100) including a sensor (101) is in an abnormal state based on the 2 nd digital data in a test mode.

According to this aspect, since the 2 nd digital data with a small waiting time can be output to the test control unit (301), the time for the test process in the test control unit (301) can be shortened.

In the AD converter (1) according to claim 2, in the AD converter (1) according to claim 1, the number of bits of the 2 nd digital data is smaller than that of the 1 st digital data.

According to this mode, the latency of the 2 nd digital data can be made smaller.

In the AD converter (1) according to claim 3, in the AD converter (1) according to claim 1 or 2, the AD conversion unit (2) includes: a 1 st AD converter (21) and a 2 nd AD converter (22) connected in series; and a digital filter (23). A2 nd AD converter (22) is provided at a stage preceding the 1 st AD converter (21) and generates 2 nd digital data. The 1 st AD converter (21) is a delta sigma type AD converter. A digital filter (23) generates 1 st digital data by performing a filtering process on the output of the 1 st AD converter (21).

According to this aspect, the resolution of the 1 st digital data can be further improved.

In the AD converter (1) according to claim 4, in the AD converter (3), the 2 nd AD converter (22) is a successive approximation AD converter.

According to this mode, the latency of the 2 nd digital data can be made smaller.

In the AD converter (1) according to claim 5, in claim 3, the 2 nd AD converter (22) is a flash-type AD converter.

According to this mode, the latency of the 2 nd digital data can be made smaller.

In the AD converter (1) according to claim 6, in the AD converter (1) or 2, the AD converter unit (2) includes an AD converter (24) and a digital filter (23). An AD converter (24) generates 2 nd digital data which is multi-bit digital data, and outputs the data to a 2 nd output unit (42) and a digital filter (23). A digital filter (23) generates 1 st digital data by performing a filtering process on the output of the AD converter (24).

According to this aspect, the resolution of the 1 st digital data can be further improved.

In the AD converter (1) according to claim 7, in claim 6, the AD converter (24) is a noise-shaping successive-comparison AD converter or a multi-bit Δ Σ AD converter.

According to this mode, the latency of the 2 nd digital data can be made smaller.

The sensor system (100) according to claim 8 includes: an AD converter (1) according to any one of claims 1 to 7; and a sensor (101).

According to this aspect, the time for the test processing in the test control unit (301) can be shortened.

The test system (300) according to claim 9 includes: the sensor system (100) according to claim 8; and a test control unit (301).

According to this aspect, the time for the test processing in the test control unit (301) can be shortened.

Industrial applicability

The AD converter, the sensor system, and the test system according to the present disclosure can shorten the time required for the digital conversion process and shorten the time of the test process, and are industrially useful.

Description of the reference numerals

1: an AD converter;

2: an AD conversion unit;

21: a 1 st AD converter (a Σ type AD converter);

22: a 2 nd AD converter (successive approximation AD converter, flash AD converter);

23: a digital filter;

24: an AD converter (noise shaping type successive approximation AD converter, multi-bit Δ Σ type AD converter);

3: an input section;

41: a 1 st output unit;

42: a 2 nd output unit;

100: a sensor system;

101: a sensor;

200: a control circuit;

300: testing the system;

301: a test control unit.