阅读说明：本技术 阵列基板及其制作方法、显示装置 (Array substrate, manufacturing method thereof and display device ) 是由 赵约瑟 李水龙 颜金成 王凯 乔传兴 于 2021-07-28 设计创作，主要内容包括：本发明适用于显示装置领域,提出一种阵列基板,所述阵列基板包括多条扫描线和多条数据线,多条所述扫描线和多条所述数据线交叉并形成多个像素区域；各所述像素区域内设有主动元件、与所述主动元件电连接的像素电极、以及反射层,所述反射层设于所述像素电极的上方并与所述像素电极电连接。本申请同时提出一种阵列基板的制作方法及一种显示装置。上述阵列基板能够反射射入显示装置中的环境光,具有反射效果,采用上述阵列基板的显示装置无需设置背光源,节省了电源消耗,具有低功耗的优点,有利于提升显示装置的续航时间。(The invention is suitable for the field of display devices, and provides an array substrate, which comprises a plurality of scanning lines and a plurality of data lines, wherein the plurality of scanning lines and the plurality of data lines are crossed to form a plurality of pixel regions; an active element, a pixel electrode electrically connected with the active element and a reflecting layer are arranged in each pixel region, and the reflecting layer is arranged above the pixel electrode and electrically connected with the pixel electrode. The application also provides a manufacturing method of the array substrate and a display device. Above-mentioned array substrate can reflect the ambient light who jets into display device, has the reflection effect, and the display device who adopts above-mentioned array substrate need not to set up the backlight, has saved power consumption, has the advantage of low-power consumption, is favorable to promoting display device's time of endurance.)

1. The array substrate is characterized by comprising a plurality of scanning lines and a plurality of data lines, wherein the plurality of scanning lines and the plurality of data lines are crossed to form a plurality of pixel regions;

an active element, a pixel electrode electrically connected with the active element and a reflecting layer are arranged in each pixel region, and the reflecting layer is arranged above the pixel electrode and electrically connected with the pixel electrode.

2. The array substrate of claim 1, wherein the active device comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprising a first gate electrode, a first semiconductor layer, a first source electrode and a first drain electrode, the second thin film transistor comprising a second gate electrode, a second semiconductor layer, a second source electrode and a second drain electrode;

in each pixel region, the first gate is connected to a corresponding scan line, the first source is connected to a corresponding data line, the first drain is connected to a corresponding second source, and the second drain is connected to a corresponding pixel electrode.

3. The array substrate of claim 1, further comprising a planarization layer covering the pixel electrodes, wherein the planarization layer has through holes, and the pixel electrodes are electrically connected to the corresponding reflective layers through the through holes.

4. The array substrate of claim 1, wherein the reflective layer covers both the pixel electrode and the active device.

5. The array substrate of claim 1, wherein a common electrode is further disposed in the pixel region, and the common electrode partially overlaps the pixel electrode to form a storage capacitor.

6. A manufacturing method of an array substrate is characterized by comprising the following steps:

manufacturing a plurality of scanning lines, a plurality of data lines and a plurality of active elements on a substrate;

manufacturing a plurality of pixel electrodes on the substrate, wherein each pixel electrode is electrically connected to the corresponding active element;

and manufacturing a reflecting layer on one side of the pixel electrode, which is far away from the substrate, wherein the reflecting layer is electrically connected with the pixel electrode.

7. The method of claim 6, wherein the active device comprises a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first grid electrode, a first semiconductor layer, a first source electrode and a first drain electrode, and the second thin film transistor comprises a second grid electrode, a second semiconductor layer, a second source electrode and a second drain electrode;

the method for manufacturing a plurality of scanning lines, a plurality of data lines and a plurality of active elements on a substrate comprises the following steps:

sputtering a first metal layer on the substrate base plate and exposing to form a plurality of scanning lines, a plurality of first grid electrodes and a plurality of second grid electrodes;

sequentially depositing a grid electrode insulating layer and a semiconductor layer on the substrate, and patterning the semiconductor layer to form a first semiconductor layer arranged above the first grid electrode and a second semiconductor layer arranged above the second grid electrode;

depositing a second metal layer on the substrate and exposing to form a plurality of data lines, a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes and a plurality of second drain electrodes, wherein the first gate electrodes are connected with the corresponding scan lines, the first source electrodes are connected with the corresponding data lines, and the first drain electrodes are connected with the corresponding second source electrodes.

8. The method of fabricating an array substrate according to claim 6, wherein after fabricating the plurality of pixel electrodes on the substrate, the method further comprises:

and depositing a flat layer on the substrate, wherein the flat layer covers the active element and the pixel electrode, and the flat layer is provided with a through hole for exposing part of the pixel electrode.

9. The method of claim 6, wherein the reflective layer covers the pixel electrode and the active device simultaneously.

10. A display device, comprising:

the array substrate of any one of claims 1-5;

the opposite substrate is arranged opposite to the array substrate;

and the liquid crystal is arranged between the array substrate and the opposite substrate.

Technical Field

The invention relates to the field of display devices, in particular to an array substrate, a manufacturing method of the array substrate and a display device.

Background

A Liquid Crystal Display (LCD) is a Display device that presents a desired image by selectively transmitting light emitted from a backlight using a polarization phenomenon of Liquid crystals. The TFT is a short term for "Thin Film Transistor", and is generally referred to as a Thin Film Transistor display. One of the most common TFT LCDs is a Twisted Nematic (TN) LCD, which includes an array substrate, a color filter substrate, a Liquid Crystal (Liquid Crystal) disposed therebetween, and a backlight source, wherein polarized light emitted from the backlight source passes through a Polarizer (Polarizer) on the array substrate, rotates 90 ° through the Liquid Crystal in an LCD box, and then is transmitted through the Polarizer on the color filter substrate to present an image.

Since TFT-LCD usually needs a backlight source, for mobile devices or devices, the backlight source occupies most of the power consumption, and when some applications require long endurance, the battery capacity is the biggest bottleneck, which limits endurance.

Disclosure of Invention

In view of this, the invention provides an array substrate, a manufacturing method thereof and a display device, which can reduce power consumption and improve endurance time of the display device.

The embodiment of the invention provides an array substrate, which comprises a plurality of scanning lines and a plurality of data lines, wherein the plurality of scanning lines and the plurality of data lines are crossed to form a plurality of pixel regions;

an active element, a pixel electrode electrically connected with the active element and a reflecting layer are arranged in each pixel region, and the reflecting layer is arranged above the pixel electrode and electrically connected with the pixel electrode.

In one embodiment, the active device includes a first thin film transistor including a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, and a second thin film transistor including a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode;

in each pixel region, the first gate is connected to a corresponding scan line, the first source is connected to a corresponding data line, the first drain is connected to the second source, and the second drain is connected to a corresponding pixel electrode.

In an embodiment, the array substrate further includes a flat layer covering the pixel electrode, the flat layer is provided with a through hole, and the pixel electrode is electrically connected to the corresponding reflection layer through the through hole.

In one embodiment, the reflective layer covers both the pixel electrode and the active device.

In an embodiment, a common electrode is further disposed in the pixel region, and the common electrode and the pixel electrode are partially overlapped to form a storage capacitor.

The invention also provides a manufacturing method of the array substrate, which comprises the following steps: manufacturing a plurality of scanning lines, a plurality of data lines and a plurality of active elements on a substrate;

manufacturing a plurality of pixel electrodes on the substrate, wherein each pixel electrode is electrically connected to the corresponding active element;

and manufacturing a reflecting layer on one side of the pixel electrode, which is far away from the substrate, wherein the reflecting layer is electrically connected with the pixel electrode.

In one embodiment, the active device includes a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first grid electrode, a first semiconductor layer, a first source electrode and a first drain electrode, and the second thin film transistor comprises a second grid electrode, a second semiconductor layer, a second source electrode and a second drain electrode;

the method for manufacturing a plurality of scanning lines, a plurality of data lines and a plurality of active elements on a substrate comprises the following steps:

sputtering a first metal layer on the substrate base plate and exposing to form a plurality of scanning lines, a plurality of first grid electrodes and a plurality of second grid electrodes;

sequentially depositing a grid electrode insulating layer and a semiconductor layer on the substrate, and patterning the semiconductor layer to form a first semiconductor layer arranged above the first grid electrode and a second semiconductor layer arranged above the second grid electrode;

depositing a second metal layer on the substrate and exposing to form a plurality of data lines, a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes and a plurality of second drain electrodes, wherein the first gate electrodes are connected with the corresponding scan lines, the first source electrodes are connected with the corresponding data lines, and the first drain electrodes are connected with the corresponding second source electrodes.

In an embodiment, after fabricating a plurality of pixel electrodes on the substrate base plate, the fabrication method further includes:

and depositing a flat layer on the substrate, wherein the flat layer covers the active element and the pixel electrode, and the flat layer is provided with a through hole for exposing part of the pixel electrode.

In one embodiment, the reflective layer covers both the pixel electrode and the active device.

The present invention also provides a display device, comprising:

an array substrate as claimed in any preceding embodiment;

the opposite substrate is arranged opposite to the array substrate;

and the liquid crystal is arranged between the array substrate and the opposite substrate.

The array substrate comprises an active element, a pixel electrode electrically connected with the active element, and a reflecting layer arranged above the pixel electrode and electrically connected with the pixel electrode, wherein the reflecting layer can reflect light, and the reflecting layer and a common electrode on the opposite substrate can drive liquid crystal together. The manufacturing method can be used for manufacturing the reflective array substrate, and is simple and low in cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the invention;

FIG. 3 is a schematic structural diagram of an active device according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for fabricating an array substrate according to an embodiment of the invention;

FIG. 5A is a schematic plan view of the array substrate after the first metal layer is formed;

FIG. 5B is a cross-sectional view of the array substrate after the first metal layer is formed;

fig. 6A is a schematic plan view of the array substrate after the first semiconductor layer and the second semiconductor layer are manufactured;

fig. 6B is a cross-sectional view of the array substrate after the first semiconductor layer and the second semiconductor layer are manufactured;

FIG. 7A is a schematic plan view of the array substrate after a second metal layer is formed;

FIG. 7B is a cross-sectional view of the array substrate after a second metal layer is formed;

FIG. 8A is a schematic plan view of the array substrate after the insulating layer is formed;

FIG. 8B is a cross-sectional view of the array substrate after the insulating layer is formed;

fig. 9A is a schematic plan view of the array substrate after fabrication of the pixel electrode;

fig. 9B is a cross-sectional view of the array substrate after fabrication of the pixel electrode;

FIG. 10A is a schematic plan view of the array substrate after fabricating the planarization layer;

fig. 10B is a cross-sectional view of the array substrate after the planarization layer is formed.

The designations in the figures mean:

100. an array substrate; 10. a substrate base plate; 20. an active element; 21. a first thin film transistor; 211. a first gate electrode; 212. a first semiconductor layer; 213. a first source electrode; 214. a first drain electrode; 22. a second thin film transistor; 221. a second gate electrode; 222. a second semiconductor layer; 223. a second source electrode; 224. a second drain electrode; 30. a pixel electrode; 40. a reflective layer; 51. an insulating layer; 511. a contact hole; 52. a planarization layer; 521. a through hole; 60. a common electrode; 200. an opposite substrate; 500. a display device.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, which are examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, are not to be construed as limiting the patent. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.

To illustrate the technical solution of the present invention, the following description is made with reference to the specific drawings and examples.

Referring to fig. 1, an embodiment of the invention provides a display device 500, which includes an array substrate 100, an opposite substrate 200 disposed opposite to the array substrate 100, and a liquid crystal (not shown) disposed between the array substrate 100 and the opposite substrate 200.

Referring to fig. 2, an embodiment of the invention provides an array substrate 100, including a substrate 10, a plurality of scan lines and a plurality of data lines (not shown) disposed on the substrate 10, wherein the plurality of scan lines and the plurality of data lines intersect to form a plurality of pixel regions; each pixel region is provided with an active device 20, a pixel electrode 30 electrically connected to the active device 20, and a reflective layer 40, and the reflective layer 40 is disposed above the pixel electrode 30 and electrically connected to the pixel electrode 30.

The material of the reflective layer 40 may be an opaque conductive material, such as a metal or an alloy material, for example: AL, Ag, ALCu, ALNd, etc., the reflective layer 40 layer serves to reflect external ambient light incident into the display device 500 to reflect the light to the opposite substrate 200, so that the display device 500 presents an image. The metal or alloy material needs to have a light reflecting ability, and the magnitude of the light reflecting ability determines the reflectivity and the reflection contrast of the reflective layer 40.

The array substrate 100 includes an active device 20, a pixel electrode 30 electrically connected to the active device 20, and a reflective layer 40 disposed above the pixel electrode 30 and electrically connected to the pixel electrode 30, wherein the reflective layer 40 can reflect light, and the reflective layer 40 and a common electrode on the opposite substrate 200 can drive liquid crystal together, so that the array substrate 100 has a reflective effect, and a display device 500 using the array substrate 100 does not need to have a backlight source, thereby saving power consumption, having the advantage of low power consumption, and facilitating to improve the endurance time of the display device 500.

The opposite substrate 200 may be a color filter substrate, and includes an array of color filters, a black matrix, a transparent material layer disposed above the color filters and the black matrix, and a common electrode disposed on the transparent material layer.

The principle of use of the display device 500 described above is as follows: when ambient light enters the display device 500, the reflective layer 40 on the array substrate 100 can reflect light to the opposite substrate 200, so that the light is filtered by the color filter and emitted, and the display device 500 displays an image.

The display device 500 can eliminate the backlight source, greatly reduce the power consumption, increase the endurance capacity of the battery, and is particularly suitable for application situations without high color gamut or dynamic display.

Referring to fig. 2 and fig. 3, in an embodiment, the active device 20 is a two-transistor design, the active device 20 includes a first thin film transistor 21 and a second thin film transistor 22, the first thin film transistor 21 includes a first gate 211, a first semiconductor layer 212, a first source 213 and a first drain 214, and the second thin film transistor 22 includes a second gate 221, a second semiconductor layer 222, a second source 223 and a second drain 224. In fig. 3, Ga is the first gate 211, and Gb is the second gate 221.

In each pixel region, the first gate electrode 211 is connected to a corresponding scan line, the first source electrode 213 is connected to a corresponding data line, the first drain electrode 214 is connected to a corresponding second source electrode 223, and the second drain electrode 224 is connected to a corresponding pixel electrode 30.

The array substrate 100 further includes a common electrode 60, the common electrode 60 is partially overlapped with the pixel electrode 30 to form a storage capacitor (Cst), and the pixel electrode 30, the common electrode (not shown) on the opposite substrate 200 and the liquid crystal form a liquid crystal capacitor (Clc).

By using the active element 20 designed with the two transistors, the display device 500 can realize a basic display function at a low refresh frequency, and the current consumption of the display device 500 itself is greatly reduced, which can be reduced from milliampere level to microampere level, and is reduced by at least 2 orders of magnitude.

In one embodiment, the array substrate 100 further includes a planarization layer 52 covering the pixel electrode 30, a through hole is formed on the planarization layer 52, and the pixel electrode 30 is electrically connected to the corresponding reflective layer 40 through the through hole. The planarization layer 52 can reduce the thickness difference caused by the existence of the active device 20, so as to planarize the array substrate 100; by providing the through hole on the planarization layer 52, the reflective layer 40 can be electrically connected to the pixel electrode 30 through the through hole 521, so that the reflective layer 40 and the pixel electrode 30 have the same voltage to drive the liquid crystal.

In one embodiment, the reflective layer 40 covers both the pixel electrode 30 and the active device 20. Thus, the reflective layer 40 can cover the entire pixel region, and has a larger area to achieve the effect of total reflection.

It is understood that the array substrate 100 further includes a gate insulating layer (not shown) disposed above the first gate electrode 211 and the second gate electrode 221, and an insulating layer 51 disposed between the pixel electrode 30 and the active device 20. Optionally, the second drain electrode 224 is electrically connected to the corresponding pixel electrode 30 through a contact hole formed in the insulating layer 51; it is understood that the pixel electrode 30 may also directly overlap the second drain electrode 224, so as to be electrically connected to the second drain electrode.

In other embodiments, the active device 20 may be a single thin film transistor.

In other embodiments, the reflective layer 40 may only cover a partial region of the pixel electrode 30, and the remaining region of the pixel electrode 30 may directly transmit light, so as to achieve the transflective effect, and also reduce the power consumption of the backlight source and prolong the endurance time of the display device 500.

Referring to fig. 2 to 4, an embodiment of the invention further provides a manufacturing method of an array substrate, including the following steps.

Step S10: a plurality of scan lines, a plurality of data lines, and a plurality of active devices 20 are formed on the base substrate 10.

The plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel regions, and the active devices 20 are respectively disposed in each pixel region and located at the intersections of the scan lines and the data lines.

In one embodiment, the active device 20 includes a first thin film transistor 21 and a second thin film transistor 22, and accordingly, the step S10 is to fabricate a plurality of scan lines, a plurality of data lines and a plurality of active devices 20 on the substrate 10, including the following steps.

First, referring to fig. 5A and 5B, a first metal layer is sputtered on the substrate 10 and exposed to form a plurality of scan lines GL, a plurality of first gate electrodes 211 and a plurality of second gate electrodes 221. Alternatively, the plurality of common electrodes 60 are formed at the same time using the first metal layer as the lower electrode of the storage capacitor (Cst).

Next, referring to fig. 6A and 6B, a gate insulating layer and a semiconductor layer are sequentially deposited on the substrate 10, and the semiconductor layer is patterned to form a first semiconductor layer 212 disposed above the first gate 211 and a second semiconductor layer 222 disposed above the second gate 221.

Next, referring to fig. 7A and 7B, a second metal layer is deposited on the substrate 10 and exposed to form a plurality of data lines DL, a plurality of first source electrodes 213, a plurality of first drain electrodes 214, a plurality of second source electrodes 223, and a plurality of second drain electrodes 224. The first source electrode 213 and the first drain electrode 214 are respectively positioned at both sides of the first semiconductor layer 212, the second source electrode 223 and the second drain electrode 224 are respectively positioned at both sides of the second semiconductor layer 222, and the first drain electrode 214 is electrically connected to the second source electrode 223.

Thus, the first gate 211, the first semiconductor layer 212, the first source 213 and the first drain 214 form a first thin film transistor 21, the second gate 221, the second semiconductor layer 222, the second source 223 and the second drain 224 form a second thin film transistor 22, and the first thin film transistor 21 and the second thin film transistor 22 together form the active device 20 (see fig. 2). In each pixel region, the first gate 211 is connected to a corresponding scan line, the first source 213 is connected to a corresponding data line, the first drain 214 is connected to a corresponding second source 223, and the second drain 224 is used for connecting to a subsequently formed pixel electrode.

Next, referring to fig. 8A and 8B, an insulating layer 51 is deposited over the second metal layer. Alternatively, a contact hole 511 is opened in the insulating layer 51 by etching, for connection of the second metal layer to the pixel electrode layer.

Alternatively, the gate insulating layer and the insulating layer 51 are etched away at a desired position by exposure etching for connection of the pixel electrode layer with the first metal layer or the second metal layer.

Step S20: a plurality of pixel electrodes 30 are formed on the base substrate 10, and each pixel electrode 30 is electrically connected to a corresponding active device 20.

Referring to fig. 7B, fig. 9A and fig. 9B, a pixel electrode 30 is formed on the insulating layer 51 by sputtering exposure, and the pixel electrode 30 is electrically connected to the corresponding second drain electrode 224. The pixel electrode 30 may be Indium Tin Oxide (ITO), but is not limited thereto, and may be other transparent electrodes.

Alternatively, the pixel electrode 30 is electrically connected to the second drain electrode 224 through the contact hole 511 on the insulating layer 51, and it is understood that the pixel electrode 30 may also directly overlap the second drain electrode 224.

Optionally, when the pixel electrode 30 is manufactured, a connection pattern of the first metal layer or the second metal layer, and a bonding pad (pad) pattern of the IC and the FPC are simultaneously manufactured.

In an embodiment, referring to fig. 10A and 10B, after the plurality of pixel electrodes 30 are fabricated on the substrate 10, the fabrication method further includes: a planarization layer 52 is deposited on the substrate 10, the planarization layer 52 covers the active device 20 and the pixel electrode 30, and a via 521 is opened on the planarization layer 52 to expose a portion of the pixel electrode 30.

Specifically, the planarization layer 52 may be formed by coating a transparent material to form a planarized surface, and exposed to light at a position corresponding to the pixel electrode 30 to form the via hole 521.

Step S30: a reflective layer 40 is formed on a side of the pixel electrode 30 facing away from the substrate 10, and the reflective layer 40 is electrically connected to the pixel electrode 30.

Specifically, the reflective layer 40 is formed by means of sputter exposure, and as shown in fig. 2, the reflective layer 40 is electrically connected to the pixel electrode 30 through the via hole 521 on the planarization layer 52.

In one embodiment, the reflective layer 40 covers both the pixel electrode 30 and the active device 20, i.e. the reflective layer 40 covers the whole pixel area to achieve the effect of total reflection.

In other embodiments, the active device 20 may be a single thin film transistor.

In other embodiments, the reflective layer 40 may only cover a partial region of the pixel electrode 30, and the remaining region of the pixel electrode 30 may directly transmit light, so as to achieve the transflective effect, and also reduce the power consumption of the backlight source and prolong the endurance time of the display device 500.

The array substrate 100 manufactured by the above manufacturing method includes the active device 20, the pixel electrode 30 and the reflective layer 40, wherein the reflective layer 40 is used for reflecting the external environment light entering the display device 500 to reflect the light to the opposite substrate 200, so that the display device 500 presents an image. The manufacturing method can manufacture the total reflection type array substrate 100, and is simple and low in cost.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.