阅读说明：本技术 半导体封装以及包括其的电子装置 (Semiconductor package and electronic device including the same ) 是由 李址华 李庚德 于 2021-05-07 设计创作，主要内容包括：提供了半导体封装和包括其的电子装置。该半导体封装包括：在基板上的半导体芯片；电压测量电路,配置为测量将输入到半导体芯片中的外部电压；以及热电模块,配置为将从半导体芯片释放的热量转变为辅助电力,并配置为将辅助电力施加到半导体芯片,热电模块与电压测量电路分开,其中电压测量电路配置为控制热电模块以响应于外部电压的变化而将辅助电力施加到半导体芯片。(Provided are a semiconductor package and an electronic device including the same. The semiconductor package includes: a semiconductor chip on the substrate; a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip; and a thermoelectric module configured to convert heat released from the semiconductor chip into auxiliary power and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in external voltage.)

1. A semiconductor package, comprising:

a semiconductor chip on the substrate;

a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip; and

a thermoelectric module configured to convert heat released from the semiconductor chip into auxiliary power and to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit,

wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage.

2. The semiconductor package of claim 1, wherein the thermoelectric module is on the semiconductor chip.

3. The semiconductor package of claim 1, wherein the thermoelectric module comprises a first thermoelectric module and a second thermoelectric module,

the first thermoelectric module is on the semiconductor chip, and

the second thermoelectric module is between the substrate and the semiconductor chip.

4. The semiconductor package of claim 1, wherein the thermoelectric module surrounds a sidewall of the semiconductor chip.

5. The semiconductor package according to claim 1, wherein the thermoelectric module comprises a first metal film, a second metal film, and a plurality of p-type semiconductors and a plurality of n-type semiconductors alternately arranged in a plan view,

one of the plurality of p-type semiconductors is connected to the first metal film, a first set temperature is supplied to the first metal film,

one of the plurality of n-type semiconductors is connected to the second metal film, a second set temperature is supplied to the second metal film, an

An operating current flows through the first metal film and the second metal film according to a difference between the first set temperature and the second set temperature to apply the auxiliary power to the semiconductor chip.

6. The semiconductor package of claim 1, further comprising:

a temperature control circuit configured to measure a set temperature provided to the semiconductor chip and configured to provide a current to the thermoelectric module,

the thermoelectric module and the semiconductor chip are connected to each other through a first transistor, an

The thermoelectric module and the temperature control circuit are connected to each other through a second transistor.

7. The semiconductor package of claim 6, wherein the thermoelectric module comprises a first metal film and a second metal film, the second metal film not being in contact with the first metal film,

a first set temperature is provided to the first metal film,

a second set temperature is provided to the second metal film,

the second set temperature is the set temperature provided to the semiconductor chip,

the temperature control circuit is configured to measure a temperature change between the first set temperature and the second set temperature, an

The voltage measurement circuit is configured to control the first transistor and the second transistor in response to the temperature change.

8. The semiconductor package of claim 7, wherein the voltage measurement circuit is configured to control to turn on the second transistor and input the current to the thermoelectric module when the temperature variation is above a target temperature variation.

9. The semiconductor package of claim 7, wherein when the temperature variation is below a target temperature variation,

the voltage measurement circuit is configured to turn on the first transistor, and the thermoelectric module is configured to apply the auxiliary power to the semiconductor chip.

10. A semiconductor package, comprising:

a semiconductor chip on the substrate;

a thermoelectric module configured to convert heat released from the semiconductor chip into auxiliary power and configured to apply the auxiliary power to the semiconductor chip;

a voltage measurement circuit configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a variation in an external voltage input to the semiconductor chip; and

a temperature control circuit configured to send a control signal to the voltage measurement circuit in response to a set temperature provided to the semiconductor chip and configured to provide a temperature control current to the thermoelectric module,

wherein the voltage measurement circuit is configured to control the temperature control current provided by the temperature control circuit to the thermoelectric module according to the control signal.

11. The semiconductor package according to claim 10, wherein the thermoelectric module comprises a plurality of P-type semiconductors, a plurality of n-type semiconductors, a first metal film, and a second metal film which are alternately arranged in a plan view,

a first voltage is applied to the p-type semiconductor on the first metal film among the plurality of p-type semiconductors,

a second voltage is applied to the n-type semiconductor on the second metal film among the plurality of n-type semiconductors,

heat generated from the semiconductor chip according to a difference between the first voltage and the second voltage is absorbed.

12. The semiconductor package of claim 10, wherein the thermoelectric module and the semiconductor chip are connected to each other through a first transistor,

the thermoelectric module and the temperature control circuit are connected to each other through a second transistor, an

The voltage measurement circuit is configured to operate the first transistor and the second transistor.

13. The semiconductor package according to claim 12, wherein when the external voltage is not applied, the first transistor is turned on, and the thermoelectric module inputs the auxiliary power into the semiconductor chip.

14. The semiconductor package of claim 12, wherein the thermoelectric module comprises a first metal film and a second metal film, the second metal film not being in contact with the first metal film,

a first set temperature is provided to the first metal film,

a second set temperature is provided to the second metal film,

the second set temperature is the set temperature provided to the semiconductor chip,

when the difference between the first set temperature and the second set temperature is changed above a target temperature, the second transistor is turned on and the temperature control current is input into the thermoelectric module.

15. The semiconductor package of claim 14, wherein the temperature control current is input into the thermoelectric module, and the thermoelectric module is configured to absorb heat generated in the semiconductor chip to cool the semiconductor chip.

16. An electronic device, comprising:

a first non-volatile memory configured to store first data;

a first thermoelectric module adjacent to the first non-volatile memory and configured to absorb heat released from the first non-volatile memory to adjust a first set temperature provided to the first non-volatile memory;

a first temperature control circuit configured to provide a first temperature control current to the first thermoelectric module in response to the first set temperature; and

a power management module configured to receive a control signal from the first temperature control circuit, configured to regulate the temperature control current, and configured to provide a first operating voltage to be input into the first non-volatile memory,

wherein the first thermoelectric module is configured to convert heat released from the first non-volatile memory into first auxiliary power, an

The power management module is configured to control the first thermoelectric module to apply the first auxiliary power to the first non-volatile memory in response to a change in the first operating voltage.

17. The electronic device of claim 16, wherein the power management module is configured to apply the first auxiliary power to the first non-volatile memory when the first operating voltage is not applied to the first non-volatile memory.

18. The electronic device of claim 16, wherein the power management module is in contact with the first non-volatile memory and is configured to absorb heat generated in the first non-volatile memory to cool the first non-volatile memory.

19. The electronic device of claim 16, further comprising:

a second non-volatile memory configured to store second data;

a second thermoelectric module adjacent to the second non-volatile memory, absorbing heat from the second non-volatile memory, and configured to adjust a second set temperature provided to the second non-volatile memory; and

a second temperature control circuit configured to provide a second temperature control current to the second thermoelectric module in response to the second set temperature,

wherein the power management module is configured to receive input of a control signal from the first temperature control circuit and to regulate the temperature control current.

20. The electronic device of claim 19, wherein the second thermoelectric module is configured to convert heat released from the second non-volatile memory to second auxiliary power, an

The power management module is configured to control the second auxiliary power and a second external voltage applied to the second non-volatile memory.

Technical Field

The present disclosure relates to a semiconductor package and an electronic device including the same.

Background

Recently, when operations such as data reading and writing are performed on a memory device, research on applying low power to perform the operations is actively being conducted. A situation in which a voltage is unstably supplied to a memory device (power collapse or sudden power off) is liable to occur when operating with low power, in which case data loss may occur, and a technique for reducing or preventing such a problem is required.

Further, when the memory device operates at high or low temperature, a defense code (defensive code) input rate increases due to a change in characteristics of the memory cell, a delay increases, and in order to lower the temperature at the time of high temperature operation, the controller may forcibly reduce the performance of the memory operation and reduce the operating efficiency of the memory device.

Disclosure of Invention

Aspects of the present disclosure provide a technique for controlling a storage device depending on a temperature of the storage device.

Aspects of the present disclosure provide a semiconductor package capable of maintaining reliability against a sudden drop of an external voltage.

Aspects of the present disclosure also provide a semiconductor package having improved operating efficiency through temperature control in the package.

Aspects of the present disclosure also provide an electronic device capable of maintaining reliability against a sudden drop of an external voltage.

Aspects of the present disclosure also provide an electronic device having improved operating efficiency through temperature control in a package.

However, aspects of the present disclosure are not limited to the aspects set forth herein. The foregoing and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by reference to the detailed description of the present disclosure set forth below.

A semiconductor package for achieving the above aspect includes: a semiconductor chip on the substrate; a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip; and a thermoelectric module configured to convert heat released from the semiconductor chip into auxiliary power and to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in external voltage.

A semiconductor package for achieving the above aspect includes: a semiconductor chip on the substrate; a thermoelectric module configured to convert heat released from the semiconductor chip into auxiliary power and configured to apply the auxiliary power to the semiconductor chip; a voltage measurement circuit configured to control the thermoelectric module to apply auxiliary power to the semiconductor chip in response to a variation in an external voltage to be input into the semiconductor chip; and a temperature control circuit configured to transmit a control signal to the voltage measurement circuit in response to a set temperature (temperature) supplied to the semiconductor chip and to supply a temperature control signal to the thermoelectric module, wherein the voltage measurement circuit is configured to control a current supplied to the thermoelectric module by the temperature control circuit according to the control signal.

An electronic device for implementing the above aspect includes: a first non-volatile memory configured to store first data; a first thermoelectric module adjacent to the first non-volatile memory and configured to absorb heat released from the first non-volatile memory to adjust a first set temperature provided to the first non-volatile memory; a first temperature control circuit configured to provide a first temperature control current to the first thermoelectric module in response to a first set temperature; and a power management module configured to receive a control signal from the first temperature control circuit, configured to adjust a temperature control current, and configured to provide a first operating voltage to be input into the first non-volatile memory, wherein the first thermoelectric module is configured to convert heat released from the first non-volatile memory into first auxiliary power, and the power management module is configured to control the first thermoelectric module to apply the first auxiliary power to the first non-volatile memory in response to a change in the first operating voltage.

Drawings

The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a block diagram illustrating a system including a storage device according to some example embodiments of the present disclosure;

FIG. 2 is an example block diagram illustrating the memory of FIG. 1;

fig. 3 is an example circuit diagram for illustrating a memory cell array in a memory device including a semiconductor package according to some example embodiments;

fig. 4 is an exemplary view for explaining a semiconductor package according to some example embodiments;

FIG. 5 is a perspective view of the thermoelectric module of FIG. 4, according to some example embodiments;

FIG. 6 is a perspective view of the thermoelectric module of FIG. 4 according to some other example embodiments;

FIG. 7 is a perspective view of the thermoelectric module of FIG. 4 according to some other example embodiments;

fig. 8 is a flowchart for explaining the operation of a semiconductor package according to some example embodiments;

fig. 9 is a diagram for explaining the operation of S110 and S111 of fig. 8;

fig. 10 is a diagram for explaining the operation of S120 and S121 of fig. 8;

fig. 11 is a diagram for explaining the operation of S120 and S130 of fig. 8;

fig. 12 to 14 are example views illustrating a semiconductor package according to some other example embodiments;

fig. 15 is an example plan view illustrating a semiconductor package according to some other embodiments;

fig. 16 is a view of the semiconductor package of fig. 15 taken along line a-a; and

fig. 17 is a block diagram illustrating a system including a storage device according to some other example embodiments.

Detailed Description

Hereinafter, example embodiments of the technical idea according to the present disclosure will be described with reference to the accompanying drawings. In the description of fig. 1 to 17, the same or substantially the same components are denoted by the same reference numerals, and a repetitive description of the components will not be provided.

Fig. 1 is a block diagram illustrating a system including a storage device according to some example embodiments of the present disclosure. FIG. 2 is an example block diagram illustrating the memory of FIG. 1.

Referring to fig. 1, a system 1 including a storage apparatus according to some example embodiments of the present disclosure may include a host 10 and a storage apparatus 20. Although the system 1 may include, for example, a flash-based data storage medium such as a memory card, a USB memory, and an SSD (solid state drive) or an electronic device including the data storage medium, and a network system, the example embodiments are not limited to these examples.

The host 10 may transmit a DATA operation request REQ and an address ADDR to the memory controller 100, and may transmit and receive DATA to and from the memory controller 100.

The memory device 20 may include a memory controller 100 and a memory 200.

The memory controller 100 may control the memory 200 in response to a request from the host 10. The memory controller 100 may read DATA stored in the memory 200, for example, in response to a DATA operation request REQ received from the host 10, and may control the memory 200 to write the DATA into the memory 200. The memory controller 100 may provide the address ADDR, the command CMD, and the control signal CTRL to the memory 200, and may control program, read, and erase operations of the memory 200. In addition, DATA for programming and read DATA may be transmitted and received between the memory controller 100 and the memory 200.

The memory 200 may output ready and busy signals RNB. The ready and busy signals RNB may indicate the state of the memory 200. When the memory 200 outputs, for example, a ready signal, the memory controller 100 may provide a command CMD to the memory 200. The memory controller 100 may not provide the command CMD, for example, when the memory 200 outputs a busy signal.

Although not shown, according to some example embodiments, memory controller 100 may also include a thermoelectric module 220, such as illustrated below in fig. 2, a temperature control circuit 230, and/or a voltage measurement circuit 240, to be adjacent to a data storage device included in memory controller 100.

Hereinafter, description will be provided with reference to fig. 2. Referring to fig. 1 and 2, the memory 200 may include a memory cell array 210, a thermoelectric module 220, a temperature control circuit 230, a voltage measurement circuit 240, control logic 250, a voltage generator 260, a row decoder 270, a page buffer circuit 280, and/or a data I/O circuit 290.

Although the memory 200 may include, for example, a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory, a resistance RAM (rram), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin-torque transfer magnetic RAM (spin STT-RAM), and the like, example embodiments are not limited to these examples.

The memory cell array 210 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells connected to a plurality of word lines WL and a plurality of bit lines BL.

The memory cell array 210 may be connected to the row decoder 270 through string selection lines SSL, a plurality of word lines WL, and/or ground selection lines GSL. In addition, the memory cell array 210 may be connected to the page buffer circuit 280 through a plurality of bit lines BL. In some example embodiments, the memory cell array 210 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In example embodiments, the memory cell array 210 may include a vertical memory cell string including a plurality of memory cells formed by being stacked on one another. The memory cell array 210 may be a two-dimensional memory cell array formed on a substrate in a two-dimensional structure (or a horizontal structure), without being limited thereto.

The memory cell array 210 will be described in detail with reference to fig. 3. The memory cell array 210 may include a plurality of memory cell strings NS11 to NS33 connected between bit lines BL1 to BL3 and a common source line CSL. Each of the plurality of memory cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, ·, MC8, and a ground selection transistor GST. Although fig. 3 shows that each of the plurality of memory cell strings NS11 through NS33 includes eight memory cells MC1 through MC8, the number and type thereof are not limited thereto.

The string selection transistors SST may be connected to corresponding string selection lines SSL. Each of the plurality of memory cells MC1, MC2, ·, MC8 may be connected to a corresponding word line WL1, WL2, ·, WL 8. The ground selection transistors GST may be connected to corresponding ground selection lines GSL1 through GSL 3. The string selection transistors SST may be connected to corresponding bit lines BL1 to BL3, and the ground selection transistors GST may be connected to a common source line CSL. Although fig. 3 illustrates the memory cell array 210 connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, the present disclosure is not limited thereto.

Referring again to fig. 1 and 2, the thermoelectric module 220 according to some example embodiments may be connected to the memory cell array 210 through a first transistor 241 and may be connected to the temperature control circuit 230 through a second transistor 243. Although the first transistor 241 is illustrated as an NMOS transistor and the second transistor 243 is illustrated as a PMOS transistor, they may be replaced with other types of transistors, switches, variable resistors, etc. as long as the current input to and output from the thermoelectric module 220 may be controlled, but example embodiments of the present disclosure are not limited to these examples.

The thermoelectric module 220 includes thermoelectric elements, and can absorb or release heat around the thermoelectric elements depending on the direction of temperature control current input through the peltier effect. Further, the thermoelectric element may generate an electric current due to a temperature change around the thermoelectric element by the seebeck effect, and may generate electricity by the generated electric current. The thermoelectric elements may include thermoelectric semiconductors that may include, for example, Bi-Te, Pb-Te, Fe-Si, Si-Ge, Mg-Si, Sn-Se, and the like. The detailed structure will be explained in fig. 5 to 7.

The thermoelectric module 220 according to some example embodiments may convert an ambient temperature change due to heat generated from the memory cell array 210 into auxiliary power by the seebeck effect. That is, it is possible to absorb heat generated from the memory cell array 210, input current into the memory cell array 210, and generate power in the memory cell array 210.

The thermoelectric module 220 according to some example embodiments may also input current into the memory cell array 210 to enhance power supply to the memory cell array 210 and increase heat generated from the memory cell array 210.

The thermoelectric module 220 according to some example embodiments may absorb heat around the memory cell array 210 via a temperature control current input from the temperature control circuit 230 by the peltier effect and cool the memory cell array 210.

The temperature control circuit 230 according to some example embodiments may be connected to the thermoelectric module 220 through a second transistor 243 and may be connected to the voltage measurement circuit 240.

The temperature control circuit 230 according to some example embodiments may measure the temperature provided to the memory cell array 210 and the temperature provided to the thermoelectric module 220. The control signal may be provided to the voltage measurement circuit 240 based on the measured temperature.

The temperature control circuit 230 according to some example embodiments may be used as a current source in the thermoelectric module 220 to input a temperature control current into the thermoelectric module 220. The thermoelectric module 220 may absorb heat generated by the memory cell array 210 according to an input temperature control current.

The voltage measurement circuit 240 according to some example embodiments is connected to the temperature control circuit 230, and may be connected to each of the first and second transistors 241 and 243 through each of the first and second inverters 242 and 244. According to some example embodiments, the voltage measurement circuit 240 may be connected to the first transistor 241 and the second transistor 243 without passing through the first inverter 242 and the second inverter 244.

The voltage measurement circuit 240 according to some example embodiments may measure the external voltage PWR input into the memory 200. Although the external voltage is input only to the voltage generator 260, it may be input in parallel to the configuration included in the memory 200. It is possible to detect the occurrence of a power dip or sudden power failure in the external voltage.

The voltage measurement circuit 240 according to some example embodiments may control the first transistor 241 and the second transistor 243 according to a control signal input from the temperature control circuit 230. The specific operation of the voltage measurement circuit 240 will be explained below in fig. 8 to 11.

The control logic 250 may generally control the memory 200 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100. Control logic 250 may control, for example, write operations, read operations, and erase operations of memory 200. The control logic 250 may output a ready signal and a busy signal RNB that represent the state of the memory 200.

The control logic 250 may provide a voltage control signal CTRL _ vol to the voltage generator 260. Control logic 250 may generate row addresses X-ADDR and column addresses Y-ADDR based on address signals ADDR. Control logic 250 may provide row addresses X-ADDR to row decoder 270 and may provide column addresses Y-ADDR to data I/O circuitry 290.

The voltage generator 260 may generate an operating voltage required to operate the memory 200 in response to the voltage control signal CTRL _ vol. The operating voltages may include, for example, but are not limited to, word line voltage VWL, program voltages, read voltages, verify voltages, erase voltages, and the like.

The row decoder 270 may be connected to the memory cell array 210 through string selection lines SSL, word lines WL, and ground selection lines GSL. The row decoder 270 may select the string selection line SSL, the word line WL, and the ground selection line GSL in response to the row address X-ADDR. The row decoder 270 may apply the operating voltage supplied from the voltage generator 260 to the selected and unselected string selection lines SSL, word lines WL, and ground selection lines GSL.

The page buffer circuit 280 may be connected to the memory cell array 210 through the plurality of bit lines BL. The page buffer circuit 280 may include a plurality of page buffers. The page buffer circuit 280 may temporarily store data to be written in a selected page at the time of a write operation. The page buffer circuit 280 may temporarily store data read from a selected page at the time of a read operation.

The data I/O circuit 290 may be connected to the page buffer circuit 280 through the data line DL. The DATA I/O circuit 290 may receive, for example, write DATA from the memory controller 100 at the time of a write operation, and may supply the write DATA to the page buffer circuit 280 based on the column address Y-ADDR supplied from the control logic 250. The DATA I/O circuit 290 may supply read DATA stored in, for example, the page buffer circuit 280 to the memory controller 100 based on the column address Y-ADDR supplied from the control logic 250 at the time of a read operation.

Fig. 4 is an exemplary diagram for illustrating a semiconductor package according to some example embodiments.

Referring to fig. 4, a semiconductor package 1000a according to some example embodiments may include first to third memory cell arrays 210_1 to 210_3, a thermoelectric module 220, a temperature control circuit 230, and/or a voltage measurement circuit 240. Although not shown, other configurations included in the memory 200 of fig. 2 may also be included in the semiconductor package 1000 a.

The first to third memory cell arrays 210_1 to 210_3, the thermoelectric module 220, the temperature control circuit 230, and/or the voltage measurement circuit 240 may be disposed on a single same substrate 201. A plurality of external connection terminals 202 may be formed under the substrate 201 to receive external electrical signals. The plurality of external connection terminals 202 may include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or aluminum (Al).

Each of the first to third memory cell arrays 210_1 to 210_3 according to some example embodiments may include a three-dimensional array structure, and may include a NAND flash memory, a vertical NAND flash memory (vertical NAND: VNAND), a NOR flash memory, a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a spin transfer torque random access memory (STT-RAM), and the like. In addition, the memory cell array according to some example embodiments may be referred to as a memory chip including a semiconductor device.

The thermoelectric module 220 may be disposed on the first to third memory chips 210_1 to 210_ 3. The detailed structure of the thermoelectric module 220 will be explained in fig. 5 to 7. The temperature control circuit 230 and the voltage measurement circuit 240 may be disposed on the same chip under the first to third memory chips 210_1 to 210_3, but may be disposed in the same package as the first to third memory chips 210_1 to 210_3 in an additional stack without being limited thereto, and the arrangement of fig. 4 related to the arrangement of the temperature control circuit 230 and the voltage measurement circuit 240 corresponds to an example.

The first to third memory chips 210_1 to 210_3, the thermoelectric module 220, the temperature control circuit 230, and/or the voltage measurement circuit 240 may be connected to each other through metal lines, and may be connected to the plurality of external connection terminals 202 through second metal lines.

Fig. 5 is a perspective view illustrating the thermoelectric module 220 of fig. 4 according to some example embodiments. Fig. 6 is a perspective view illustrating the thermoelectric module 220 of fig. 4 according to some other example embodiments. Fig. 7 is a perspective view illustrating the thermoelectric module 220 of fig. 4 according to some other example embodiments.

Referring to fig. 5, the pair of P-type and N-type semiconductors 223 and 224 (e.g., a pair of P-type and N-type semiconductors 223-1 and 224-2, and a pair of P-type and N-type semiconductors 223-2 and 224-1) arranged in the X direction constitute a single thermocouple, and a plurality of thermocouples are arranged in the Y direction and may be included in the module 220. By including a plurality of thermocouples, the thermoelectric module 220 may have improved heat exchange performance and capacity. The positions of the P-type semiconductors 223 and the N-type semiconductors 224 of the neighboring thermocouples arranged in the Y direction may be reversed, and thus, the P-type semiconductors 223 and the N-type semiconductors 224 may be alternately arranged along the Y direction. The P-type semiconductor 223 and the N-type semiconductor 224 forming one thermocouple may be bonded to each other through the first metal film 221. The P-type semiconductor 223 belonging to one of the thermocouples may be joined to the N-type semiconductor 224 belonging to another adjacent thermocouple through the second metal film 222.

A voltage is applied through the second metal film 222 bonded to the P-type semiconductor 223 of the first thermocouple and the second metal film 222 bonded to the N-type semiconductor 224 of the last thermocouple to generate a current. The movement of heat is caused by the current generated by the thermoelectric module 220 through the peltier effect. The direction of movement of the flowing heat may vary depending on the polarity of the applied voltage.

In contrast, when a first set temperature (providing temperature) is supplied to the first metal film 221 and a second set temperature is supplied to the second metal film 222, a current may be generated in the first metal film 221 and the second metal film 222 by the seebeck effect. The direction of the current may vary depending on a temperature comparison between the first set temperature and the second set temperature. Specifically, the second set temperature is the set temperature provided to the memory chip (i.e., memory cell array) 210. In some example embodiments, at least one of the first set temperature and the second set temperature reflects a set temperature provided to the memory chip.

Fig. 6 is a modified example of fig. 5. Differences from the thermoelectric module 220 shown in fig. 5 will be mainly described. Referring to fig. 6, the pair of P-type and N-type semiconductors 223 and 224 (e.g., a pair of P-type and N-type semiconductors 223-1 and 224-1, and a pair of P-type and N-type semiconductors 223-2 and 224-2) arranged in the Y direction constitute a single thermocouple, and a plurality of thermocouples may be arranged in the Y direction and included in the module 220. The positions of the P-type semiconductors 223 and the N-type semiconductors 224 of the neighboring thermocouples arranged in the X direction may be reversed, and thus, the P-type semiconductors 223 and the N-type semiconductors 224 may be alternately arranged along the Y direction. The X-direction and the Y-direction may be changed from each other.

Fig. 7 is a modified example of fig. 6. Differences from the thermoelectric module 220 shown in fig. 6 will be mainly described. Referring to fig. 7, as in the example embodiment of fig. 6, a pair of P-type and N-type semiconductors 223 and 224 arranged in the Y-direction form a single thermocouple, and a plurality of thermocouples may be arranged in the Y-direction and included in the thermoelectric module 220.

However, the P-type semiconductor 223 and the N-type semiconductor 224 extend in the Y direction, and may partially overlap with the first metal film 221 and the second metal film 222 from a planar view, and the first metal film 221 and the second metal film 222 may not overlap with each other in a plan view.

Fig. 8 is a flowchart for explaining the operation of a semiconductor package according to some example embodiments. Fig. 9 is a diagram for explaining the operation of S110 and S111 of fig. 8. Fig. 10 is a diagram for explaining the operations of S120 and S121 of fig. 8. Fig. 11 is a diagram for explaining the operation of S120 and S130 of fig. 8.

Referring to fig. 8 and 9, the voltage measurement circuit may measure whether the voltage input to the memory cell array is stably maintained (S110).

The thermoelectric module 220 supplies the auxiliary power to the memory cell array 210 (S111). When the voltage PWR is not stably maintained (power collapse or sudden power off), the voltage measurement circuit 240 may turn on the first transistor 241 and turn off the second transistor 243 through the first and second inverters 242 and 244.

The thermoelectric module 220 may convert heat absorbed from the memory cell array 210 into an auxiliary current I_AuxiliaryAnd an auxiliary current I is supplied through the first transistor 241_AuxiliaryInto the memory cell array 210 to provide auxiliary power.

Referring additionally to fig. 4 and 10, the temperature control circuit 230 checks whether a temperature variation between the first set temperature and the second set temperature is greater than a target temperature variation (S120).

When the voltage PWR is stably maintained, the temperature control circuit 230 may check whether a temperature variation Δ T between a first set temperature T1 provided to the first metal film 221 of the thermoelectric module 220 and a second set temperature T2 provided to the second metal film 222 is greater than a preset target temperature variation T_TGThe size of (2).

When the temperature variation between the first set temperature and the second set temperature is greater than the magnitude of the target temperature variation, the temperature control circuit may input a temperature control current into the thermoelectric module (S121). The temperature control circuit 230 may input the second control signal Sig 2 into the voltage measurement circuit 240 and perform control to turn off the first transistor 241 and turn on the second transistor 243.

The temperature control circuit 230 may input a temperature control current I into the thermoelectric module 220 through the second transistor 243. The thermoelectric module 220 may receive the temperature control current and absorb heat discharged from the memory cell array 210 to lower a set temperature provided to the memory cell array 210.

Referring additionally to fig. 4 and 11, when the temperature variation between the first set temperature and the second set temperature is less than the target temperature variation, the thermoelectric module supplies the auxiliary power to the memory cell array 210 (S130).

The temperature control circuit 230 may input a third control signal Sig 3 into the voltage measurement circuit 240 and perform control to turn on the first transistor 241 and turn off the second transistor 243.

The thermoelectric module 220 may convert heat absorbed from the memory cell array 210 into a current I and input the current into the memory cell array 210 to increase a set temperature provided to the memory cell array 210.

Fig. 12 to 14 are example views illustrating a semiconductor package according to some other example embodiments. Fig. 12 to 14 are modified examples of fig. 4. Differences from the thermoelectric module 220 shown in fig. 4 will be mainly described.

Referring to fig. 12, the thermoelectric module 220 may include a first thermoelectric module 220a and a second thermoelectric module 220 b. The first thermoelectric module 220a includes a first metal film 221a, a second metal film 222a, a P-type semiconductor 223a, and/or an N-type semiconductor 224a, as in the thermoelectric module 220 of fig. 4, and may be disposed on the first to third memory chips 210_1 to 210_ 3.

The second thermoelectric module 220b includes a first metal film 221b, a second metal film 222b, a P-type semiconductor 223b, and/or an N-type semiconductor 224b, as in the thermoelectric module 220 of fig. 4, and may be included between the first to third memory chips 210_1 to 210_3 and the substrate 201.

Referring to fig. 13, when compared to the thermoelectric module 220 of fig. 12, the thermoelectric module 220 of fig. 13 may further include a third thermoelectric module 220 c. The third thermoelectric module 220c may include a first metal film 221c, a second metal film 222c, a P-type semiconductor 223c, and an N-type semiconductor 224c, and may be disposed between the first to third memory chips 210_1 to 210_ 3. Although the third thermoelectric module 220c is illustrated as being disposed between the first and second memory chips 210_1 and 210_2, example embodiments are not limited thereto.

Referring to fig. 14, the semiconductor package 1000d may include a first stack Sa and a second stack Sb on the substrate 201. The first stack Sa may include the first to third memory chips 210_1 to 210_3, the first thermoelectric module 220a, the first temperature control circuit 230a, and/or the first voltage measurement circuit 240a, as in the semiconductor package 1000a of fig. 4.

The second stack Sb may include the fourth to sixth memory chips 210_4 to 210_6, the second thermoelectric module 220b, the second temperature control circuit 230b, and/or the second voltage measurement circuit 240b, as in the first stack Sa.

Each of the first and second thermoelectric modules 220a and 220b may be provided on each of the first to third memory chips 210_1 to 210_3 and the fourth to sixth memory chips 210_4 to 210_ 6.

The first stack Sa and the second stack Sb may be electrically connected to each other through the substrate 201, metal lines, or the like. Although the first stack Sa and the second stack Sb are divided into the first temperature control circuit 230a and the second temperature control circuit 230b for the temperature control circuit 230 and into the first voltage measurement circuit 240a and the second voltage measurement circuit 240b for the voltage measurement circuit 240, example embodiments are not limited thereto, and the first stack Sa and the second stack Sb may be implemented as each of a single temperature control circuit 230 and a single voltage measurement circuit 240 according to example embodiments.

Fig. 15 is an example plan view illustrating a semiconductor package according to some other example embodiments in a plan view. Fig. 16 is a view of the semiconductor package of fig. 15 taken along line a-a. Fig. 15 is a modified example of fig. 4. Differences from the thermoelectric module 220 shown in fig. 4 will be mainly described.

Referring to fig. 15 and 16, the thermoelectric module 220 may be provided in a form extending along an edge of the substrate 201. The thermoelectric module 220 includes P-type semiconductors 223 and N-type semiconductors 224 alternately arranged along an edge of the substrate 201, and may have a ring shape surrounding sidewalls of the first to third memory chips 210_1 to 210_ 3. Although the P-type semiconductor 223 and the N-type semiconductor 224 may be arranged in a line along the edge of the substrate 201, they may be arranged in a plurality of lines (e.g., two lines), without being limited thereto.

Further, the upper surface of the first metal film 221 and the upper surface of the third memory chip 210_3 may form the same plane, and the lower surface of the second metal film 222 and the substrate 201 may contact each other.

FIG. 17 is a block diagram illustrating a system including a storage device according to another example embodiment. Fig. 17 is a modified example of fig. 1 and 2.

The system 2 may include a host 10_1, a PMIC (power management integrated circuit) 10_2, a first storage device 20, and/or a second storage device 30.

The host 10_1 may transmit the DATA operation request REQ and the address ADDR to the first and second memory devices 20 and 30, and may transmit and receive DATA to and from the first and second memory devices 20 and 30, similarly to the first host 10 of fig. 1.

The PMIC 10_2 is connected to a power source (e.g., a battery) and may control the level of power distributed to each component of the system 2. Although the PMIC 10_2 is separated from the host 10_1, the PMIC 10_2 may be included in the host 10_1 without being limited thereto. For example, although not shown, the PMIC 10_2 may control the levels of voltages applied to an antenna, a modem, an RF circuit, a processor, a temperature sensor, the first storage device 20, and the second storage device 30 included in the system 2 in response to a control signal received from a Power Management Unit (PMU).

The PMIC 10_2 may control and measure a first external voltage and a second external voltage, which are input to the first memory cell array 210 and the second memory cell array 310, respectively.

PMIC 10_2 may control circuit 230 and second temperature according to the slaveThe control signal input from the two temperature control circuit 330 controls each of the current to be input to the first and second thermoelectric modules 220 and 320 and the current output from the first and second thermoelectric modules 220 and 320. The PMIC 10_2 may adjust first and second auxiliary currents I output from the first thermoelectric module 220 and the second thermoelectric module 320_AuxiliaryTo control the auxiliary power applied to each of the first and second memory cell arrays 210 and 310.

Each of the first and second storage devices 20 and 30 may include first and second memory cell arrays 210 and 310, first and second thermoelectric modules 220 and 320, and/or first and second temperature control circuits 230 and 330, as in the storage device 20 of fig. 1 and 2.

Unlike the memory device 20 of fig. 1 and 2, the first and second memory devices 20 and 30 do not include a voltage measurement circuit, but rather, the PMIC 10_2 may function as the voltage measurement circuit of fig. 1 and 2.

A system according to some example embodiments of the present disclosure may stably provide a voltage (e.g., power). By utilizing the seebeck effect of the thermoelectric module 220 according to example embodiments, when a certain level of power is not smooth, auxiliary power may be provided to the memory cell array 210 to enhance the reliability of the storage device 20.

The system according to some example embodiments of the present disclosure may utilize the peltier effect of the thermoelectric module 220 to reduce temperature variation in the memory cell array 210 and reduce latency of the storage device 20, thereby improving performance.

Further, when the temperature variation is small, current is additionally supplied to the storage device 20 using the seebeck effect of the thermoelectric module 220, which can effectively utilize the low power consumption effect.

At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred exemplary embodiments without substantially departing from the principles of the present disclosure. Accordingly, the disclosed preferred example embodiments of the present disclosure are used in a generic and descriptive sense only and not for purposes of limitation.

This application claims priority from korean patent application No. 10-2020-0055194, filed in korean intellectual property office on 8.5.2020 and incorporated herein by reference in its entirety.