阅读说明：本技术 一种集成沟槽和体平面栅的SiC MOSFET器件 (SiC MOSFET device integrating groove and body plane gate ) 是由 陈伟中 许峰 秦海峰 王玉婵 于 2021-08-12 设计创作，主要内容包括：本发明涉及一种集成沟槽和体平面栅的SiC MOSFET器件,属于半导体技术领域。该MOSFET是在传统沟槽栅的基础上,在沟槽栅底部引入体平面栅结构。该体平面栅由源金属﹑栅绝缘介质层﹑栅底部N+源﹑栅底部P电场屏蔽区以及栅底部沟道区组成,且栅底部N+源﹑栅底部P电场屏蔽区与源金属短接。该体平面栅不但引入新的沟道,且在P电场屏蔽区/N-漂移区之间集成了新PN结型二极管。与传统沟槽型SiC MOSFET相比,槽栅底部峰值电场下降了75.3％；栅漏电荷下降了91.5％；开启损耗在1MHZ频率下降了66.6％；关断损耗下降了78.0％。(The invention relates to a SiC MOSFET device integrating a groove and a body plane gate, belonging to the technical field of semiconductors. The MOSFET is characterized in that a body plane gate structure is introduced to the bottom of a trench gate on the basis of a traditional trench gate. The body plane gate consists of source metal, a gate insulating dielectric layer, a gate bottom N + source, a gate bottom P electric field shielding region and a gate bottom channel region, wherein the gate bottom N + source and the gate bottom P electric field shielding region are in short circuit with the source metal. The body plane gate not only introduces a new channel, but also integrates a new PN junction diode between the P electric field shielding region/the N-drift region. Compared with the traditional groove type SiC MOSFET, the peak electric field at the bottom of the groove gate is reduced by 75.3%; the grid leakage charge is reduced by 91.5%; the turn-on loss is reduced by 66.6% at a frequency of 1 MHz; the turn-off loss decreased by 78.0%.)

1. A SiCMOS MOSFET device integrating a trench and a body plane gate, comprising: the device structure is symmetrical left and right;

the transistor comprises a drain metal contact region (1), an N + substrate (2), an N-drift region (3), a P-body region (4), a P + source region (5), an N + source region (6), P + polycrystalline silicon (10), a current extension region (14) and a second drift region (15); the key structure body plane gate comprises a source metal (7), an insulating dielectric layer (8), a gate bottom channel region (11), a gate bottom N + source region (12) and a gate bottom P electric field shielding region (13);

the drain electrode metal contact region (1) is positioned on the lower surface of the N + substrate (2);

the N + substrate layer (2) is respectively positioned on the lower surface of the N-drift region (3) and the upper surface of the cathode metal contact region (1);

the N-drift region (3) is positioned on the lower surface of the P-body region (4) and the lower surface of the current expansion region (14) and is also positioned on the upper surface of the N + substrate layer (2);

the P-body region (4) is respectively positioned on the upper surface of the second drift region (15) and the lower surfaces of the P + source region (6) and the N + source region (7), and the side surface of the P-body region (5) is also contacted with the outer side surface of the insulating medium layer (8);

the P + source region (5) is positioned on the upper surface of the P-body region (4), the upper surface of the P + source region (5) is in contact with a source metal (7), and the side surface of the P + source region (5) is in contact with the N + source region (6);

the N + source region (6) is positioned on the upper surface of the P-body region (5), the upper surface of the N + source region (6) is in contact with a source metal (7), and the side surface of the N + source region (6) is in contact with the P + source region (5);

the source metal (7) is positioned on the upper surfaces of the P + source region (5) and the N + source region (6) and is positioned on the upper surfaces of the N + source region (12) at the bottom of the gate and the P electric field shielding region (13) at the bottom of the gate, the P + source region (5), the N + source region (6), the N + source region (12) at the bottom of the gate and the P electric field shielding region (13) at the bottom of the gate are connected through the source metal (7), and the insulating dielectric layer (8) is divided into two parts which are symmetrical left and right;

the insulating medium layer (8) is positioned above the gate bottom channel region (11), the gate bottom N + source region (12) and the contact current expansion region (14), the outer side of the insulating medium layer (8) is in contact with the P-body region (4), the N + source region (6), the source metal (7) and the second drift region (15), and the insulating medium layer (8) divides the P + polycrystalline silicon (10) from other regions;

the P + polysilicon (10) is completely surrounded by the insulating medium layer (8);

the gate bottom channel region (11) is positioned above the gate bottom P electric field shielding region (13) and is positioned below the insulating dielectric layer (8), the inner side of the gate bottom N + source region (12) is contacted with the current expansion region (14), and the outer side of the gate bottom N + source region is contacted with the current expansion region (14);

the gate bottom N + source region (12) is in contact with the source metal (7), the gate bottom channel region (11), the gate bottom P electric field shielding region (13) and the insulating medium layer (8);

the grid bottom P electric field shielding region (13) is in contact with the source (7), the grid bottom channel region (11), the grid bottom N + source region (12) and the insulating medium layer (8);

the current expansion region (14) is positioned on the upper surface of the N-drift region (3) and the lower surface of the second drift region (15), and meanwhile, the current expansion region (14) is also contacted with the insulating medium layer (8), the grid bottom channel region (11) and the outer side surface of the grid bottom P electric field shielding region (13);

the second drift region (15) is located on the upper surface of the current expansion region (14) and on the lower surface of the P-body region (4), and meanwhile, the side surface of the second drift region (15) is also in contact with the outer side surface of the insulating medium layer (8).

2. The integrated trench and body plane gate SiCMOSFET device of claim 1 wherein: the N + substrate (2) is doped with N-type impurities with the concentration of 2 x 10¹⁹cm^-3The N-drift region (3) is doped with N-type impurities at a concentration of 3X 10¹⁵cm^-3The P-body region (4) is doped with P-type impurities at a concentration of 2X 10¹⁷cm^-3The P + source region (5) is doped with P-type impurity at a concentration of 2X 10¹⁹cm^-3The N + source region (6) is doped with N type impurity at a concentration of 2X 10¹⁹cm^-3N-polysilicon (9) doped with N-type impurity at a concentration of 5X 10¹⁷cm^-3P + polysilicon (10) doped with P-type impurity at a concentration of 2X 10¹⁹cm^-3。

3. The integrated trench and body plane gate SiCMOSFET device of claim 1 wherein: the drain electrode metal contact region (1) is made of Al, Au or Pt.

4. The integrated trench and body plane gate SiCMOSFET device of claim 1 wherein: the source metal (7) is made of Al, Au or Pt.

5. The integrated trench and body plane gate SiCMOSFET device of claim 1 wherein: the material of the grid contact metal (11) is Al, Au or Pt.

6. The integrated trench and body plane gate SiCMOSFET device of claim 1 wherein: the insulating medium layer (8) can use SiO₂、SiN、Al₂O₃、AlN、MgO、Ga₂O₃、AlHfO_xAnd HfSiON, or a combination of several of them.

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a SiC MOSFET device integrating a groove and a body plane gate.

Background

SiC (silicon carbide) is a compound semiconductor material composed of silicon (Si) and carbon (C). SiC is considered to be a material for manufacturing power devices exceeding the Si limit, because it has not only the advantages that the dielectric breakdown field strength is 10 times that of Si and the band gap is 3 times that of Si, but also that necessary P-type and N-type control can be achieved in a wide range at the time of device manufacturing. Since SiC materials can be used for high-voltage applications in majority carrier devices (schottky barrier diodes and MOSFETs) having a fast device structure, three characteristics of "high withstand voltage", "low on resistance", and "high frequency" can be achieved at the same time. The drift layer resistance of the SiC device is smaller than that of the Si device, and high withstand voltage and low on-resistance can be simultaneously achieved with a MOSFET having a fast device structural feature without using conductivity modulation.

The power MOSFET is a voltage control type power device, has the characteristics of simple gate drive circuit, short switching time, high power density and high conversion efficiency, and is widely applied to various power electronic systems. In principle, the MOSFET does not generate a tail current, and when the MOSFET is used in place of an IGBT, a large reduction in switching loss and a reduction in size of a heat sink can be achieved.

In the internal structure of the MOS tube, the grid is actually separated from the drain and the source by an insulating layer of silicon dioxide, which is equivalent to the existence of a capacitor. When the driving circuit controls the device, a charging and discharging process of the parasitic capacitor exists, the switching speed of the device is greatly reduced, meanwhile, the power loss and the driving power in the switching process are increased, and the phenomenon is more obvious under the high-frequency working condition. The silicon carbide trench MOSFET structure also has a very important problem, that is, in the device blocking state, the electric field strength of the oxide layer at the bottom of the trench MOS is very high, about 2.5 times of the electric field strength of the peak pn junction thereof, and the electric field at the corner of the bottom of the trench is more concentrated therein due to the two-dimensional effect, and the electric field strength is higher. This makes the gate oxide at the trench gate corners of a silicon carbide trench MOSFET device more susceptible to breakdown first, causing a reduction in the reliability of the device.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a SiC MOSFET device integrating a trench and a body plane gate.

In order to achieve the purpose, the invention provides the following technical scheme:

a SiCMOS device integrating a groove and a body plane gate has a bilaterally symmetrical structure; the transistor comprises a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, P + polysilicon 10, a current extension region 14 and a second drift region 15; the key structure body plane gate comprises a source metal 7, an insulating dielectric layer 8, a gate bottom channel region 11, a gate bottom N + source region 12 and a gate bottom P electric field shielding region 13;

the drain metal contact region 1 is positioned on the lower surface of the N + substrate 2;

the N + substrate layer 2 is respectively positioned on the lower surface of the N-drift region 3 and the upper surface of the cathode metal contact region 1;

the N-drift region 3 is positioned on the lower surface of the P-body region 4 and the lower surface of the current expansion region 14 and is also positioned on the upper surface of the N + substrate layer 2;

the P-body region 4 is respectively positioned on the upper surface of the second drift region 15 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8;

the P + source region 5 is positioned on the upper surface of the P-body region 4, the upper surface of the P + source region 5 is contacted with a source metal 7, and the side surface of the P + source region 5 is contacted with the N + source region 6;

the N + source region 6 is positioned on the upper surface of the P-body region 5, the upper surface of the N + source region 6 is in contact with the source metal 7, and the side surface of the N + source region 6 is in contact with the P + source region 5;

the source metal 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6, and is positioned on the upper surfaces of the gate bottom N + source region 12 and the gate bottom P electric field shielding region 13, the P + source region 5, the N + source region 6, the gate bottom N + source region 12 and the gate bottom P electric field shielding region 13 are connected by the source metal 7, and the insulating medium layer 8 is divided into two parts which are symmetrical left and right;

the insulating medium layer 8 is positioned above the gate bottom channel region 11, the gate bottom N + source region 12 and the contact current expansion region 14, the outer side of the insulating medium layer 8 is in contact with the P-body region 4, the N + source region 6, the source metal 7 and the second drift region 15, and the insulating medium layer 8 divides the P + polycrystalline silicon 10 from other regions;

the P + polysilicon 10 is completely surrounded by the insulating medium layer 8;

the gate bottom channel region 11 is positioned above the gate bottom P electric field shielding region 13 and below the insulating medium layer 8, the inner side of the gate bottom P electric field shielding region is in contact with the gate bottom N + source region 12, and the outer side of the gate bottom P electric field shielding region is in contact with the current expansion region 14;

the gate bottom N + source region 12 is in contact with the source metal 7, the gate bottom channel region 11, the gate bottom P electric field shielding region 13 and the insulating medium layer 8;

the gate bottom P electric field shielding region 13 is in contact with the source metal 7, the gate bottom channel region 11, the gate bottom N + source region 12 and the insulating medium layer 8;

the current expansion region 14 is positioned on the upper surface of the N-drift region 3 and the lower surface of the second drift region 15, and meanwhile, the current expansion region 14 is also contacted with the outer side surfaces of the insulating medium layer 8, the gate bottom channel region 11 and the gate bottom P electric field shielding region 13;

the second drift region 15 is located on the upper surface of the current extension region 14 and on the lower surface of the P-body region 4, and the side surface of the second drift region 15 is also in contact with the outer side surface of the insulating medium layer 8.

Optionally, the N + substrate 2 is doped with N-type impurities with a concentration of 2 × 10¹⁹cm^-3The N-drift region 3 is doped with N-type impurity at a concentration of 3X 10¹⁵cm^-3The P-body region 4 is doped with P-type impurities at a concentration of 2X 10¹⁷cm^-3The P + source region 5 is doped with P-type impurity at a concentration of 2 × 10¹⁹cm^-3The N + source region 6 is doped with N-type impurity with a concentration of 2 × 10¹⁹cm^-3N-polysilicon 9 doped with N-type impurity at a concentration of 5 × 10¹⁷cm^-3P + polysilicon 10 doped with P-type impurity at a concentration of 2 × 10¹⁹cm^-3。

Optionally, the material of the drain metal contact region 1 is Al, Au, or Pt.

Optionally, the source metal 7 is made of Al, Au or Pt.

Optionally, the gate contact metal 11 is made of Al, Au, or Pt.

Optionally, the insulating dielectric layer 8 can be SiO₂、SiN、Al₂O₃、AlN、MgO、Ga₂O₃、AlHfO_xAnd in HfSiONOne or a combination of several of them.

The invention has the beneficial effects that: the SiC MOSFET device integrating the trench gate and the body plane gate provided by the invention changes the parasitic capacitance coupling structure of the device, thereby reducing the gate charge of the device and achieving the purpose of improving the switching performance of the device.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a conventional trench-gate MOSFET structure;

FIG. 2 is a schematic diagram of the dimensions of a conventional trench-gate MOSFET embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an improved MOSFET device (SiC MOSFET device integrating a trench gate and a bulk-plane gate) provided by the present invention;

FIG. 4 is a schematic size diagram of an embodiment of an improved MOSFET device (SiC MOSFET device integrating a trench gate and a bulk-plane gate) provided by the present invention;

FIG. 5 shows T-300K, V_gOutput characteristic curves of a conventional trench gate MOSFET and a modified MOSFET (a SiC MOSFET device integrating a trench gate and a body plane gate) when the gate voltage is 15V;

FIG. 6 shows T-300K, V_gThe blocking characteristic curves of a conventional trench gate MOSFET and a modified MOSFET (SiC MOSFET device integrating a trench gate and a body plane gate) when (gate voltage) is 0V;

FIG. 7 shows T-300K, V_gConventional trench gate MOSFET when (gate voltage) is 0V, at V_d(drain voltage) 800VThe potential profile of (a).

FIG. 8 shows T-300K, V_gImproved MOSFET (integrated trench gate and bulk planar gate SiC MOSFET device) at 0V (gate voltage)_dPotential profile at (drain voltage) 800V;

FIG. 9 shows T-300K, V_gParasitic diode I-V characteristic curves of conventional trench gate MOSFETs, modified MOSFETs (SiC MOSFET devices integrating trench gate and bulk planar gate) when (gate voltage) is 0V;

FIG. 10 shows T-300K, V_g(gate voltage) ═ 0V, V_dThe electric field intensity is 5nm below the grid electrode of the traditional trench gate MOSFET and the improved MOSFET (SiC MOSFET device integrating the trench gate and the body plane gate) when the drain voltage is 800V.

Fig. 11 is a gate charge characteristic curve for a conventional trench-gate MOSFET, a modified MOSFET (SiC MOSFET device integrating a trench-gate and a body-plane gate) at T-300K;

fig. 12 is a graph of gate charge time for a conventional trench-gate MOSFET, a modified MOSFET (SiC MOSFET device integrating trench-gate and bulk-plane gate) at 300K;

FIG. 13 shows T-300K, V_g(gate voltage) is 0V feedback capacitance curve of conventional trench gate MOSFET, modified MOSFET (SiC MOSFET device integrating trench gate and bulk planar gate);

fig. 14 is a bar graph of switching loss for a conventional trench-gate MOSFET, a modified MOSFET (SiC MOSFET device integrating trench-gate and bulk-plane gate) with T-300K.

Reference numerals: the transistor comprises a 1-drain metal contact region, a 2-N + substrate, a 3-N-drift region, a 4-P-body region, a 5-P + source region, a 6-N + source region, a 7-source metal, an 8-insulating dielectric layer, 10-P + polycrystalline silicon, an 11-grid bottom channel region, a 12-grid bottom N + source region, a 13-grid bottom P + source region, a 14-current expansion region and a 15-second drift region.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Example 1:

as shown in fig. 1 and fig. 2, the trench gate MOSFET of the present invention comprises a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source metal 7, an insulating dielectric layer 8, P + polysilicon 10, and a gate metal contact region 11.

The drain metal contact region 1 is located on the lower surface of the N + substrate layer 2.

The N + substrate layer 2 is positioned on the lower surface of the N-drift region 3 and the upper surface of the drain electrode metal contact region 1; length in horizontal direction of 4 μm and vertical directionThe length in the direction is 3 μm; doping N-type impurity with concentration of 2 × 10¹⁹cm^-3。

The N-drift region 3 is positioned on the lower surface of the P-body region 4, the lower surface and the outer lower surface of the insulating medium layer 8 and is also positioned on the upper surface of the N + high-concentration substrate layer 2; the length of the bottom of the N-drift region 3 in the horizontal direction is 4 micrometers, the distance between the bottom of the N-drift region 3 and the insulating medium layer 8 in the vertical direction is 12 micrometers, and the distance between the bottom of the N-drift region 3 and the P-body region 4 in the vertical direction is 12.4 micrometers; doping N-type impurity with concentration of 5 × 10¹⁵cm^-3。

The P-body region 4 is respectively positioned on the upper surface of the N-drift region 3 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8; the length of the P-body region 4 in the horizontal direction is 1 μm, and the length in the vertical direction is 0.5 μm; the P-body region 4 is doped with P-type impurity at a concentration of 2X 10¹⁷cm^-3。

The P + source region 5 is positioned on the upper surface of the P-body region 4, the upper surface of the P + source region 5 is contacted with a source metal 7, and the side surface of the P + source region 5 is contacted with the N + source region 6; the length of the P + source region 5 in the horizontal direction is 0.5 μm, and the length of the P + source region in the vertical direction is 0.3 μm; the P + source region 5 is doped with P type impurity with concentration of 2 × 10¹⁹cm^-3。

The N + source region 6 is positioned on the upper surface of the P-body region 5, the upper surface of the N + source region 6 is contacted with the source metal 7, and the side surface of the N + source region 6 is contacted with the P + source region 5; the length of the N + source region 5 in the horizontal direction is 0.5 μm, and the length of the N + source region in the vertical direction is 0.3 μm; the N + source region 6 is doped with N-type impurities with a concentration of 2 x 10¹⁹cm^-3。

The source metal 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6;

the insulating medium layer 8 is positioned above the N & lt- & gt drift region 3, is simultaneously contacted with the lower surface and the outer side surface of the P & lt + & gt polycrystalline silicon 10, and has the thickness of 0.05 mu m.

The P + polysilicon 10 is positioned between the insulating medium layers 8 and is completely surrounded by the insulating medium layers 8; the length of the P + polysilicon 10 in the horizontal direction is 3.9 μm, the length of the P + polysilicon 10 in the vertical direction is 1.45 μm, and the concentration of the P-type impurity doped in the P + polysilicon 10 is 2 x 10¹⁹cm^-3。

The gate metal contact region 11 is located on the upper surface of the P + polysilicon 10.

Example 2:

as shown in fig. 3 and 4, the present invention relates to a SiC MOSFET device structure of an improved SiC MOSFET device integrating a trench gate and a body plane gate, the device includes a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source metal 7, an insulating dielectric layer 8, a P + polysilicon 10, a gate metal contact region 10, a gate bottom channel region 11, a gate bottom N + source region 12, a gate bottom P electric field shielding region 13, a current spreading region 14, and a second drift region 15.

The drain metal contact region 1 is located on the lower surface of the N + substrate 2.

The N + substrate layer 2 is respectively positioned on the lower surface of the N-drift region 3 and the upper surface of the cathode metal contact region 1; the length in the horizontal direction is 4 μm, and the length in the vertical direction is 3 μm; doping N-type impurity with concentration of 2 × 10¹⁹cm-3。

The N-drift region 3 is positioned on the lower surface of the current expansion region 14, the lower surface and the outer lower surface of the insulating medium layer 8 and is also positioned on the upper surface of the N + substrate layer 2; the length of the bottom of the N-drift region 3 in the horizontal direction is 4 microns, and the length of the bottom of the N-drift region 3 in the vertical direction with the insulating medium layer 8 is 12 microns.

The P-body region 4 is respectively positioned on the upper surface of the second drift region 15 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8; the length of the P-body region 4 in the horizontal direction is 1 μm, and the length in the vertical direction is 0.5 μm; the P-body region 4 is doped with P-type impurity at a concentration of 2X 10¹⁷cm^-3。

The P + source region 5 is positioned on the upper surface of the P-body region 4, the upper surface of the P + source region 5 is contacted with a source metal 7, and the side surface of the P + source region 5 is contacted with the N + source region 6; the length of the P + source region 5 in the horizontal direction is 0.5 μm, and the length of the P + source region in the vertical direction is 0.3 μm; the P + source region 5 is doped with P type impurity with concentration of 2 × 10¹⁹cm^-3。

The N + source region 6 is positioned on the upper surface of the P-body region 5, the upper surface of the N + source region 6 is contacted with the source metal 7, and the side surface of the N + source region 6 is contacted with the P + source region 5; the length of the N + source region 5 in the horizontal direction is 0.5 μm, and the length of the N + source region in the vertical direction is 0.3 μm; n + source region 5 doped with N type impurity at a concentration of 2X 10¹⁹cm^-3。

The source metal 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6, and is positioned on the upper surfaces of the gate bottom N + source region 12 and the gate bottom P electric field shielding region 13, the P + source region 5, the N + source region 6, the gate bottom N + source region 12 and the gate bottom P electric field shielding region 13 are connected by the source metal 7, and the insulating medium layer 8 is divided into two parts which are symmetrical left and right;

the insulating medium layer 8 is positioned above the N-drift region 3, the outer side of the insulating medium layer 8 is in contact with the P-body region 4, the N + source region 6, the source metal 7, the grid bottom channel region 11, the grid bottom N + source region 12, the current expansion region 14 and the second drift region 15, and the insulating medium layer 8 divides the P + polycrystalline silicon 10 from other regions; the thickness of the side wall of the insulating medium layer 8 is 0.05 μm, and the thickness of the insulating medium layer 8 above the channel region 11 at the bottom of the gate is 0.02 μm.

The P + polysilicon 10 is completely surrounded by the insulating medium layer 8; the length of the P + polysilicon 10 in the horizontal direction is 0.65 μm, the length in the vertical direction is 1 μm, and the concentration of the P-type impurity doped in the P + polysilicon 10 is 2 x 10¹⁹cm^-3。

The outer side of the gate bottom channel region 11 is positioned above the N-drift region 3 and below the insulating medium layer 8, the inner side of the gate bottom channel region is in contact with the gate bottom N + source region 12 and the gate bottom P electric field shielding region 13, and the outer side of the gate bottom channel region is in contact with the current expansion region 14; the maximum horizontal length of the channel region 11 at the bottom of the gate is 1.8 μm, the maximum vertical length is 0.6 μm, and the concentration of doped P-type impurity is 5 × 10¹⁷cm^-3。

The gate bottom N + source region 12 is in contact with the gate bottom channel region 11, the gate bottom P electric field shielding region 13 and the insulating medium layer 8; the length of the gate bottom N + source region 12 in the horizontal direction is 0.2 μm, and the length in the vertical direction is 0.2 μm; n + source region 5 doped with N type impurity at a concentration of 2X 10¹⁹cm^-3。

The grid bottom P electric field shielding region 13 is contacted with the grid bottom channel region 11, the grid bottom N + source region 12 and the insulating medium layer 8; the length of the P electric field shielding region 13 at the bottom of the grid in the horizontal direction is 0.2 mu m, and the length of the P electric field shielding region in the vertical direction is 0.2 mu m; the P + source region 5 is doped with P type impurity with concentration of 2 × 10¹⁹cm^-3。

The current expansion region 14 is positioned on the upper surface of the N-drift region 3 and the lower surface of the second drift region 15, and the side surface of the current expansion region 14 is also contacted with the outer side surface of the insulating medium layer 8; current spreading region14 the length in the horizontal direction is 1.05 μm, and the length in the vertical direction is 0.6 μm; n + source region 5 doped with N type impurity at a concentration of 5 × 10¹⁶cm^-3。

The second drift region 15 is positioned on the upper surface of the current expansion region 14 and on the lower surface of the P-body region 4, and the side surface of the second drift region 15 is also contacted with the outer side surface of the insulating medium layer 8; the length of the second drift region 15 in the horizontal direction is 1 μm, and the length in the vertical direction is 0.6 μm; n + source region 5 doped with N type impurity at a concentration of 5 × 10¹⁵cm^-3。

FIG. 5 shows T-300K, V_gAnd (gate voltage) is 15V, and the output characteristic curve of the conventional trench gate MOSFET and the improved MOSFET is obtained. The drain current of the improved MOSFET is smaller than that of the traditional trench gate MOSFET under the same drain voltage. This is because the presence of the gate bottom channel region 11 and the gate bottom P electric field shielding region 13 introduces a new JFET resistance region, so that the on-resistance increases.

FIG. 6 shows T-300K, V_gThe blocking characteristic curve of the traditional trench gate MOSFET and the improved MOSFET when the gate voltage is 0V. The blocking voltage of the improved MOSFET is 1404V, the blocking voltage of the traditional trench gate MOSFET is 1480V, and the blocking voltage is reduced by 3%.

Fig. 7 and 8 show T-300K, V, respectively_gPotential distribution diagram of avalanche breakdown of the conventional trench gate MOSFET and the improved MOSFET when the gate voltage is 0V. Due to the introduction of the P-type area at the bottom of the grid, the improved MOSFET is more uniform in potential distribution at the bottom of the grid compared with the traditional trench grid MOSFET.

FIG. 9 shows T-300K, V_gAnd the parasitic diode I-V characteristic curve of the traditional trench gate MOSFET and the improved MOSFET when the grid voltage is 0V. The drain voltage is added to-3V from 0V, the turn-on voltage of a body diode of the traditional trench gate MOSFET is-2.7V, and the improved MOSFET can be turned on when the body plane gate channel is-2.1V. The body plane gate channel introduced by the improved MOSFET structure is started earlier than the original body diode, so that the starting of the original body diode is inhibited.

FIG. 10 shows T-300K, V_g(gate voltage) ═ 0V, V_d(drain voltage) is 800V traditional trench gate MOSFET, improved MOSFET grid lower 5nmThe magnitude of the electric field intensity. The 5nm peak electric field (7.3MV/cm) below the gate dielectric layer of the conventional trench-gate MOSFET clearly exceeds the safety threshold (4MV/cm), while the peak electric field (1.8MV/cm) of the improved MOSFET is below the safety threshold. This is because the bottom P electric field shielding region 13 at the bottom of the gate shields the bottom large electric field.

Fig. 11 is a gate charge characteristic curve of a conventional trench gate MOSFET, a modified MOSFET, with T-300K. The grid voltage of the device is increased from 0V to 15V, and the total grid charge of the traditional trench grid MOSFET is 1571nC/cm²The total gate charge of the improved MOSFET is 611nC/cm²The decrease is 61.1%. The grid leakage charge quantity of the traditional trench grid MOSFET is 892nC/cm²The total gate-drain charge of the improved MOSFET is 76nC/cm²The reduction is 91.5%. This is because the capacitive coupling structure and the coupling area among the gate, the drain, and the source are changed when the device structure is changed.

Fig. 12 is a graph of gate charge time for a conventional trench-gate MOSFET, a modified MOSFET, with T-300K. Due to the reduction of the grid charge quantity, the grid charging time is reduced, the reduction of grid signal delay is facilitated, and the working frequency range of the device is widened.

FIG. 13 shows T-300K, V_gThe gate voltage is 0V of the feedback capacitance curve of the conventional trench gate MOSFET and the improved MOSFET. The feedback capacitance of the improved MOSFET is reduced to some extent thanks to this development of the device structure. Device V_dWhen the drain voltage is 800V, the feedback capacitance of the traditional trench gate MOSFET and the improved MOSFET is 54.87pF/cm²、32.74pF/cm²(ii) a The improved MOSFET is 40.3% lower than the conventional trench-gate MOSFET.

Fig. 14 shows the switching loss curves of the conventional trench gate MOSFET and the modified MOSFET with T-300K. The working voltage of the device is 800V, and the current density flowing through the device is 100A/cm². The device turn-on loss is the loss generated in the process of adding the gate voltage from 0V to 15V, and the device turn-off loss is the loss generated in the process of adding the gate voltage from 15V to 0V. The total switching loss, the turn-on loss and the turn-off loss of the traditional trench gate MOSFET under different switching frequencies are all larger than those of the improved MOSFET. Main switch of traditional trench gate MOSFET under different switching frequenciesThe loss, the turn-on loss and the turn-off loss are reduced along with the increase of the switching frequency, the descending trend is slowed down after the switching frequency is greater than 10M, the total loss is the minimum when the switching frequency is 10M, and the total switching loss, the turn-on loss and the turn-off loss are realized at the moment. The total switching loss, the turn-on loss and the turn-off loss of the traditional trench gate MOSFET under different switching frequencies are reduced along with the increase of the switching frequency, and the total loss is the minimum when the switching frequency is 100M. When the switching frequency is 100M, the turn-on loss of the conventional trench gate MOSFET and the improved MOSFET is 14.78 (mJ/cm)²)、0.53(mJ/cm²) Compared with the traditional trench gate MOSFET, the improved MOSFET is reduced by 96.4%; when the switching frequency is 100M, the turn-off loss of the conventional trench gate MOSFET and the improved MOSFET is 14.67 (mJ/cm)²)、1.43(mJ/cm²) Compared with the traditional trench gate MOSFET, the improved MOSFET is reduced by 90.3%;

table 1 shows the comparison of key performance indicators of the conventional trench gate MOSFET and the improved MOSFET, where the table includes on-resistance, breakdown voltage gate-drain charge, and feedback capacitance. TABLE 2 switching losses at different switching frequencies

TABLE 1 comparison of key performance metrics for different MOSFETs (Note 1: the drain voltage is 800V at this time)

TABLE 2 switching losses at different switching frequencies for conventional trench gate MOSFET and improved MOSFET

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.