阅读说明：本技术 用于红外接收装置的环境光补偿电路 (Ambient light compensation circuit for infrared receiving device ) 是由 曹晶 于 2021-08-13 设计创作，主要内容包括：本发明涉及一种用于红外接收装置的环境光补偿电路,包括依次连接的电位检测单元、电压积分单元和电压电流转换单元,其中,所述电位检测单元用于接收第一电压信号(VSAM),并将第一电压信号(VSAM)与基准电压比较；所述电压积分单元包括控制电容充电的第一开关(SW1)和控制电容放电的第二开关(SW2),根据所述电位检测单元输出信号控制所述第一开关(SW1)和第二开关(SW2),从而对电容充电或放电以输出第二电压信号(VX),所述电压电流转换单元用于对所述第二电压信号(VX)转换以输出补偿电流。本发明能够实现环境光电流补偿,实现稳定增益。(The invention relates to an ambient light compensation circuit for an infrared receiving device, which comprises a potential detection unit, a voltage integration unit and a voltage-current conversion unit which are sequentially connected, wherein the potential detection unit is used for receiving a first Voltage Signal (VSAM) and comparing the first Voltage Signal (VSAM) with a reference voltage; the voltage integration unit comprises a first switch (SW1) for controlling the charging of the capacitor and a second switch (SW2) for controlling the discharging of the capacitor, the first switch (SW1) and the second switch (SW2) are controlled according to the output signal of the potential detection unit, so that the capacitor is charged or discharged to output a second voltage signal (VX), and the voltage-current conversion unit is used for converting the second voltage signal (VX) to output a compensation current. The invention can realize ambient light current compensation and realize stable gain.)

1. An ambient light compensation circuit for an infrared receiving device, comprising an infrared receiving diode (D1) and a load Resistor (RL), characterized by comprising a potential detection unit, a voltage integration unit and a voltage-current conversion unit connected in sequence, wherein,

the potential detection unit is used for receiving a first Voltage Signal (VSAM) and comparing the first Voltage Signal (VSAM) with a reference voltage;

the voltage integration unit includes a first switch (SW1) controlling charging of the capacitor and a second switch (SW2) controlling discharging of the capacitor, the first switch (SW1) and the second switch (SW2) being controlled according to the potential detection unit output signal to charge or discharge the capacitor to output a second voltage signal (VX),

the voltage-current conversion unit is used for converting the second voltage signal (VX) to output a compensation current.

2. The ambient light compensation circuit for an infrared receiving device according to claim 1, characterized in that: the potential detection unit comprises a first comparator (COMP1) and a second comparator (COMP2), the first comparator (COMP1) outputs signals to control the on-off of the first switch (SW1), and the second comparator (COMP2) controls the on-off of the second switch (SW 2).

3. The ambient light compensation circuit for an infrared receiving device according to claim 2, characterized in that: the first comparator (COMP1) has a first inverting terminal and a second inverting terminal, the first inverting terminal is connected with a first reference voltage (VREF1), and the second inverting terminal is connected with a second reference voltage (VREF 2);

when the first Voltage Signal (VSAM) is greater than the second reference voltage (VREF2), the first comparator (COMP1) output signal flips from low level to high level; when the first Voltage Signal (VSAM) is less than the first reference voltage (VREF1), the first comparator (COMP1) output signal is flipped from high level to low level;

the first reference voltage (VREF1) is less than the second reference voltage (VREF 2).

4. The ambient light compensation circuit for an infrared receiving device according to claim 3, characterized in that: a second comparator (COMP2) having a third inverting terminal and a fourth inverting terminal, the third inverting terminal being connected to a third reference voltage (VREF3), the fourth inverting terminal being connected to a fourth reference voltage (VREF 4);

when the first Voltage Signal (VSAM) is greater than the fourth reference voltage (VREF4), the second comparator (COMP2) output signal flips from low to high; when the first Voltage Signal (VSAM) is less than the third reference voltage (VREF3), the second comparator (COMP2) output signal is flipped from high level to low level;

the third reference voltage (VREF3) is less than a fourth reference voltage (VREF 4).

5. The ambient light compensation circuit for an infrared receiving device according to claim 4, characterized in that: the first reference voltage (VREF1) < the second reference voltage (VREF2) < the third reference voltage (VREF3) < the fourth reference voltage (VREF 4).

6. The ambient light compensation circuit for an infrared receiving device according to claim 4, characterized in that:

controlling the first switch (SW1) to be turned off when the first comparator (COMP1) outputs a high level;

when the first comparator (COMP1) outputs a low level, controlling the first switch (SW1) to pull in;

when the second comparator (COMP2) outputs a high level, controlling the second switch (SW2) to pull in;

when the second comparator (COMP2) outputs a low level, the second switch (SW2) is controlled to be turned off.

7. The ambient light compensation circuit for an infrared receiving device according to claim 1, characterized in that: the voltage integration unit comprises a first constant current source (IC1), a second constant current source (IC2) and a first Capacitor (CX), wherein a first switch (SW1) and a second switch (SW2) are sequentially connected between the first constant current source (IC1) and the second constant current source (IC 2); the common terminal between the first switch (SW1) and the second switch (SW2) is connected with the first Capacitor (CX).

8. The ambient light compensation circuit for an infrared receiving device according to claim 7, characterized in that: the voltage integration unit comprises a second Capacitor (CF) and a first Resistor (RF), the first Capacitor (CX), the second Capacitor (CF) and the first Resistor (RF) are connected to form a pi-type filter loop, and the first end of the first Capacitor (CX) is connected with the input end of the voltage-current conversion unit through the first Resistor (RF).

9. The ambient light compensation circuit for an infrared receiving device according to claim 7, characterized in that: the voltage and current conversion unit comprises a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a fourth PMOS tube (P4) and a third constant current source (IC3),

the first PMOS tube (P1), the second PMOS tube (P2), the third PMOS tube (P3) and the fourth PMOS tube (P4) are connected to form a laminated current mirror structure, the first PMOS tube (P1) and the second PMOS tube (P2) are connected to form a group, and the common end between the drain of the fourth PMOS tube (P4) and the third constant current source (IC3) is connected with the output end (ICOM) of the voltage-current conversion unit.

10. The ambient light compensation circuit for an infrared receiving device according to claim 9, characterized in that: the voltage and current conversion unit comprises an operational amplifier (AMP1) and an NMOS (NX), wherein the in-phase end of the operational amplifier (AMP1) is connected with the first end of the first Capacitor (CX), and the reverse-phase end of the operational amplifier (AMP1) is grounded through a Resistor (RS); the output end of the operational amplifier (AMP1) is connected with the grid electrode of the NMOS tube (NX), and the common end between the inverting end of the operational amplifier (AMP1) and the Resistor (RS) is connected with the source electrode of the NMOS tube (NX).

Technical Field

The invention relates to an ambient light compensation circuit for an infrared receiving device.

Background

As shown in fig. 1, the circuit structure of the conventional infrared receiving apparatus includes: a photosensitive tube D1, load resistors R1 and R2 … RN, bypass tubes N1 and N2 … NN, a voltage source VDD, an internal reference source VS and an output terminal VOUT.

The work flow of the structure is as follows: the photodiode D1 receives the infrared signal and generates an infrared reception current I ═ ISIG + IF (ISIG is the signal current, IF is the ambient photocurrent, ISIG < IF), which forms a signal voltage across the resistors R1, R2 … RN.

When the current I is small, VOUT is VS-I (R1+ R2+ … + RN), and the gain is 1/Gm, namely R1+ R2+ … + RN; when the current becomes larger and the voltage drop across the resistor is sufficient to turn on the bypass, the gain will gradually decrease.

It can be seen from the above process that the gain of the device varies for different ambient photocurrents IF, i.e. VOUT ═ f (i) function is nonlinear, so that the receiving device cannot be applied to a linear amplification system.

Disclosure of Invention

The invention aims to provide an ambient light compensation circuit for an infrared receiving device, which can realize ambient light current compensation and realize stable gain.

The technical scheme for realizing the purpose of the invention is as follows:

an ambient light compensation circuit for an infrared receiving device, comprising an infrared receiving diode (D1) and a load Resistor (RL), comprising:

comprises a potential detection unit, a voltage integration unit and a voltage-current conversion unit which are connected in sequence, wherein,

the potential detection unit is used for receiving a first Voltage Signal (VSAM) and comparing the first Voltage Signal (VSAM) with a reference voltage;

the voltage integration unit includes a first switch (SW1) controlling charging of the capacitor and a second switch (SW2) controlling discharging of the capacitor, the first switch (SW1) and the second switch (SW2) being controlled according to the potential detection unit output signal to charge or discharge the capacitor to output a second voltage signal (VX),

the voltage-current conversion unit is used for converting the second voltage signal (VX) to output a compensation current.

Further, the potential detection unit comprises a first comparator (COMP1) and a second comparator (COMP2), the first comparator (COMP1) outputs signals to control the on-off of the first switch (SW1), and the second comparator (COMP2) controls the on-off of the second switch (SW 2).

Further, the first comparator (COMP1) has a first inverting terminal and a second inverting terminal, the first inverting terminal being connected to a first reference voltage (VREF1), the second inverting terminal being connected to a second reference voltage (VREF 2);

when the first Voltage Signal (VSAM) is greater than the second reference voltage (VREF2), the first comparator (COMP1) output signal flips from low level to high level; when the first Voltage Signal (VSAM) is less than the first reference voltage (VREF1), the first comparator (COMP1) output signal is flipped from high level to low level;

the first reference voltage (VREF1) is less than the second reference voltage (VREF 2).

Further, the second comparator (COMP2) has a third inverting terminal terminating the third reference voltage (VREF3) and a fourth inverting terminal terminating the fourth reference voltage (VREF 4);

when the first Voltage Signal (VSAM) is greater than the fourth reference voltage (VREF4), the second comparator (COMP2) output signal flips from low to high; when the first Voltage Signal (VSAM) is less than the third reference voltage (VREF3), the second comparator (COMP2) output signal is flipped from high level to low level;

the third reference voltage (VREF3) is less than a fourth reference voltage (VREF 4).

Further, the first reference voltage (VREF1) < the second reference voltage (VREF2) < the third reference voltage (VREF3) < the fourth reference voltage (VREF 4).

Further, when the first comparator (COMP1) outputs a high level, the first switch (SW1) is controlled to be turned off;

when the first comparator (COMP1) outputs a low level, controlling the first switch (SW1) to pull in;

when the second comparator (COMP2) outputs a high level, controlling the second switch (SW2) to pull in;

when the second comparator (COMP2) outputs a low level, the second switch (SW2) is controlled to be turned off.

Further, the voltage integration unit comprises a first constant current source (IC1), a second constant current source (IC2) and a first Capacitor (CX), wherein a first switch (SW1) and a second switch (SW2) are sequentially connected between the first constant current source (IC1) and the second constant current source (IC 2); the common terminal between the first switch (SW1) and the second switch (SW2) is connected with the first Capacitor (CX).

Furthermore, the voltage integration unit comprises a second Capacitor (CF) and a first Resistor (RF), the first Capacitor (CX), the second Capacitor (CF) and the first Resistor (RF) are connected to form a pi-type filter loop, and a first end of the first Capacitor (CX) is connected to an input end of the voltage-current conversion unit through the first Resistor (RF).

Further, the voltage-current conversion unit comprises a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a fourth PMOS tube (P4), and a third constant current source (IC3),

the first PMOS tube (P1), the second PMOS tube (P2), the third PMOS tube (P3) and the fourth PMOS tube (P4) are connected to form a laminated current mirror structure, the first PMOS tube (P1) and the second PMOS tube (P2) are connected to form a group, and the common end between the drain of the fourth PMOS tube (P4) and the third constant current source (IC3) is connected with the output end (ICOM) of the voltage-current conversion unit.

Further, the voltage-current conversion unit comprises an operational amplifier (AMP1) and an NMOS (NX), wherein the in-phase end of the operational amplifier (AMP1) is connected with the first end of the first Capacitor (CX), and the inverting end of the operational amplifier (AMP1) is grounded through a Resistor (RS); the output end of the operational amplifier (AMP1) is connected with the grid electrode of the NMOS tube (NX), and the common end between the inverting end of the operational amplifier (AMP1) and the Resistor (RS) is connected with the source electrode of the NMOS tube (NX).

The invention has the following beneficial effects:

the voltage-current conversion circuit comprises a potential detection unit, a voltage integration unit and a voltage-current conversion unit, wherein the potential detection unit is used for comparing the voltage of a first voltage signal output end (VSAM) with a reference voltage; the voltage integration unit is controlled by the potential detection unit, and outputs a second voltage signal (VX) by charging or discharging the capacitor, and the voltage-current conversion unit converts the second voltage signal (VX) into an output compensation current (ambient light compensation current). The invention realizes the stripping of the ambient light current IF in the infrared receiving current I by detecting the high-low change of the output voltage VOUT (equivalent to a first voltage signal output end VSAM) of the infrared receiving device, forming an integral voltage through voltage integral calculation, and finally outputting a compensation current (ambient light compensation current) through voltage current conversion, wherein the retained current comprises a lossless real signal current ISIG and a part of residual ambient light current components, so that the output voltage VOUT can be ensured to be in a specific level range and can not be close to the ground, and meanwhile, the gain of the infrared receiving device is ensured to be constant.

The potential detection unit comprises a first comparator (COMP1) and a second comparator (COMP2), wherein the first comparator (COMP1) and the second comparator (COMP2) are hysteresis comparators and are respectively provided with four reference voltages, the first comparator (COMP1) outputs signals to control the on-off of a first switch (SW1), and the second comparator (COMP2) controls the on-off of a second switch (SW2), so that a voltage integration unit is controlled. According to the invention, through the arrangement of four reference voltages of the potential detection unit, the ambient light intensity is simulated, and more adaptive detection and compensation precision is further ensured.

The voltage integration unit comprises a first constant current source (IC1), a second constant current source (IC2), a first Capacitor (CX), a second Capacitor (CF) and a first Resistor (RF), wherein the first Capacitor (CX), the second Capacitor (CF) and the first Resistor (RF) are connected to form a pi-type filtering loop, so that spike interference can be eliminated, a second voltage signal (VX) is stabilized, and detection and compensation accuracy is further guaranteed.

The voltage and current conversion unit comprises a first PMOS (P1), a second PMOS (P2), a third PMOS (P3), a fourth PMOS (P4) and a third constant current source (IC3), wherein the first PMOS (P1), the second PMOS (P2), the third PMOS (P3) and the fourth PMOS (P4) are connected into a laminated current mirror structure, so that a second voltage signal (VX) is effectively converted into a compensation current signal.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional infrared receiving apparatus;

FIG. 2 is a schematic block diagram of the circuit of the present invention;

FIG. 3 is a schematic of the circuit of the present invention;

FIG. 4 is a schematic diagram of the input and output voltages of the voltage detection unit according to the present invention.

Detailed Description

The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.

As shown in fig. 2 and 3, the ambient light compensation circuit for an infrared receiving device according to the present invention includes an infrared receiving diode D1 and a load resistor RL, and includes:

the signal input end of the potential detection unit is connected with a first voltage signal output end VSAM, the first voltage signal output end VSAM is connected with the common end of the infrared receiving diode D1 and the load resistor RL, and the potential detection unit is used for comparing the voltage of the first voltage signal output end VSAM with a reference voltage;

a voltage integration unit outputting a second voltage signal VX by charging or discharging a capacitor, the voltage integration unit being provided with a first switch SW1 controlling charging of the capacitor and a second switch SW2 controlling discharging of the capacitor, the first switch SW1 and the second switch SW2 being controlled by the potential detection unit output signal,

the signal input end of the voltage-current conversion unit is connected with the signal output end of the voltage integration unit, and the voltage-current conversion unit converts a second voltage signal VX into a compensation current; and the signal output end ICOM of the voltage-current conversion unit is connected with the signal output end VOUT of the infrared receiving diode D1.

The potential detection unit comprises a first comparator COMP1 and a second comparator COMP2, the same-phase ends of the first comparator COMP1 and the second comparator COMP2 are connected with a first voltage signal output end VSAM, a signal output by the first comparator COMP1 controls the on-off of the first switch SW1, and the second comparator COMP2 controls the on-off of the second switch SW 2.

The first comparator COMP1 and the second comparator COMP2 are hysteresis comparators; the first comparator COMP1 is provided with a first inverting terminal and a second inverting terminal, wherein the first inverting terminal is connected with a first reference voltage VREF1, and the second inverting terminal is connected with a second reference voltage VREF 2; when the voltage of the first voltage signal output end VSAM is greater than the second reference voltage VREF2, the output signal of the first comparator COMP1 is inverted from a low level to a high level, when the voltage of the first voltage signal output end VSAM is less than the first reference voltage VREF1, the output signal of the first comparator COMP1 is inverted from the high level to the low level, and the first reference voltage VREF1 is less than the second reference voltage VREF 2.

The second comparator COMP2 is provided with a third inverting terminal and a fourth inverting terminal, wherein the third inverting terminal is connected with a third reference voltage VREF3, and the fourth inverting terminal is connected with a fourth reference voltage VREF 4; when the voltage of the first voltage signal output end VSAM is greater than the fourth reference voltage VREF4, the output signal of the second comparator COMP2 is inverted from a low level to a high level, when the voltage of the first voltage signal output end VSAM is less than the third reference voltage VREF3, the output signal of the second comparator COMP2 is inverted from the high level to the low level, and the third reference voltage VREF3 is less than the fourth reference voltage VREF 4; the third reference voltage VREF3 is less than the fourth reference voltage VREF4, the first reference voltage VREF1 is less than the third reference voltage VREF3, and the second reference voltage VREF2 is less than the fourth reference voltage VREF 4. In this embodiment, the first reference voltage VREF1 < the second reference voltage VREF2 < the third reference voltage VREF3 < the fourth reference voltage VREF 4.

When the first comparator COMP1 outputs a high level, the first switch SW1 is controlled to be turned off; when the first comparator COMP1 outputs a low level, the first switch SW1 is controlled to be closed; when the second comparator COMP2 outputs a high level, the second switch SW2 is controlled to be closed, and when the second comparator COMP2 outputs a low level, the second switch SW2 is controlled to be opened.

The voltage integration unit comprises a first constant current source IC1, a second constant current source IC2 and a first capacitor CX, wherein a first switch SW1 and a second switch SW2 are sequentially connected between the first constant current source IC1 and the second constant current source IC2, one end of the first constant current source IC1 is connected with a power supply end VDD, and one end of the second constant current source IC2 is grounded; the common terminal between the first switch SW1 and the second switch SW2 is connected with the first terminal of the first capacitor CX, the first terminal of the first capacitor CX is connected with the signal input terminal of the voltage-current conversion unit, and the second terminal of the first capacitor CX is grounded.

The voltage integration unit comprises a second capacitor CF and a first resistor RF, the first capacitor CX, the second capacitor CF and the first resistor RF are connected to form a pi-type filter loop, and the first end of the first capacitor CX is connected with the signal input end of the voltage current conversion unit through the first resistor RF.

The voltage and current conversion unit comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4 and a third constant current source IC3, wherein the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are connected into a laminated current mirror structure, the first PMOS tube P1 and the second PMOS tube P2 are connected into a group, a current IX1 sequentially flowing through the first PMOS tube P1 and the second PMOS tube P2 is related to a second voltage signal VX, a current IX and a current IX1 sequentially flowing through the third PMOS tube P3 and the fourth PMOS tube P4 form a current mirror, a common end between a drain electrode of the fourth PMOS tube P4 and the third constant current source IC3 is connected with a signal output end ICOM of the voltage conversion unit, and the signal output end ICOM outputs compensation current.

The voltage and current conversion unit comprises an operational amplifier AMP1 and an NMOS (N-channel metal oxide semiconductor) tube NX, wherein the in-phase end of the operational amplifier AMP1 is connected with the first end of the first capacitor CX, and the reverse-phase end of the operational amplifier AMP1 is grounded through a resistor RS; the output end of the operational amplifier AMP1 is connected with the grid electrode of the NMOS tube NX, and the common end between the inverting end of the operational amplifier AMP1 and the resistor RS is connected with the source electrode of the NMOS tube NX.

The working principle of the present invention is further explained below.

As shown in fig. 2 and 3, the first voltage signal output terminal VSAM is used for acquiring the potential of the signal output terminal VOUT of the infrared receiving diode D1, the voltage value of the VSAM represents the magnitude of the infrared receiving current, and the VSAM is VOUT-VS-I RL, and VS is the voltage of the power supply terminal VS.

On the one hand, the signal current ISIG < the ambient photocurrent IF in the infrared receiving current I, so that the change of VSAM is mainly caused by the change of IF. On the other hand, the variation frequency of the IF is much smaller than that of the signal, so that the ambient light current IF approximates a dc component to the signal current ISIG. That is, the change amount of the VSAM voltage is basically derived from the change in the ambient light current IF, and the change frequency of the VSAM is low, showing the change characteristic of the IF.

The voltage VSAM is compared with reference voltages VREF1, VREF2, VREF3, and VREF4, and outputs control signals CTRL1 and CTRL2 to control the first switch SW1 and the second switch SW2, respectively.

For the first comparator COMP1, VREF1 is the comparison point and VREF2 is the hysteresis comparison point, i.e., CTRL1 will toggle from high to low only when VSAM < VREF1 as the VSAM voltage gradually drops; when VSAM voltage rises gradually from low, requiring VSAM > VREF2, the output CTRL1 will flip from low to high.

For the second comparator COMP2, CTRL2 will flip from low to high only when the VSAM voltage gradually rises and VSAM > VREF 4; when VSAM voltage again ramps down from high, requiring VSAM < VREF3, the output CTRL2 will toggle from high to low. See fig. 4 for a specific comparison of effects.

The first switch SW1 and the second switch SW2 are turned on and off depending on whether CTRL1 and CTRL2 are high or low, respectively, as detailed in the following table:

CTRL1 at "low" level	SW1 "closed"
		CTRL1 at "high" level	SW1 "OFF"
CTRL2 at "low" level	SW2 "OFF"
		CTRL2 at "high" level	SW2 "closed"

When the first switch SW1 is "closed", the second switch SW2 is necessarily "open", and vice versa.

When the first switch SW1 is "closed", the first constant current source IC1 charges the first capacitor (integrating capacitor) CX, and the potential of the second voltage signal VX gradually rises; when the second switch SW2 is "closed", the second constant current source IC2 discharges the first capacitor (integrating capacitor) CX to ground, and the potential of the second voltage signal VX gradually decreases.

The voltage value of the second voltage signal VX produces a current IX (IX ≧ 0) through operational amplifier AMP 1.

The compensation current output is:

in the formula, k is a current mirror transfer coefficient, and IC3 is a third constant current source current value;

the VSAM voltage thus compensated is

By reasonably setting four reference voltages (VREF1, VREF2, VREF3 and VREF4), VX is set to fluctuate near 0.5 times VDD voltage and is far away from 0 and VDD, so that the detection compensation system can stably work, and VDD is power supply voltage.

In the extreme case of no ambient light, the VSAM voltage at this time is:

VS-RL*(I+IC3)＝VS-RL*(ISIG+IC3)

setting ISIG < IC3, i.e., the static voltage of VSAM is determined by IC3, which is the highest voltage of VSAM.

At this time, since VSAM > VREF4, the second switch SW2 is always in a closed state, the second voltage signal VX remains at an extremely low level, and the compensation current is an initial value (-IC 3).

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.