Data processing method, data processing device, processor chip, electronic device and medium

文档序号：1831095 发布日期：2021-11-12 浏览：24次中文

阅读说明：本技术 数据处理方法、装置、处理器芯片、电子设备和介质 (Data processing method, data processing device, processor chip, electronic device and medium ) 是由王京施佳鑫谢汉林龚小章于 2021-07-20 设计创作，主要内容包括：本公开提供了一种数据处理方法、装置、处理器芯片、电子设备和介质,涉及人工智能芯片技术领域。具体实现方案为：获取第一关系指令,根据第一关系指令,执行第一关系指令之前获取的至少一个第一计算指令,在至少一个第一计算指令执行完成的情况下,根据第一关系指令,发送确认信息,以使得接收到确认信息的第二协处理器,根据确认信息,恢复获取第二协处理器获取到的第二关系指令之后的第二计算指令的状态。本公开中,第一协处理和第二协处理间根据第一关系指令,生成确认信息,根据确认信息实现协处理器间自行协调运行时间,提升了整体的运行效率。(The disclosure provides a data processing method, a data processing device, a processor chip, electronic equipment and a medium, and relates to the technical field of artificial intelligence chips. The specific implementation scheme is as follows: the method comprises the steps of obtaining a first relation instruction, executing at least one first calculation instruction obtained before the first relation instruction according to the first relation instruction, sending confirmation information according to the first relation instruction under the condition that execution of the at least one first calculation instruction is completed, enabling a second coprocessor receiving the confirmation information to recover the state of a second calculation instruction obtained by the second coprocessor after the second relation instruction is obtained according to the confirmation information. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.)

1. A data processing method for a first coprocessor in a chip, the method comprising:

acquiring a first relation instruction;

according to the first relation instruction, executing at least one first calculation instruction acquired before the first relation instruction;

under the condition that the execution of the at least one first calculation instruction is completed, sending confirmation information according to the first relation instruction, so that the second coprocessor receiving the confirmation information recovers to acquire the state of a second calculation instruction according to the confirmation information; wherein the second computing instruction is fetched by the second coprocessor after receiving a second relationship instruction.

2. The method of claim 1, the first relationship instruction including an identification of a second coprocessor which is dependent on the first coprocessor;

the sending of the confirmation information according to the first relation instruction when the execution of the at least one calculation instruction is completed includes:

and sending the confirmation information to the second coprocessor according to the identification of the second coprocessor indicated by the first relation instruction under the condition that the execution of the at least one calculation instruction is completed.

3. The method of claim 2, the first relationship instruction containing an event identification;

the sending of the confirmation information according to the first relation instruction when the execution of the at least one calculation instruction is completed includes:

upon completion of execution of the at least one computing instruction, broadcasting acknowledgement information including the event identification.

4. The method according to any one of claims 1-3, further comprising:

acquiring a command queue query request sent by a control unit;

inquiring the residual storage space contained in the command queue according to the inquiry request;

sending the inquired indication information of the remaining storage space to the control unit, so that the control unit stores the first relation instruction or the first calculation instruction into the remaining storage space.

5. A data processing method for a second coprocessor in a chip, the method comprising:

acquiring a second relation instruction sent by the control unit;

under the condition of obtaining the first relation instruction, stopping obtaining a calculation instruction from a command queue corresponding to the second coprocessor;

monitoring confirmation information sent by the first coprocessor;

and recovering the state of acquiring the second calculation instruction from the command queue according to the confirmation information and the second relation instruction.

6. The method of claim 5, the first relationship instruction including an identification of the first coprocessor; the recovering the state of obtaining the second calculation instruction from the command queue according to the confirmation information and the second relation instruction includes:

and under the condition that the identification of the first coprocessor contained in the confirmation information is matched with the identification of the first coprocessor contained in the second relation instruction, resuming to acquire the second calculation instruction from the command queue.

7. The method of claim 5, the first relationship instruction containing an event identification; the recovering the state of obtaining the second calculation instruction from the command queue according to the confirmation information and the second relation instruction includes:

and under the condition that the event identifier contained in the confirmation information is matched with the event identifier contained in the first relation instruction, recovering to obtain a second calculation instruction from the command queue.

8. The method according to any one of claims 5-7, further comprising:

acquiring a command queue query request sent by a control unit;

inquiring the residual storage space contained in the command queue according to the inquiry request;

sending the inquired indication information of the remaining storage space to the control unit, so that the control unit stores the second relation instruction or the second calculation instruction in the remaining storage space.

9. A processor chip comprises a control unit, a first coprocessor and a second coprocessor;

the control unit is used for sending a first calculation instruction and a first relation instruction to the first coprocessor and sending a second calculation instruction and a second relation instruction to the second coprocessor;

the first coprocessor, for performing the data processing method of any one of claims 1-4;

the second coprocessor, configured to perform the data processing method according to any one of claims 5 to 8.

10. A data processing apparatus, the apparatus comprising:

the acquisition module is used for acquiring a first relation instruction;

the execution module is used for executing at least one first calculation instruction acquired before the first relation instruction according to the first relation instruction;

a sending module, configured to send acknowledgement information according to the first relation instruction when execution of the at least one first computation instruction is completed, so that the second coprocessor that receives the acknowledgement information resumes obtaining a state of a second computation instruction according to the acknowledgement information; wherein the second computing instruction is fetched by the second coprocessor after receiving a second relationship instruction.

11. A data processing apparatus, the apparatus comprising:

the acquisition module is used for acquiring a first relation instruction sent by the control unit;

the processing module is used for stopping acquiring a second calculation instruction from the command queue corresponding to the second coprocessor under the condition of acquiring the first relation instruction;

the monitoring module is used for monitoring the confirmation information sent by the first coprocessor;

and the processing module is further configured to recover, according to the confirmation information and the second relation instruction, a state of obtaining a second calculation instruction from the command queue.

12. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4 or to perform the method of any one of claims 5-8.

13. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-4 or to perform the method of any one of claims 5-8.

14. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1-4 or performs the method of any of claims 5-8.

Technical Field

The present disclosure relates to the field of artificial intelligence chip technology, and in particular, to a data processing method, apparatus, processor chip, electronic device, and medium.

Background

In a system-on-chip processor, there is a cooperation between different processor cores to complete a computing task, for example, in an accelerator or a processor facing deep learning, or an accelerator or a processor for large data processing, heterogeneous processors are usually required to be constructed to jointly implement a computing task, that is, output data of a previous coprocessor in the heterogeneous processors needs to be used by a next processor in a computing process.

How to control the cooperation among the coprocessors to improve the overall operating efficiency of the heterogeneous processor is an urgent technical problem to be solved.

Disclosure of Invention

The present disclosure provides a data processing method, a processor chip, an apparatus, an electronic device, and a medium for improving operation efficiency.

According to an aspect of the present disclosure, there is provided a data processing method for a first coprocessor, the method including:

acquiring a first relation instruction;

according to the first relation instruction, executing at least one calculation instruction acquired before the first relation instruction;

and under the condition that the execution of the at least one calculation instruction is completed, sending confirmation information according to the first relation instruction, so that the second coprocessor receiving the confirmation information recovers the state of acquiring the calculation instruction according to the confirmation information.

According to another aspect of the present disclosure, there is provided a data processing method for a second coprocessor, the method comprising:

acquiring a first relation instruction sent by a control unit;

under the condition of obtaining the first relation instruction, stopping obtaining a calculation instruction from a command queue corresponding to the second coprocessor;

monitoring confirmation information sent by the first coprocessor;

and according to the confirmation information, recovering to obtain the calculation instruction from the command queue, and performing data processing according to the obtained calculation instruction.

According to another aspect of the present disclosure, there is provided a processor chip including a control unit, a first coprocessor, and a second coprocessor;

the first coprocessor is used for executing the data processing method of the previous aspect;

the second coprocessor is used for executing the data processing method of the other aspect.

According to another aspect of the present disclosure, there is provided a data processing apparatus provided in a first coprocessor, the apparatus including:

the acquisition module is used for acquiring a first relation instruction;

the execution module is used for executing at least one calculation instruction acquired before the first relation instruction according to the first relation instruction;

and the sending module is used for sending confirmation information according to the first relation instruction under the condition that the execution of the at least one calculation instruction is completed, so that the second coprocessor receiving the confirmation information recovers the state of acquiring the calculation instruction according to the confirmation information.

According to another aspect of the present disclosure, there is provided a data processing apparatus provided in a second coprocessor, the apparatus comprising:

the acquisition module is used for acquiring a first relation instruction sent by the control unit;

the processing module is used for stopping obtaining the calculation instruction from the command queue corresponding to the second coprocessor under the condition of obtaining the first relation instruction;

the monitoring module is used for monitoring the confirmation information sent by the first coprocessor;

and the processing module is further used for recovering to acquire the calculation instruction from the command queue according to the confirmation information so as to perform data processing according to the acquired calculation instruction.

According to another aspect of the present disclosure, there is provided an electronic device including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the first aspect or to perform the method of the second aspect.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of the first aspect or to perform the method of the second aspect.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the method of the first aspect or performs the method of the second aspect.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a diagram illustrating coordination among coprocessors in the prior art;

fig. 2 is a schematic flow chart of a data processing method according to an embodiment of the disclosure

Fig. 3 is a schematic flow chart of another data processing method provided in the embodiment of the present disclosure;

fig. 4 is a schematic diagram of an acknowledgement message transmission according to an embodiment of the disclosure;

fig. 5 is a schematic flow chart of another data processing method provided in the embodiments of the present disclosure;

fig. 6 is a second schematic diagram illustrating the transmission of an acknowledgement message according to the embodiment of the disclosure;

fig. 7 is a schematic flow chart of another data processing method provided in the embodiments of the present disclosure;

fig. 8 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure;

fig. 9 is a schematic flow chart of another data processing method provided in the embodiments of the present disclosure;

FIG. 10 is a schematic flow chart diagram illustrating another data processing method according to an embodiment of the present disclosure;

fig. 11 is a schematic flow chart of another data processing method provided in the embodiments of the present disclosure;

fig. 12 is a schematic structural diagram of a processor chip according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure;

fig. 15 is a schematic block diagram of an electronic device 800 provided by an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

A data processing method, an apparatus, a processor chip, an electronic device, and a medium of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

The heterogeneous processor includes a plurality of coprocessors and control units, and each coprocessor often needs to cooperate to complete a computation task, for example, in a deep learning scenario of artificial intelligence, or in a big data processing scenario, that is, output data of a previous coprocessor needs to be used by a next processor in a computation flow. In a scenario where data is dependent between coprocessors, a synchronization mechanism needs to be implemented so that each processor operates at a correct time point, and a next coprocessor cannot be started until a previous coprocessor finishes processing.

The heterogeneous processor in the related art synchronizes each coprocessor through the control unit so that each coprocessor operates at a correct time point. As shown in fig. 1, if there is a data dependency between two instructions sent to different coprocessors, synchronization is required. After the control unit generates a first instruction, the instruction is firstly sent to the corresponding coprocessor 1, and then the blocking waiting coprocessor 1 returns a completion signal. The control unit will continue to generate the second instruction after receiving the completion signal from the previous coprocessor 1, and send the instruction to the next coprocessor 2. This ensures that the coprocessors execute in the correct order.

However, in this processing manner, the control unit needs to block waiting during the operation of the coprocessor 1, and the execution overhead of the control unit itself cannot be masked, which affects the overall efficiency. Meanwhile, the instruction and the completion signal are transmitted in a time-sharing manner between the control unit and the coprocessor, so that time overhead is caused, and the overall efficiency is influenced.

Therefore, the data processing method is applied to a first coprocessor of artificial intelligence, the first coprocessor acquires a first relation instruction, executes at least one calculation instruction acquired before the first relation instruction according to the first relation instruction, and sends confirmation information according to the first relation instruction under the condition that the execution of the at least one calculation instruction is completed, so that a second coprocessor which receives the confirmation information recovers the state of acquiring the calculation instruction according to the confirmation information. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.

Fig. 2 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure.

As shown in fig. 2, the method comprises the following steps:

step 201, a first relation instruction is obtained.

In the embodiment of the present disclosure, a relationship instruction is set for describing a dependency relationship between coprocessors, where the dependency relationship indicates a dependency sequence executed by the coprocessors in a computing process, that is, the start of one coprocessor needs to be started depending on confirmation of another coprocessor having a dependency relationship. Therefore, for convenience of description, in the coprocessor having a dependency relationship in this embodiment, the coprocessor which transmits the acknowledgement information is referred to as a first coprocessor, and the coprocessor which is executed after receiving the acknowledgement information is referred to as a second coprocessor, so that the relationship instruction received by the first coprocessor is referred to as a first relationship instruction, and the relationship instruction received by the second coprocessor is referred to as a second relationship instruction. The second coprocessor will be described in the following embodiments.

The execution body of the disclosed embodiment is a first coprocessor.

The first relation instruction can be realized through a compiler, so that technicians in the field can freely and flexibly design the dependence relation among various coprocessors through programming control, and the requirements of different calculation tasks are met.

In the embodiment of the present disclosure, the first relation instruction is generated by the control unit, and the first coprocessor acquires the first relation instruction from the control unit.

Step 202, according to the first relation instruction, executing at least one first calculation instruction acquired before the first relation instruction.

In this embodiment, the control unit parses the program according to the program to be run to obtain a corresponding instruction, where the instruction obtained through parsing includes a first computation instruction and a first relationship instruction, the control unit sequentially sends the first computation instruction and the first relationship instruction obtained through parsing to the first coprocessor according to a sequence of each instruction set in the program, the first coprocessor executes the corresponding first computation instruction after receiving the first computation instruction, and the first coprocessor counts at least one first computation instruction received before the first relationship instruction according to the first relationship instruction after receiving the first relationship instruction, and executes the at least one first computation instruction.

And 203, under the condition that the execution of at least one calculation instruction is completed, sending confirmation information according to the first relation instruction, so that the second coprocessor receiving the confirmation information recovers to acquire the state of the second calculation instruction according to the confirmation information.

In this embodiment, the first relation instruction indicates a dependency relationship between the first coprocessor and the second coprocessor, and at the same time, at least one first computation instruction received before the first instruction may be determined, and when execution of at least one first computation instruction acquired before the first instruction is completed, according to the dependency relationship between the first coprocessor and the second coprocessor indicated by the first relation instruction, acknowledgement information is generated and sent to the second coprocessor, so that the second coprocessor receiving the acknowledgement information resumes acquiring a state of the second computation instruction according to the acknowledgement information, that is, before the second coprocessor receives the acknowledgement information, the second coprocessor is in a blocking state in which acquisition and execution of the second computation instruction after the second relation instruction are stopped, thereby implementing that the second coprocessor waits for an acknowledgement signal sent by the first coprocessor before starting a specific computation task, the running time of the first coprocessor and the running time of the second coprocessor can be automatically coordinated, and the overall running efficiency of the processor is greatly improved.

It should be noted that, in the embodiment of the present disclosure, the first coprocessor sends the acknowledgement information to the second coprocessor, and the acknowledgement information may be sent in a point-to-point manner or in a broadcast manner, and in the subsequent embodiments, different embodiments are used to respectively describe the sending manner of the acknowledgement information.

In the data processing method of the embodiment of the disclosure, a first relation instruction is acquired, at least one first calculation instruction acquired before the first relation instruction is executed according to the first relation instruction, and when execution of the at least one first calculation instruction is completed, confirmation information is sent according to the first relation instruction, so that a second coprocessor receiving the confirmation information recovers a state of acquiring a second calculation instruction of the second coprocessor after the second relation instruction according to the confirmation information. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.

Based on the foregoing embodiment, this embodiment provides another data processing method, which illustrates that a first relationship instruction received by a first coprocessor includes an identifier of a second coprocessor having a dependency relationship with the first coprocessor, so that acknowledgement information can be sent to the second coprocessor point-to-point. Fig. 3 is a schematic flow chart of another data processing method according to an embodiment of the disclosure, as shown in fig. 3, the method includes the following steps:

step 301, a first relation instruction is obtained.

The first relation instruction comprises a key word and identification of a second coprocessor which has a dependency relation with the first coprocessor. The identifier of the second coprocessor may be used to uniquely identify the second coprocessor, and a specific identification method is not limited in this embodiment. The key indicates that the first coprocessor is the sender, that is, the first relation instruction indicates that the first coprocessor needs to send the acknowledgement information to the second coprocessor indicated by the identification.

The explanation in step 201 is also applicable to the embodiment of the present disclosure, and the principle is the same, which is not described again in this embodiment.

In one implementation of the disclosed embodiment, the first relation instruction may be expressed as:

key words: transmitting a signal

Received second coprocessor identification

For example, SEND to P2 is a first relationship instruction where SEND to is a key and P2 is the received second coprocessor identification.

In the embodiment of the present disclosure, the first coprocessor means that in the dependency relationship, the second coprocessor needs to depend on an execution result of the first coprocessor, and therefore, after the first coprocessor completes executing a corresponding result, the first coprocessor needs to send confirmation information to the second coprocessor, and therefore, in the first relationship instruction, it is indicated that after the first coprocessor completes a calculation task before the first relationship instruction, the first coprocessor needs to send confirmation information to the second coprocessor.

Step 302, according to the first relation instruction, executing at least one first calculation instruction obtained before the first relation instruction.

In the embodiment of the present disclosure, after receiving the first relation instruction, the first coprocessor needs to confirm how many first calculation instructions are received before the first relation instruction, that is, needs to record how many currently executed but unexecuted calculation tasks are.

The explanation in step 202 is also applicable to the embodiment of the present disclosure, and the principle is the same, which is not described again in this embodiment.

Step 303, when the execution of the at least one first computation instruction is completed, sending acknowledgement information to the second coprocessor according to the identifier of the second coprocessor indicated by the first relation instruction, so that the second coprocessor receiving the acknowledgement information resumes acquiring the state of the second computation instruction according to the acknowledgement information.

In the embodiment of the present disclosure, according to the content included in the first relation instruction, when the execution of at least one first calculation instruction is completed, that is, after all the corresponding calculation tasks are executed, it is necessary to send an acknowledgement signal to the specified second coprocessor according to the content indicated by the first relation instruction, so that the second coprocessor receiving the acknowledgement information resumes executing the state of the second calculation instruction received after receiving the second relation instruction according to the acknowledgement information.

It should be understood that the first coprocessor only needs to record the first calculation instruction that is not completed when the first relation instruction is received, and the first calculation instruction received after the first relation instruction is unrelated to the acknowledgement signal that the first relation instruction needs to send; the first coprocessor is used for sending a confirmation signal, the first coprocessor does not need to be blocked, can continue to execute the first calculation instruction received after the first relation instruction, and can send confirmation information to the second coprocessor only after all the at least one first calculation instruction received before the first relation instruction is executed.

For clearly illustrating the embodiment of the present disclosure, the embodiment of the present disclosure provides an example, and fig. 4 is one of schematic diagrams of the transmission of the acknowledgement information provided by the embodiment of the present disclosure. As shown in FIG. 4, the instructions received by the first coprocessor P1 are CMD1, CMD2, SEND to P2 and CMD3, wherein CMD1, CMD2 and CMD3 are first computing instructions, SEND to P2 is a first relational instruction, wherein SEND to is a key, and P2 is a received second coprocessor identification. Often, coprocessors have a long pipeline, with each instruction being pipelined, so that the preceding instruction may still be executing at the beginning of the execution of the subsequent instruction. The first coprocessor P1 has received the first compute instructions CMD1 and CMD2 before receiving the first relationship instruction SEND to P2, so the condition for the first coprocessor P1 to SEND an acknowledge signal to the second coprocessor P2 is that the first compute instructions CMD1 and CMD2 are complete. But the first relational instruction SEND to P2 does not block execution of the subsequent first compute instruction CMD 3. In the embodiment of the disclosure, after the first coprocessor completes a corresponding calculation task through the keyword included in the first relation instruction and the identifier of the second coprocessor, the first coprocessor sends the confirmation information to the corresponding second coprocessor according to the indicated identifier, so that the second coprocessor can restore the second calculation instruction received after the second relation instruction is executed, so as to execute the corresponding processor task, thereby realizing the control of the synchronization process between the coprocessors based on the relation instruction and the confirmation information, and improving the overall operating efficiency of the heterogeneous processor.

It should be noted that, if there are multiple second coprocessors having dependencies with the first coprocessor, for example, if there are two second coprocessors, the identification part of the second coprocessor indicated in the first relationship instruction for receiving may include two second coprocessor identifications, for example, the first coprocessor P1, and send the acknowledgement information to the second coprocessor P2 and the second coprocessor P3 according to the identification indicated in the first relationship instruction.

In the data processing method of the embodiment of the disclosure, a first relation instruction is acquired, at least one first calculation instruction acquired before the first relation instruction is executed according to the first relation instruction, and when the execution of the at least one first calculation instruction is completed, confirmation information carrying identification information is sent according to the first relation instruction, so that a second coprocessor receiving the confirmation information recovers to acquire a state of a second calculation instruction according to the confirmation information. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.

Based on the foregoing embodiment, this embodiment provides another data processing method, where the first coprocessor sends the acknowledgement information in a broadcast manner, fig. 5 is a schematic flow diagram of another data processing method provided in this embodiment of the disclosure, and as shown in fig. 5, the method includes the following steps:

step 501, a first relation instruction is obtained.

In the embodiment of the disclosure, the first relation instruction includes a setting keyword and an event identifier. Each event identification number can correspond to an event with a specific meaning, and can be planned by a software programmer, for example, the event is as follows: and setting the click quantity of the user in time. The keyword indicates that the first coprocessor is a sender, that is, the first relation instruction indicates that the first coprocessor needs to send out the event identifier, in the embodiment of the present disclosure, the event identifier is sent in a broadcast manner.

In one implementation of the disclosed embodiment, the first relation instruction may be expressed as:

key words: transmitting a signal

Event identification

For example, SEND1 is a first relation instruction, where SEND is a keyword, 1 is an event identifier, and for example, 1 indicates a user click amount within a set time obtained by statistics.

In the embodiment of the present disclosure, the first coprocessor indicates that, in the dependency relationship, the second coprocessor needs to depend on the execution result of the first coprocessor, and in the first relationship instruction, it indicates that the first coprocessor needs to send out the confirmation information after completing the calculation task before the first relationship instruction, so that the second coprocessor needing to depend on the execution result of the first coprocessor can execute the corresponding calculation instruction according to the confirmation information.

Step 502, according to the first relation instruction, executing at least one first calculation instruction obtained before the first relation instruction.

Step 503, under the condition that the execution of at least one first computation instruction is completed, broadcasting the confirmation information containing the event identifier, so that the second coprocessor receiving the confirmation information resumes acquiring the state of the second computation instruction according to the confirmation information.

In the embodiment of the present disclosure, according to the content included in the first relation instruction, in a case that execution of at least one first calculation instruction is completed, that is, after all corresponding calculation tasks are executed, it is necessary to broadcast the confirmation information including the event identifier according to the content indicated by the first relation instruction, so that the second coprocessor receiving the confirmation information recovers to acquire the state of the second calculation instruction after receiving the second relation instruction according to the confirmation information.

For clarity of explanation of the embodiment of the present disclosure, the embodiment of the present disclosure provides an example, and fig. 6 is a second schematic diagram of sending the acknowledgement information provided by the embodiment of the present disclosure. As shown in FIG. 4, the instructions received by the first coprocessor P1 are CMD1, CMD2, SEND1 and CMD3, wherein CMD1, CMD2 and CMD3 are first computing instructions, SEND1 is a first relation instruction, wherein SEND is the key word "SEND", and 1 is the event identifier. Often, coprocessors have a long pipeline, with each instruction being pipelined, so that the preceding instruction may still be executing at the beginning of the execution of the subsequent instruction. The first coprocessor P1 has received the first compute instructions CMD1 and CMD2 before receiving the first relational instruction SEND1, so the condition for the first coprocessor P1 to broadcast the acknowledge signal is that the first compute instructions CMD1 and CMD2 have completed execution. But the first relational instruction SEND1 does not block execution of a subsequent first compute instruction CMD 3. In the embodiment of the disclosure, the event identifier is sent in a broadcast manner after the first coprocessor completes a corresponding calculation task through calculation by using keywords and the event identifier included in the first relation instruction, so that each second coprocessor receiving the event identifier can confirm the second calculation instruction received after the second relation instruction is recovered to execute the corresponding processor task according to the received second relation instruction, in the disclosure, when a plurality of second coprocessors having a dependency relationship with the first coprocessor are provided, the confirmation information is sent in a broadcast manner, so that the sending efficiency of the first coprocessor is improved, based on the relation instruction and the confirmation information, a synchronization process between the coprocessors is controlled, and the overall operating efficiency of the heterogeneous processor is improved.

It should be noted that, after receiving the second relation instruction, the second coprocessor may continue to receive the second calculation instruction adjacent to the second relation instruction from the control unit to the second coprocessor after receiving the second relation instruction; or the second calculation instruction may be blocked from being acquired from the control unit when the second relation instruction is received, and the second calculation instruction may be acquired from the control unit and executed after the confirmation message is received.

It should be understood that the explanation in step 201-203 also applies to the embodiment of the present disclosure, the principle is the same, and the detailed description in the embodiment of the present disclosure is omitted.

In the data processing method of the embodiment of the disclosure, a first relation instruction is acquired, at least one first calculation instruction acquired before the first relation instruction is executed according to the first relation instruction, and when the execution of the at least one first calculation instruction is completed, confirmation information is broadcasted and sent according to the first relation instruction, so that a second coprocessor receiving the confirmation information recovers the state of acquiring the calculation instruction according to the confirmation information. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.

Based on the foregoing embodiments, the disclosed embodiments provide an implementation manner, fig. 7 is a schematic flow chart of another data processing method provided by the embodiments of the present disclosure, and as shown in fig. 7, steps 201, 301, and 501 include the following steps before:

step 701, obtaining a command queue query request sent by a control unit.

Step 702, querying the remaining storage space contained in the command queue according to the query request.

Step 703, sending the queried indication information of the remaining storage space to the control unit, so that the control unit stores the first relation instruction or the first calculation instruction in the remaining storage space.

The first coprocessor is provided with a corresponding command queue, and the command queue is used for storing instructions sent to the first coprocessor by the control unit, such as a first calculation instruction or a first relation instruction.

In the embodiment of the disclosure, the first coprocessor queries the remaining storage space in the command queue corresponding to the first coprocessor according to the obtained command queue query request sent by the control unit, and sends the queried indication information of the remaining storage space to the control unit, wherein, the indication information can be address information of the storage space, so that the control unit stores the first relation instruction or the first calculation instruction into the remaining storage space according to the indication information, and realizes that the control unit can firstly store the analyzed instruction into a command queue corresponding to the first coprocessor in the process of coordinating the running time between the first coprocessor and the second coprocessor, and realizes that the control unit sends the instruction to the first coprocessor without blocking, the control unit and each coprocessor can run in parallel, and the running efficiency of the heterogeneous processor is improved.

Based on the foregoing embodiments, this embodiment provides a data processing method applied to a second coprocessor in a chip. Fig. 8 is a schematic flowchart of a data processing method according to an embodiment of the disclosure, and as shown in fig. 8, the method includes the following steps:

step 801, acquiring a second relation instruction sent by the control unit.

For the description of the second relation instruction, refer to the explanation in step 201, the principle is the same, and the description in this embodiment is omitted.

Step 802, under the condition of obtaining the second relation instruction, stopping obtaining the second calculation instruction from the command queue corresponding to the second coprocessor.

The command queue is used for storing each instruction acquired from the control unit, and comprises a second relation instruction and a second calculation instruction.

In this embodiment of the present disclosure, after acquiring the second relation instruction, the second coprocessor needs to stop acquiring the second calculation instruction from the corresponding command queue, that is, after acquiring the second relation instruction, the second coprocessor needs to block the instruction from being continuously acquired, so as to wait for the confirmation information.

It should be noted that the second coprocessor stops fetching instructions from the command queue, but the control unit may continue to send instructions to the command queue until there is no storage space in the command queue.

Step 803, the acknowledgement sent by the first coprocessor is listened to.

In one implementation of the embodiment of the present disclosure, the second coprocessor obtains the acknowledgement information sent by the first coprocessor.

In an implementation manner of the embodiment of the present disclosure, the second coprocessor obtains the acknowledgement information sent by the first coprocessor in a broadcast manner.

For the explanation on the sending of the acknowledgement information by the first coprocessor, reference may be made to the foregoing embodiments, which are not described in detail in this embodiment.

And step 804, recovering the state of acquiring the second calculation instruction from the instruction queue according to the confirmation information and the second relation instruction.

In the embodiment of the disclosure, the second coprocessor determines, according to information carried in the received acknowledgement information and used for determining whether the identification information included in the received second relationship instruction matches with the identification information included in the received second relationship instruction, whether the state of obtaining the second calculation instruction from the command queue can be recovered by matching with the second relationship instruction after the acknowledgement information is received by the second coprocessor, and executes the calculation instruction obtained after the second relationship instruction after the execution of the second calculation instruction obtained before the second relationship instruction is completed after the state of obtaining the second calculation instruction from the command queue can be recovered by determining, so that the self-coordination of the running time between the first coprocessor and the second coprocessor is realized, and the overall operating efficiency of the processor is greatly improved.

In the data processing method of the embodiment of the disclosure, the second coprocessor acquires the second relation instruction sent by the control unit, stops acquiring the second calculation instruction from the command queue corresponding to the second coprocessor under the condition of acquiring the second relation instruction, monitors the confirmation information sent by the first coprocessor, and restores the state of acquiring the second calculation instruction from the command queue according to the confirmation information and the second relation instruction, so that the self-coordination of the running time among the coprocessors is realized based on the confirmation information and the second relation instruction, and the overall running efficiency is improved.

Based on the foregoing embodiment, this embodiment provides another data processing method, which illustrates how to coordinate running times between different coprocessors according to relationship information when a second relationship instruction includes an identifier of a first coprocessor, and fig. 9 is a flowchart of the another data processing method provided in this embodiment of the disclosure, and as shown in fig. 9, the method includes the following steps:

step 901, a second relation instruction sent by the control unit is obtained.

The second relation instruction comprises a key word and the identification of the first coprocessor which has a dependency relation with the second coprocessor. The identifier of the first coprocessor may be used to uniquely identify the first coprocessor, and a specific identification method is not limited in this embodiment. The key indicates that the second coprocessor is the receiving party, that is, the second relation instruction indicates that the second coprocessor needs to acquire the acknowledgement information sent by the first coprocessor indicated by the identification.

The explanation in step 201 is also applicable to the embodiment of the present disclosure, and the principle is the same, which is not described again in this embodiment.

In one implementation of the embodiment of the present disclosure, the second relation instruction may be represented as:

key words: receiving a signal

First coprocessor identification sent

For example, RECV from P1 is the second relational instruction, where RECV from is the key and P1 is the first coprocessor id to send acknowledgement.

And step 902, stopping obtaining the second calculation instruction from the command queue corresponding to the second coprocessor under the condition of obtaining the second relation instruction.

As shown in FIG. 4, the receivable commands of the second coprocessor P2 are CMD4, CMD5, RECV from P1 and CMD6, wherein CMD4, CMD5 and CMD6 are second computing commands and RECV to P1 is a second relational command. The second coprocessor P2 has received the second computing instructions CMD4 and CMD5 before the second relationship instruction RECV from P1, wherein CMD4 and CMD5 continue to execute. However, before the second coprocessor P2 receives the acknowledgement from the first coprocessor P1, the second computing instruction CMD6 may be blocked, i.e., the second coprocessor P2 may stop fetching CMD6 from the command queue.

Step 903, listening for the acknowledgement sent by the first coprocessor.

The explanation of steps 901 to 903 may refer to the explanation in the foregoing embodiments, and the principle is the same, which is not described again in this embodiment.

Step 904, resuming obtaining the second computation instruction from the command queue if the identification of the first coprocessor included in the confirmation information matches the identification of the first coprocessor included in the second relationship instruction.

Wherein, the second relation instruction comprises the identification of the coprocessor with the dependency relation.

And the confirmation information comprises the identification of the first coprocessor, the second coprocessor matches the identification of the coprocessor contained in the confirmation information with the identification of the coprocessor contained in the second relation instruction after receiving the confirmation information, and the second calculation instruction is recovered to be obtained from the command queue under the condition that the identifications are matched.

Further, as shown in fig. 4, after receiving the confirmation information, if the identification information matches, the second coprocessor executes the second computing command CMD6 received after the second relationship command RECV from P1 after the second computing commands CMD4 and CMD5 received before the second relationship command RECV from P1 are executed.

Based on the foregoing embodiment, this embodiment provides another data processing method, which illustrates how to coordinate running times between different coprocessors according to relationship information when a relationship instruction includes identification information of an event, and fig. 10 is a flowchart of the another data processing method provided in this embodiment of the disclosure, and as shown in fig. 10, the method includes the following steps:

step 1001, a second relation instruction sent by the control unit is acquired.

In the embodiment of the present disclosure, the second relation instruction includes a setting keyword and an event identifier. Each event identification number can correspond to an event with a specific meaning, and can be planned by a software programmer, for example, the event is as follows: and setting the click quantity of the user in time. The keyword indicates that the second coprocessor is a receiving party, that is, the second relation instruction indicates that the second coprocessor needs to acquire the event identifier, and in the embodiment of the present disclosure, the event identifier is sent in a broadcast manner.

In one implementation of the embodiment of the present disclosure, the second relation instruction may be represented as:

key words: receiving a signal

Event identification

For example, RECV 1 is a second relation instruction, where RECV is a keyword, 1 is an event identifier, and for example, 1 indicates a counted user click amount in a set time.

Step 1002, in the case of obtaining the second relation instruction, stopping obtaining the second calculation instruction from the command queue corresponding to the second coprocessor.

Step 1003, listening for the acknowledgement information sent by the first coprocessor.

The explanation of steps 1001 to 1003 can refer to the explanation in the foregoing embodiment, and the principle is the same, and the details are not repeated in this embodiment.

Step 1004, when the event identifier contained in the confirmation information is matched with the event identifier contained in the first relation instruction, resuming to obtain the second calculation instruction from the command queue.

The second relationship instruction includes an event identifier having a dependency relationship, for example, the event is: the user's click volume within a set time is identified by the number "1".

Further, as shown in fig. 4, after receiving the confirmation information, if the event identifications match, the second coprocessor executes the second computing command CMD6 received after the second relationship command RECV from P1 after the second computing commands CMD4 and CMD5 received before the second relationship command RECV from P1 are executed.

Based on the foregoing embodiments, this embodiment provides an implementation manner, and fig. 11 is a schematic flow chart of another data processing method provided in the embodiment of the present disclosure, as shown in fig. 11, before steps 801, 901, and 1001, the following steps are included:

step 1101, obtaining a command queue query request sent by the control unit.

Step 1102, querying the remaining storage space contained in the command queue according to the query request.

Step 1103, sending the queried indication information of the remaining storage space to the control unit, so that the control unit stores the second relation instruction or the second calculation instruction in the remaining storage space.

The second coprocessor is provided with a corresponding command queue, and the command queue is used for storing instructions sent by the control unit to the second coprocessor, such as a second calculation instruction or a second relation instruction.

In the embodiment of the disclosure, the second coprocessor queries the remaining storage space in the command queue corresponding to the second coprocessor according to the obtained command queue query request sent by the control unit, and sends the queried indication information of the remaining storage space to the control unit, wherein, the indication information can be address information of the storage space, so that the control unit stores the second relation instruction or the second calculation instruction into the remaining storage space according to the indication information, and realizes that the control unit can firstly store the analyzed instruction into a command queue corresponding to the second coprocessor in the process of coordinating the running time between the first coprocessor and the second coprocessor, and realizes that the control unit sends the instruction to the second coprocessor without blocking, the control unit and each coprocessor can run in parallel, and the running efficiency of the heterogeneous processor is improved.

In order to implement the above embodiments, the embodiments of the present disclosure provide a processor chip.

Fig. 12 is a schematic structural diagram of a processor chip according to an embodiment of the present disclosure, where the processor chip is, for example, a heterogeneous processor, and the heterogeneous processor may be applied to a deep learning processor or an accelerator, or a big data processing processor or an accelerator, to implement a computing task.

In one scenario, an accelerator or a processor facing deep learning abstracts each layer of a neural network into an operator, such as convolution, full connection, pooling, activation, and the like, hardware is correspondingly divided into a plurality of modules, such as a convolution module, a full connection module, a pooling module, an activation module, and the like, and a computation task is jointly realized by calling the modules.

In another scenario, an accelerator or a processor for big data processing abstracts each operation in a database query into an operator, such as filtering, connecting, sorting, aggregating, and the like, and hardware is correspondingly implemented by a plurality of modules, such as a filtering module, a connecting module, a sorting module, an aggregating module, and the like, and a computing task is implemented together by calling the modules.

As shown in fig. 12, the processor chip includes a control unit 1201, a first coprocessor 1202 and a second coprocessor 1203.

A control unit 1201, configured to send a first calculation instruction and a first relation instruction to the first coprocessor 1202, and send a second calculation instruction and a second relation instruction to the second coprocessor 1203.

A first coprocessor 1202 configured to perform the data processing method described in the corresponding embodiments of fig. 1-7.

A second coprocessor 1203 is configured to perform the data processing method described in the corresponding embodiments of fig. 8-11.

Specifically, reference may be made to the explanations in the embodiments corresponding to fig. 2 to fig. 11, which have the same principle and are not repeated in this embodiment.

In the processor chip in this embodiment, the first coprocessor generates the confirmation information according to the first relationship instruction acquired from the control unit, and the second coprocessor coordinates the running time between the first coprocessor and the second coprocessor according to the second relationship instruction acquired from the control unit and the confirmation message acquired from the first coprocessor, without having a processor to control the running time between the first coprocessor and the second coprocessor, thereby avoiding the separate overhead of the control unit and improving the overall running efficiency.

In order to implement the above embodiments, the present disclosure provides a data processing apparatus.

Fig. 13 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure, and as shown in fig. 13, the apparatus includes:

the obtaining module 131 is configured to obtain the first relation instruction.

The execution module 132 is configured to execute, according to the first relation instruction, at least one first calculation instruction obtained before the first relation instruction.

A sending module 133, configured to send, according to the first relation instruction, acknowledgement information when execution of the at least one first computation instruction is completed, so that the second coprocessor that receives the acknowledgement information resumes obtaining a state of a second computation instruction according to the acknowledgement information; wherein the second computing instruction is fetched by the second coprocessor after receiving a second relationship instruction.

Further, as an implementation of the embodiments of the present disclosure,

the first relationship instruction includes an identification of a second coprocessor which has a dependency relationship with the first coprocessor; a sending module 133, configured to:

As an implementation manner of the embodiment of the present disclosure, the first relation instruction includes an event identifier; a sending module 133, configured to:

upon completion of execution of the at least one computing instruction, broadcasting acknowledgement information including the event identification.

As an implementation manner of the embodiment of the present disclosure, the apparatus further includes:

the obtaining module 131 is further configured to obtain a command queue query request sent by the control unit;

the query module is used for querying the residual storage space contained in the command queue according to the query request;

the sending module 133 is further configured to send the queried indication information of the remaining storage space to the control unit, so that the control unit stores the first relation instruction or the first calculation instruction in the remaining storage space.

It should be noted that the foregoing explanation of the method embodiment is also applicable to the apparatus of this embodiment, and the principle is the same, and is not repeated in this embodiment.

In the data processing apparatus according to the embodiment of the present disclosure, a first relation instruction is obtained, at least one first calculation instruction obtained before the first relation instruction is executed according to the first relation instruction, and when execution of the at least one first calculation instruction is completed, acknowledgement information is sent according to the first relation instruction, so that a second coprocessor receiving the acknowledgement information resumes, according to the acknowledgement information, a state of obtaining a second calculation instruction of the second coprocessor after the second relation instruction. According to the method and the device, the first co-processing and the second co-processing generate the confirmation information according to the first relation instruction, the self-coordination running time between the co-processors is realized according to the confirmation information, and the overall running efficiency is improved.

In order to implement the above embodiments, the present disclosure provides a data processing apparatus.

Fig. 14 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure, and as shown in fig. 14, the apparatus includes:

the obtaining module 141 is configured to obtain the first relation instruction sent by the control unit.

And the processing module 142 is configured to stop obtaining the second calculation instruction from the command queue corresponding to the second coprocessor when the first relation instruction is obtained.

A monitoring module 143, configured to monitor the acknowledgement sent by the first coprocessor.

The processing module 143 is further configured to recover, according to the confirmation information and the second relation instruction, a state of obtaining a second calculation instruction from the command queue.

Further, in an implementation manner of the embodiment of the present disclosure, the first relation instruction includes an identifier of the first coprocessor; a processing module 143 configured to:

In an implementation manner of the embodiment of the present disclosure, the first relation instruction includes an event identifier; a processing module 143 configured to:

In an implementation manner of the embodiment of the present disclosure, the apparatus further includes:

the obtaining module 141 is further configured to obtain a command queue query request sent by the control unit.

And the query module is used for querying the residual storage space contained in the command queue according to the query request.

And the sending module is used for sending the inquired indication information of the remaining storage space to the control unit so that the control unit stores the second relation instruction or the second calculation instruction in the remaining storage space.

In order to implement the above embodiments, the present embodiment provides an electronic device, including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of the foregoing method embodiments.

To implement the above embodiments, the present embodiment provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of the foregoing method embodiments.

In order to implement the above embodiments, the present embodiment provides a computer program product comprising a computer program which, when executed by a processor, implements the method of the aforementioned method embodiments.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

Fig. 15 is a schematic block diagram of an electronic device 800 provided by an embodiment of the disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 15, the device 800 includes a computing unit 801 which can perform various appropriate actions and processes in accordance with a computer program stored in a ROM (Read-Only Memory) 802 or a computer program loaded from a storage unit 808 into a RAM (Random Access Memory) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The calculation unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An I/O (Input/Output) interface 805 is also connected to the bus 804.

A number of components in the device 800 are connected to the I/O interface 805, including: an input unit 806, such as a keyboard, a mouse, or the like; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, or the like; and a communication unit 809 such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

Computing unit 801 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of the computing Unit 801 include, but are not limited to, a CPU (Central Processing Unit), a GPU (graphics Processing Unit), various dedicated AI (Artificial Intelligence) computing chips, various computing Units running machine learning model algorithms, a DSP (Digital Signal Processor), and any suitable Processor, controller, microcontroller, and the like. The calculation unit 801 executes the respective methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and/or installed onto device 800 via ROM 802 and/or communications unit 809. When loaded into RAM 803 and executed by the computing unit 801, a computer program may perform one or more steps of the data processing method described above. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be realized in digital electronic circuitry, Integrated circuitry, FPGAs (Field Programmable Gate arrays), ASICs (Application-Specific Integrated circuits), ASSPs (Application Specific Standard products), SOCs (System On Chip, System On a Chip), CPLDs (Complex Programmable Logic devices), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an EPROM (Electrically Programmable Read-Only-Memory) or flash Memory, an optical fiber, a CD-ROM (Compact Disc Read-Only-Memory), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a Display device (e.g., a CRT (Cathode Ray Tube) or LCD (Liquid Crystal Display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: LAN (Local Area Network), WAN (Wide Area Network), internet, and blockchain Network.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The Server can be a cloud Server, also called a cloud computing Server or a cloud host, and is a host product in a cloud computing service system, so as to solve the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service ("Virtual Private Server", or simply "VPS"). The server may also be a server of a distributed system, or a server incorporating a blockchain.

It should be noted that artificial intelligence is a subject for studying a computer to simulate some human thinking processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.), and includes both hardware and software technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology mainly comprises a computer vision technology, a voice recognition technology, a natural language processing technology, machine learning/deep learning, a big data processing technology, a knowledge map technology and the like.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

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