阅读说明：本技术 一种基于标准频率信号的时钟生成方法及系统 (Clock generation method and system based on standard frequency signal ) 是由 皮德义 朱炳强 于 2021-08-18 设计创作，主要内容包括：本发明提供一种基于标准频率信号的时钟生成方法及系统,方案包括：首先频率检测器检测输入时钟、参考时钟和标准频率信号的频率,然后判断所述输入时钟、参考时钟和标准频率信号之间的频率关系是否满足预设条件,得到判断结果,最后根据所述判断结果,调整用于生成输出时钟的工作模式,得到输出时钟。本申请利用长期频率稳定的标准频率信号作参考,得到稳定的时钟信号,从而保证了时钟信号的精准度和稳定度。(The invention provides a clock generation method and a system based on standard frequency signals, and the scheme comprises the following steps: firstly, a frequency detector detects the frequencies of an input clock, a reference clock and a standard frequency signal, then judges whether the frequency relation among the input clock, the reference clock and the standard frequency signal meets a preset condition to obtain a judgment result, and finally adjusts a working mode for generating an output clock according to the judgment result to obtain the output clock. The method and the device utilize the standard frequency signal with stable long-term frequency as reference to obtain the stable clock signal, thereby ensuring the accuracy and stability of the clock signal.)

1. A clock generation method based on a standard frequency signal, comprising:

detecting frequencies of an input clock, a reference clock and a standard frequency signal;

judging preset conditions corresponding to the frequency relation among the input clock, the reference clock and the standard frequency signal;

and generating an output clock based on the working mode matched with the preset condition.

2. The clock generation method according to claim 1, wherein the preset condition includes:

a first preset condition, a second preset condition and a third preset condition

The first preset condition is as follows: the value of fin/fgolden satisfies a first preset rule;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule;

the third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

3. The method according to claim 2, wherein generating the output clock based on the operation mode matching the preset condition comprises:

when the preset condition is a first preset condition, generating an output clock by taking the frequency of the input clock as a reference;

when the preset condition is a second preset condition, generating an initial signal by taking the frequency of the reference clock as a reference, and performing frequency correction on the initial signal by adopting the ratio of the value of fgolden/fref to an expected value to obtain an output clock;

and when the preset condition is a third preset condition, outputting a null clock signal and outputting a prompt signal for representing the system fault.

4. The clock generation method according to claim 1, wherein the standard frequency signal is a signal having a predetermined frequency.

5. The method according to claim 1, wherein the reference signal is a signal generated by a crystal oscillator.

6. A clock generation system based on a standard frequency signal, comprising:

a frequency detector for detecting frequencies of the input clock, the reference clock, and the standard frequency signal;

the judger is used for judging preset conditions corresponding to the frequency relation among the input clock, the reference clock and the standard frequency signal;

and the signal generator is used for generating an output clock based on the working mode matched with the preset condition.

7. The clock generation system according to claim 6, wherein the determiner is specifically configured to:

judging whether the frequency relation among the input clock, the reference clock and the standard frequency signal corresponds to a first preset condition, a second preset condition or a third preset condition;

the first preset condition is as follows: the value of fin/fgolden satisfies a first preset rule;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule;

the third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

8. The standard frequency signal based clock generation system of claim 7, wherein the signal generator is configured to:

when the preset condition is a first preset condition, generating an output clock by taking the frequency of the input clock as a reference;

when the preset condition is a second preset condition, generating an initial signal by taking the frequency of the reference clock as a reference, and performing frequency correction on the initial signal by adopting the ratio of the value of fgolden/fref to an expected value to obtain an output clock;

and when the preset condition is a third preset condition, outputting a null clock signal and outputting a prompt signal for representing the system fault.

9. The clock generation system according to claim 8, wherein the signal generator specifically comprises:

a frequency synthesizer and a numerically controlled oscillator;

the frequency synthesizer is used for carrying out frequency discrimination and phase discrimination on the input clock or the reference clock and the output clock of the numerical control oscillator according to a judgment result output by the judger, adjusting a frequency doubling ratio and generating a control signal;

the input end of the numerical control oscillator is connected with the output end of the frequency synthesizer, and the numerical control oscillator is used for generating an output clock according to the control signal output by the frequency synthesizer.

10. The clock generation system according to claim 9, wherein the frequency synthesizer is specifically configured to:

when the preset condition is a first preset condition, performing frequency discrimination and phase discrimination on the input clock and the output clock of the numerically controlled oscillator to generate a first control signal;

when the preset condition is a second preset condition, performing frequency discrimination and phase discrimination on the reference clock and the output clock of the numerically-controlled oscillator, and adjusting a frequency multiplying ratio based on the ratio of the value of fgolden/fref to a desired value to generate a second control signal;

and when the preset condition is a third preset condition, outputting a control signal to be null, and simultaneously outputting a prompt signal for representing the system fault.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a clock generation method and system based on standard frequency signals.

Background

At present, in a high-speed 5G communication network, many links need a precise and stable clock to ensure efficient and high-quality communication of the network, and the precision, accuracy and stability of the clock are all highly required. If the precision, accuracy and stability of the clock are poor, the synchronous operation of the communication network is affected, and the performance of the communication network is degraded.

In the prior art, an input clock and a reference clock are processed by a phase-locked loop to obtain a synchronous output clock. When the frequency of the input clock is stable and within a normal range, the frequency of the input clock is taken as a reference to obtain an output clock; when the frequency of the input clock is deviated, the frequency of the reference clock is taken as a reference to obtain the output clock. When the reference clock is aged and the frequency of the reference clock is deviated, the method can be mistaken for the deviation of the frequency of the input clock, so that the output clock is mistakenly output along with the deviation of the reference clock.

Disclosure of Invention

In view of this, embodiments of the present invention provide a clock generation method and system based on a standard frequency signal, so as to provide an accurate output clock generation scheme.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

a clock generation method based on a standard frequency signal, comprising:

detecting frequencies of an input clock, a reference clock and a standard frequency signal;

judging preset conditions corresponding to the frequency relation among the input clock, the reference clock and the standard frequency signal;

and generating an output clock based on the working mode matched with the preset condition.

Optionally, in the clock generating method based on a standard frequency signal, the preset condition includes:

a first preset condition, a second preset condition and a third preset condition

The first preset condition is as follows: the value of fin/fgolden satisfies a first preset rule;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule;

the third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

Optionally, in the clock generating method based on a standard frequency signal, generating an output clock based on a working mode matched with the preset condition includes:

when the preset condition is a first preset condition, generating an output clock by taking the frequency of the input clock as a reference;

when the preset condition is a second preset condition, generating an initial signal by taking the frequency of the reference clock as a reference, and performing frequency correction on the initial signal by adopting the ratio of the value of fgolden/fref to an expected value to obtain an output clock;

and when the preset condition is a third preset condition, outputting a null clock signal and outputting a prompt signal for representing the system fault.

Optionally, in the clock generating method based on a standard frequency signal, the standard frequency signal is a signal having a predetermined frequency.

Optionally, in the clock generation method based on a standard frequency signal, the reference signal is a signal generated by a crystal oscillator.

A clock generation system based on a standard frequency signal, comprising:

a frequency detector for detecting frequencies of the input clock, the reference clock, and the standard frequency signal;

the judger is used for judging preset conditions corresponding to the frequency relation among the input clock, the reference clock and the standard frequency signal;

and the signal generator is used for generating an output clock based on the working mode matched with the preset condition.

Optionally, in the clock generation system based on the standard frequency signal, the determiner is specifically configured to:

judging whether the frequency relation among the input clock, the reference clock and the standard frequency signal corresponds to a first preset condition, a second preset condition or a third preset condition;

the first preset condition is as follows: the value of fin/fgolden satisfies a first preset rule;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule;

the third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

Optionally, in the clock generating system based on a standard frequency signal, the signal generator is configured to:

when the preset condition is a first preset condition, generating an output clock by taking the frequency of the input clock as a reference;

when the preset condition is a second preset condition, generating an initial signal by taking the frequency of the reference clock as a reference, and performing frequency correction on the initial signal by adopting the ratio of the value of fgolden/fref to an expected value to obtain an output clock;

and when the preset condition is a third preset condition, outputting a null clock signal and outputting a prompt signal for representing the system fault.

Optionally, in the clock generating system based on a standard frequency signal, the signal generator specifically includes:

a frequency synthesizer and a numerically controlled oscillator;

the frequency synthesizer is used for carrying out frequency discrimination and phase discrimination on the input clock or the reference clock and the output clock of the numerical control oscillator according to a judgment result output by the judger, adjusting a frequency doubling ratio and generating a control signal;

the input end of the numerical control oscillator is connected with the output end of the frequency synthesizer, and the numerical control oscillator is used for generating an output clock according to the control signal output by the frequency synthesizer.

Optionally, in the clock generation system based on the standard frequency signal, the frequency synthesizer is specifically configured to:

when the preset condition is a first preset condition, performing frequency discrimination and phase discrimination on the input clock and the output clock of the numerically controlled oscillator to generate a first control signal;

when the preset condition is a second preset condition, performing frequency discrimination and phase discrimination on the reference clock and the output clock of the numerically-controlled oscillator, and adjusting a frequency multiplying ratio based on the ratio of the value of fgolden/fref to a desired value to generate a second control signal;

and when the preset condition is a third preset condition, outputting a control signal to be null, and simultaneously outputting a prompt signal for representing the system fault.

Based on the above technical solution, in the above scheme provided in the embodiment of the present invention, the frequency detector detects the frequencies of the input clock, the reference clock, and the standard frequency signal, then determines whether the frequency relationship among the input clock, the reference clock, and the standard frequency signal satisfies a preset condition, obtains a determination result, and finally adjusts a working mode for generating the output clock according to the determination result, and obtains the output clock. The method and the device utilize the standard frequency signal with stable long-term frequency as reference to obtain the stable clock signal, thereby ensuring the accuracy and stability of the clock signal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a flowchart of a clock generation method based on a standard frequency signal according to an embodiment of the present disclosure;

FIG. 2 is a flowchart of a clock generation method based on a standard frequency signal according to another embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a clock generation system based on a standard frequency signal according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a clock generation system based on a standard frequency signal according to another embodiment of the present application.

Detailed Description

The invention of the present application aims to: the method and the system are simple and generate the clock by using the standard frequency signal, and are used for realizing stable output of the clock, so that the accuracy and the stability of the clock signal are ensured.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, fig. 1 is a flowchart of a clock generation method based on a standard frequency signal according to an embodiment of the present application, where the method includes:

step S101: the frequencies of the input clock, the reference clock, and the standard frequency signal are detected.

In this scheme, the frequencies of the input clock Clkin, the reference clock Clkref, and the standard frequency signal clkgold, which is well known to those skilled in the art, are first detected, and the Golden signal is a signal that is stable for long-term frequencies or a name of the standard frequency signal, that is, a signal having a predetermined fixed frequency.

Step S102: and judging preset conditions corresponding to the frequency relation among the input clock, the reference clock and the standard frequency signal.

In the technical solution disclosed in the embodiment of the present application, in order to ensure that a system applying the method can output an accurate output clock, a plurality of preset conditions may be preset, each condition corresponds to a frequency relationship among the input clock, the reference clock, and the standard frequency signal, after the frequency relationship among the input clock, the reference clock, and the standard frequency signal is obtained, the preset conditions corresponding to the input clock, the reference clock, and the standard frequency signal at the current time may be determined based on the relationships, and the corresponding preset conditions are different, and specific ways for generating the output clock are different.

Step S103: and generating an output clock based on the working mode matched with the preset condition.

In the technical scheme disclosed in the embodiment of the application, different working modes are established in advance according to different preset conditions, and the different working modes are different in the mode of generating the output clock.

In the technical solution disclosed in the embodiment of the present application, the standard frequency signal is a signal with a fixed frequency, and by comparing the frequencies of the input clock, the reference clock and the standard frequency signal, the frequency change states of the input clock and the reference clock can be obtained to determine the working mode for generating the output clock, thereby ensuring the reliability of the generated output clock.

In the technical solution disclosed in this embodiment, the applicant obtains through a large number of experiments, and the preset conditions may include: a first preset condition, a second preset condition and a third preset condition;

the first preset condition is as follows: the value of fin/fgolden meets a first preset rule, and when the frequency relation among the input clock, the reference clock and the standard frequency signal meets a first preset condition, the frequency of the input clock Clkin is stable, and the frequency of the input clock Clkin is within a preset range;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule; when the frequency relation among the input clock, the reference clock and the standard frequency signal satisfies a second preset condition, it indicates that the frequency of the input clock Clkin has a deviation, and the deviation is not within a preset range, but the frequency of the reference clock Clkref does not exceed a preset aging threshold.

The third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule; when the frequency relation among the input clock, the reference clock and the standard frequency signal meets a third preset condition, it is indicated that the frequency of the input clock Clkin is deviated and is not within a preset range, and the frequency of the reference clock Clkref exceeds a preset aging threshold;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

Referring to fig. 2, in the technical solution disclosed in this embodiment of the present application, when the preset condition that the frequency relationship among the input clock, the reference clock, and the standard frequency signal satisfies is different, the operating mode of the system that applies the method to generate the output clock is different, specifically, in the technical solution disclosed in this embodiment, the generating the output clock based on the operating mode matched with the preset condition may specifically include:

and when the preset condition is a first preset condition, indicating that the frequency of the input clock Clkin is within a preset range, and determining that the working mode for generating the output clock is a normal working mode. In the normal working mode, the frequency of the input clock Clkin is taken as a reference to obtain an output clock Clkout;

when the preset condition is a second preset condition, it indicates that the frequency of the input clock Clkin is not within the preset range, but the frequency of the reference clock Clkref does not exceed the aging threshold, the operating mode for generating the output clock is the Holdover mode. In the Holover mode, the frequency of the reference clock Clkref is used as a reference to generate an initial signal, and then the frequency of the initial signal is corrected according to the ratio of the actual value of fgolden/fref to an expected value to obtain an output clock Clkout;

and when the preset condition is a third preset condition, the frequency of the input clock Clkin is not in a preset range, and the frequency of the reference clock Clkref exceeds an aging threshold, so that a system fault is indicated. At this time, the output clock is empty, and a prompt signal for representing system failure is output.

In the technical solution disclosed in this embodiment, the generation manner of the reference signal may be selected based on user requirements, for example, in the technical solution disclosed in this embodiment, the reference signal may be an XO signal, that is, the reference signal may be generated by a crystal oscillator.

In this embodiment, a clock generation system based on a standard frequency signal is disclosed corresponding to the above method, and the specific working contents of each component in the system please refer to the clock generation system based on a standard frequency signal in the above method embodiment.

Referring to fig. 3, the system may include: a frequency detector 100, a determiner 200, and a signal generator 300.

Wherein, the input terminals of the frequency detector 100 include a first input terminal, a second input terminal and a third input terminal, the first input terminal, the second input terminal and the third input terminal are respectively used for obtaining an input clock Clkin, a reference clock Clkref and a standard frequency signal Clkgolden, and the frequency detector 100 corresponds to the step S101 of the above method for detecting the frequencies of the input clock, the reference clock and the standard frequency signal;

an input end of the determiner 200 is connected to an output end of the frequency detector 100, and is configured to obtain frequencies of the input clock, the reference clock, and the standard frequency signal output by the frequency detector 100, corresponding to step S102 in the method, after obtaining the frequencies of the input clock, the reference clock, and the standard frequency signal, the determiner 200 is configured to determine a preset condition corresponding to a frequency relationship among the input clock, the reference clock, and the standard frequency signal, and an output end of the determiner 200 is configured to output a determination result corresponding to the determined preset condition;

the first input terminal, the second input terminal and the third input terminal of the signal generator 300 are respectively used for obtaining the input clock Clkin, the reference clock Clkref and the standard frequency signal Clkgolden, the fourth input terminal of the signal generator 300 is connected to the output terminal of the determiner 200, and the signal generator 300 corresponds to step S103 of the above method for generating an output clock based on an operation mode matching with the preset condition.

Similar to the method, in the clock generation system disclosed in the embodiment of the present application, the frequency detector detects frequencies of the input clock, the reference clock, and the standard frequency signal, the determiner determines whether a frequency relationship among the input clock, the reference clock, and the standard frequency signal satisfies a preset condition to obtain a determination result, and the signal generator adjusts a working mode of the signal generator according to the determination result to obtain an output clock. The method and the device utilize the standard frequency signal with stable long-term frequency as reference to obtain the stable clock signal, thereby ensuring the accuracy and stability of the clock signal.

Corresponding to the above method, when determining the preset condition corresponding to the frequency relationship between the input clock, the reference clock and the standard frequency signal, the determiner 200 is specifically configured to:

judging whether the frequency relation among the input clock, the reference clock and the standard frequency signal corresponds to a first preset condition, a second preset condition or a third preset condition;

the first preset condition is as follows: the value of fin/fgolden satisfies a first preset rule;

the second preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value satisfies a second preset rule;

the third preset condition is as follows: the value of fin/fgolden does not satisfy a first preset rule, and the ratio of the value of fgolden/fref to the expected value does not satisfy a second preset rule;

wherein fin represents a frequency of the input clock, fref represents a frequency of the reference clock, and fgolden represents a frequency of the standard frequency signal.

Corresponding to the above method, the signal generator 300 is configured to:

when the preset condition is a first preset condition, generating an output clock by taking the frequency of the input clock as a reference;

when the preset condition is a second preset condition, generating an initial signal by taking the frequency of the reference clock as a reference, and performing frequency correction on the initial signal by adopting the ratio of the value of fgolden/fref to an expected value to obtain an output clock;

and when the preset condition is a third preset condition, outputting a null clock signal and outputting a prompt signal for representing the system fault.

In the technical solution disclosed in the embodiment of the present application, the specific structure of the signal generator may be set according to the user requirement, for example, referring to fig. 4, in the technical solution disclosed in the embodiment of the present application, the signal generator may be composed of two parts: one part is a frequency synthesizer 301, and the other part is a numerically controlled oscillator 302;

a first input end, a second input end, and a third input end of the frequency synthesizer 301 are respectively configured to obtain the input clock Clkin, the reference clock Clkref, and the standard frequency signal Clkgolden, a fourth input end of the frequency synthesizer 301 is connected to the output end of the determiner 200, a fifth input end of the frequency synthesizer 301 is connected to the output end of the dco 302, and the frequency synthesizer 301 is specifically configured to perform frequency and phase discrimination on the input clock or the reference clock and an output clock of the dco according to a determination result output by the determiner, and adjust a frequency doubling ratio to generate a control signal;

it should be noted that: the frequency multiplier ratio of the frequency synthesizer 301 is denoted by N and the ratio of the actual value to the desired value of fgolden/fref is denoted by M. When the judgment result indicates that the frequency of the input clock Clkin is not within the preset range but the frequency of the reference clock Clkref does not exceed the preset aging threshold, the frequency doubling ratio of the frequency synthesizer 301 needs to be adjusted to N/M. When the other determination results, the frequency multiplying ratio of the frequency synthesizer 301 may be kept unchanged.

The input end of the digital controlled oscillator 302 is connected to the output end of the frequency synthesizer 301, and the digital controlled oscillator 302 is configured to generate an output clock according to the control signal output by the frequency synthesizer 301.

Corresponding to the above method, the frequency synthesizer 301 is specifically configured to:

when the preset condition is a first preset condition, performing frequency discrimination and phase discrimination on the input clock and the output clock of the numerically controlled oscillator to generate a first control signal;

when the preset condition is a second preset condition, performing frequency discrimination and phase discrimination on the reference clock and the output clock of the numerically-controlled oscillator, and adjusting a frequency multiplying ratio based on the ratio of the value of fgolden/fref to a desired value to generate a second control signal;

and when the preset condition is a third preset condition, outputting a control signal to be null, and simultaneously outputting a prompt signal for representing the system fault.

Corresponding to the system, the application also discloses electronic equipment applying the system, and the electronic equipment can be a mobile phone, a computer and the like.

For convenience of description, the above system is described with the functions divided into various modules, which are described separately. Of course, the functionality of the various modules may be implemented in the same one or more software and/or hardware implementations of the invention.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.