阅读说明：本技术 一种确定硅片导电类型的方法 (Method for determining conductivity type of silicon wafer ) 是由 魏星 李名浩 薛忠营 于 2021-08-06 设计创作，主要内容包括：本申请公开了一种确定硅片导电类型的方法。所述方法包括：测量所述硅片的电阻率,以得到第一电阻率；将所述硅片在空气中放置预设时间；放置预设时间之后再次测量所述硅片的电阻率,以得到第二电阻率；通过比较所述第一电阻率和所述第二电阻率,判断所述硅片的导电类型。所述方法对于高电阻率(高于500ohm～(-cm))可以快速准确的判断硅片导电类型,测试结果准确,操作简单,对设备要求低,成本低。(The application discloses a method for determining the conductivity type of a silicon wafer. The method comprises the following steps: measuring the resistivity of the silicon wafer to obtain a first resistivity; placing the silicon wafer in the air for a preset time; after the silicon wafer is placed for a preset time, measuring the resistivity of the silicon wafer again to obtain a second resistivity; and judging the conductivity type of the silicon wafer by comparing the first resistivity with the second resistivity. The method is for high resistivity (above 500 ohm) ‑cm ) The method can quickly and accurately judge the conductivity type of the silicon wafer, and has the advantages of accurate test result, simple operation, low requirement on equipment and low cost.)

1. A method of determining the conductivity type of a silicon wafer, the method comprising:

measuring the resistivity of the silicon wafer to obtain a first resistivity;

placing the silicon wafer in the air for a preset time;

after the silicon wafer is placed for a preset time, measuring the resistivity of the silicon wafer again to obtain a second resistivity;

and judging the conductivity type of the silicon wafer by comparing the first resistivity with the second resistivity.

2. The method of claim 1, wherein determining the conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity comprises:

if the first resistivity is smaller than the second resistivity, the silicon wafer is of an N type;

and if the first resistivity is greater than the second resistivity, the silicon wafer is of a P type.

3. The method of claim 1, wherein prior to obtaining the first resistivity, the method further comprises:

and carrying out rapid thermal treatment on the silicon wafer to remove the thermal donor in the silicon wafer.

4. The method for determining the conductivity type of the silicon wafer as claimed in claim 3, wherein the rapid thermal treatment is carried out at a temperature ranging from 750 ℃ to 1250 ℃ for a time ranging from 30 s to 50 s.

5. The method of claim 1, wherein the first resistivity and the second resistivity of the silicon wafer are measured by a straight-row four-probe.

6. The method for determining the conductivity type of the silicon wafer as claimed in claim 1, wherein the preset time is in the range of 1h-168 h.

7. According to claimThe method for determining the conductivity type of the silicon wafer is characterized in that the resistivity of the silicon wafer is higher than 500ohm^-cmThe silicon wafer of (1).

8. The method of determining the conductivity type of a silicon wafer according to claim 1, wherein the silicon wafer is a monocrystalline silicon wafer.

9. The method for determining the conductivity type of the silicon wafer as claimed in claim 1, wherein the silicon wafer is left in the air for a predetermined time to allow the surface of the silicon wafer to undergo natural oxidation and/or chemisorption.

Technical Field

The application relates to the field of semiconductors, in particular to a method for determining the conductivity type of a silicon wafer.

Background

Single crystal silicon grown by the czochralski method is widely used in the manufacture of semiconductor electronic devices, and silicon crystals of different resistivities can be grown by doping. For some devices such asAdvanced wireless communication applications, Insulated Gate Bipolar Transistors (IGBTs) and low power, low leakage devices require silicon wafers with very high resistivity (over 500 ohm)^-cm). The silicon chip with high resistance value is beneficial to reducing the influence of parasitic capacitance between devices, the devices can be more densely accumulated on the surface of the silicon chip, and meanwhile, the signal transmission loss between the devices can be reduced.

High-resistance single crystal silicon is obtained by doping a small amount of dopant or by undoped. The silicon wafer has high resistivity and low carrier concentration (1E11-1E13 atom/cm)³) It becomes difficult to determine the conductivity type of the carrier, and therefore, the determination of the conductivity type needs to be determined through measurement. However, the existing methods for judging the conductivity type of the silicon wafer are only suitable for low-resistance silicon wafers and have the problems of inconvenient operation, unreliable test results and the like.

Therefore, improvements are required to solve the above problems.

Disclosure of Invention

In order to solve the problems in the prior art, the application provides a method for determining the conductivity type of a silicon wafer, which comprises the following steps:

measuring the resistivity of the silicon wafer to obtain a first resistivity;

placing the silicon wafer in the air for a preset time;

after the silicon wafer is placed for a preset time, measuring the resistivity of the silicon wafer again to obtain a second resistivity;

and judging the conductivity type of the silicon wafer by comparing the first resistivity with the second resistivity.

Optionally, the determining the conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity includes:

if the first resistivity is smaller than the second resistivity, the silicon wafer is of an N type;

and if the first resistivity is greater than the second resistivity, the silicon wafer is of a P type.

Optionally, before obtaining the first resistivity, the method further comprises:

and carrying out rapid thermal treatment on the silicon wafer to remove the thermal donor in the silicon wafer.

Optionally, the rapid thermal treatment is performed at a temperature ranging from 750 ℃ to 1250 ℃ for a time ranging from 30 s to 50 s.

Optionally, the first resistivity and the second resistivity of the silicon wafer are measured by a straight row four probe.

Optionally, the preset time ranges from 1h to 168 h.

Optionally, the silicon wafer has a resistivity higher than 500ohm^-cmThe silicon wafer of (1).

Optionally, the silicon wafer is a monocrystalline silicon wafer.

Optionally, the silicon wafer is placed in the air for a preset time, so that the surface of the silicon wafer is subjected to natural oxidation and/or chemical adsorption.

In order to solve the technical problems existing at present, the application provides a method for determining the conduction type of a silicon wafer. The method is for high resistivity (above 500 ohm)^-cm) The method can quickly and accurately judge the conductivity type of the silicon wafer, and has the advantages of accurate test result, simple operation, low requirement on equipment and low cost.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps. In the drawings, there is shown in the drawings,

FIG. 1 is a schematic flow chart illustrating a method for determining the conductivity type of a silicon wafer according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a surface state of a silicon wafer according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating the resistivity change of silicon wafers of different conductivity types after being left for a predetermined time period according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present application.

It is to be understood that the present application is capable of implementation in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

The current commonly used methods for judging the conductivity type of the silicon wafer are a cold-hot probe method and a surface photovoltage method.

The cold and hot probe method is characterized in that two metal probes with different temperatures are pressed at different positions on the surface of a silicon wafer by utilizing the principle of thermoelectric effect, a galvanometer (or a digital voltmeter) is externally connected between the two probes, and the conductivity type can be determined according to the direction of temperature difference current (or temperature difference voltage) caused by the temperature difference existing at two contact points. The contact between the probe and the silicon wafer is not easy to control, and the measurement operation is inconvenient. For high resistivity silicon wafers, the test results are unreliable.

The surface photovoltage method is characterized in that non-equilibrium carriers are generated when a silicon sample is irradiated by light, the surface of the sample changes relative to the potential in a body, and the conductivity type can be judged according to the surface potential difference before and after the light irradiation. The presence of static charges or damage layers on the sample surface can affect the test and require special testing equipment.

In addition, there are other methods for determining the conductivity type of a silicon wafer, and a determination device and a tester based on the determination method, for example, if a silicon wafer to be measured is selected and the actual resistance value of the silicon wafer is measured, the measured actual resistance value of the silicon wafer is compared with a set resistance threshold, if the actual resistance value is higher than the resistance threshold, the silicon wafer is a P-type silicon wafer, and if the actual resistance value is lower than the resistance threshold, the silicon wafer is an N-type silicon wafer. However, the above device and the above method cannot be used for judging the resistance value of the N-type silicon wafer exceeding 200 Ω and the resistance value of the P-type silicon wafer below 5000 Ω.

In view of the above problem, the present application provides a method for determining the conductivity type of a silicon wafer, as shown in fig. 1, the method comprising:

step S1: measuring the resistivity of the silicon wafer to obtain a first resistivity;

step S2: placing the silicon wafer in the air for a preset time;

step S3: after the silicon wafer is placed for a preset time, measuring the resistivity of the silicon wafer again to obtain a second resistivity;

step S4: and judging the conductivity type of the silicon wafer by comparing the first resistivity with the second resistivity.

In order to solve the technical problems existing at present, the application provides a method for determining the conduction type of a silicon wafer. The method is for high resistivity (above 500 ohm)^-cm) The method can quickly and accurately judge the conductivity type of the silicon wafer, and has the advantages of accurate test result, simple operation, low requirement on equipment and low cost.

The earphone of the present application is described in detail below with reference to the accompanying drawings, wherein fig. 1 is a schematic flow chart of a method for determining a conductive type of a silicon wafer according to an embodiment of the present application.

The method is applicable to a silicon wafer of single crystal silicon in the present application, but it should be noted that the method is also applicable to other types of silicon wafers, and is not limited herein.

Wherein, the method is suitable for the resistivity higher than 500ohm^-cmCompared with the prior art, the silicon chip has wider application range.

In the step S1, a silicon wafer is prepared and selected.

In one example of the present application, single crystal silicon is grown by the Czochralski method. Specifically, the semiconductor crystal growth device comprises a furnace body, a crucible is arranged in the furnace body, a heater for heating the crucible is arranged outside the crucible, silicon melt is contained in the crucible, the crucible is composed of a graphite crucible and a quartz crucible sleeved in the graphite crucible, the graphite crucible receives the heating of the heater to melt polycrystalline silicon materials in the quartz crucible to form the silicon melt, and the high-resistance monocrystalline silicon can be grown by controlling the amount of a dopant put into the crucible. Wherein each quartz crucible is used for one batch semiconductor growth process and each graphite crucible is used for multiple batch semiconductor growth processes.

And a pulling device is arranged at the top of the furnace body, and the seed crystal is pulled out of the silicon crystal rod from the liquid level of the silicon melt under the driving of the pulling device.

After obtaining the silicon crystal bar, the silicon crystal bar is cut into silicon wafers in a predetermined thickness.

In step S1, a silicon wafer is selected and the resistivity of the silicon wafer is measured to obtain a first resistivity.

The resistivity of the silicon wafer was measured using an inline four probe in this step. In an embodiment of the application, the resistivity of the silicon wafer can be measured by using a straight-line four-probe according to the standard GB/T1552 to obtain the first resistivity.

Optionally, in an embodiment of the present application, before measuring the first resistivity, the method further includes performing a rapid thermal process on the silicon wafer to remove thermal donors in the silicon wafer.

The Czochralski silicon is led out through the seed crystal, a large number of thermal donors are generated in the subsequent cooling process, the carrier concentration of the n-type monocrystalline silicon is increased, the resistivity is reduced, the carrier concentration of the p-type silicon is compounded, the resistivity is increased, and finally the p-type silicon can be converted into n-type silicon. The oxygen of the silicon wafer mainly comes from a quartz crucible, and oxygen impurities can generate a donor effect when subjected to low-temperature heat treatment. In order to remove the donor effect, a rapid thermal processing process is performed after selecting a silicon wafer to remove the thermal donor.

The temperature range of the rapid heat treatment is 750-1250 ℃, and the time range is 30-50 s. It should be noted that the temperature and time of the rapid thermal treatment are not limited to the above ranges, and can be selected according to actual needs.

In the step S2, the silicon wafer is left in the air for a preset time.

The preset time is not limited to a specific value or a range of values, and can be selected according to actual needs.

In one embodiment of the present application, the silicon wafer is placed in the air for 1h-168h (1h-1 week) to allow the surface of the silicon wafer to undergo natural oxidation and/or chemisorption.

Specifically, as shown in fig. 2, when the silicon wafer is placed in the air, natural oxidation and chemical adsorption occur, the surface of the silicon wafer is negatively charged, the surface of the N-type silicon wafer is in a depletion state, and the resistivity measured by the straight-line four probes is increased; and the surface of the P-type silicon wafer is in an accumulation state, and the resistivity measured by the straight-line four probes is reduced. Based on the mechanism, the conductivity type of the silicon chip can be judged according to the resistivity measured by four straight-line probes arranged in the air.

In the step S3, the resistivity of the silicon wafer is measured again after the silicon wafer is placed for a preset time to obtain a second resistivity.

Specifically, the resistivity of the silicon wafer was measured using an inline four-probe after being left for a preset time in this step. In an embodiment of the application, the resistivity of the silicon wafer can be measured by using a straight-line four-probe according to the standard GB/T1552 to obtain the second resistivity.

The conductive type of the silicon wafer is judged by comparing the first resistivity and the second resistivity.

The change trends of the resistivities of the N-type silicon wafer and the P-type silicon wafer along with the increase of the standing time are shown in fig. 3, as can be seen from fig. 3, the initial resistivities of the N-type silicon wafer and the P-type silicon wafer are the same, the surface of the N-type silicon wafer is in a depletion state along with the increase of the standing time, the resistivity is gradually increased and tends to be stable along with the increase of the standing time, and the surface of the P-type silicon wafer is in an accumulation state and the resistivity is gradually reduced and tends to be stable along with the increase of the standing time.

Taking the standing time of 5h as an example, the resistivity changes of the N-type silicon wafer and the P-type silicon wafer are shown in the following table:

as can be seen from the above table, the resistivity of the P-type silicon wafer decreases after the P-type silicon wafer is placed for a preset time, and the resistivity of the N-type silicon wafer increases after the N-type silicon wafer is placed for a preset time, so that the type of the silicon wafer can be determined by the change in the resistivity before and after the P-type silicon wafer is placed for the preset time.

Specifically, the judging the conductivity type of the silicon wafer by comparing the first resistivity with the second resistivity includes:

if the first resistivity is smaller than the second resistivity, the silicon wafer is of an N type;

and if the first resistivity is greater than the second resistivity, the silicon wafer is of a P type.

The method for determining the conductive type of the silicon wafer comprises the steps of placing the silicon wafer in the air, measuring a first resistivity and a second resistivity before and after placing, and comparing the first resistivity and the second resistivity to obtain the conductive type of the silicon wafer. The method is for high resistivity (above 500 ohm)^-cm) The method can quickly and accurately judge the conductivity type of the silicon wafer, and has the advantages of accurate test result, simple operation, low requirement on equipment and low cost.

Although the example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above-described example embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the present application, various features of the present application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present application should not be construed to reflect the intent: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.