阅读说明：本技术 一种P-GaN栅增强型HEMT器件及其制备方法 (P-GaN gate enhanced HEMT device and preparation method thereof ) 是由 李祥东 韩占飞 刘苏杭 张进成 郝跃 于 2021-08-06 设计创作，主要内容包括：本发明公开了一种P-GaN栅增强型HEMT器件及其制备方法,制备方法包括：在衬底层上依次生长缓冲层、沟道层、势垒层和P-GaN层；在P-GaN上半层注入氢原子,形成高阻GaN层；在高阻GaN层的上形成TiN金属层；在TiN金属层的上形成栅极区域,刻蚀掉栅极区域外的TiN金属层、高阻GaN层和P-GaN层直至势垒层的上表面；在TiN金属层和势垒层的上及P-GaN层和高阻GaN层两侧形成钝化层；在钝化层的上表面的两端形成N离子注入区；刻蚀掉栅极区域的钝化层直至TiN金属层的上表面,在TiN金属层的上沉积栅金属形成栅极；分别刻蚀掉漏极区域的钝化层、势垒层和部分沟道层,并分别在沟道层上形成漏极、源极。本发明制备得到了可用的MISP-GaN栅结构,在有效提高器件击穿电压的同时抑制阈值电压漂移。(The invention discloses a P-GaN gate enhanced HEMT device and a preparation method thereof, wherein the preparation method comprises the following steps: sequentially growing a buffer layer, a channel layer, a barrier layer and a P-GaN layer on the substrate layer; injecting hydrogen atoms into the upper half layer of the P-GaN layer to form a high-resistance GaN layer; forming a TiN metal layer on the high-resistance GaN layer; forming a gate region on the TiN metal layer, and etching away the TiN metal layer, the high-resistance GaN layer and the P-GaN layer outside the gate region until reaching the upper surface of the barrier layer; forming passivation layers on the TiN metal layer and the barrier layer and on the P-GaN layer and the two sides of the high-resistance GaN layer; forming N ion injection regions at two ends of the upper surface of the passivation layer; etching the passivation layer of the gate region until reaching the upper surface of the TiN metal layer, and depositing gate metal on the TiN metal layer to form a gate; and respectively etching the passivation layer, the barrier layer and part of the channel layer in the drain region, and respectively forming a drain electrode and a source electrode on the channel layer. The MISP-GaN gate structure prepared by the invention can effectively improve the breakdown voltage of the device and inhibit the drift of the threshold voltage.)

1. A preparation method of a P-GaN gate enhanced HEMT device is characterized by comprising the following steps:

step 1: sequentially growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on the substrate layer;

step 2: injecting hydrogen atoms into the upper half layer of the P-GaN layer to form a high-resistance GaN layer; wherein, the implantation depth of the hydrogen atoms is less than the thickness of the P-GaN layer;

and step 3: depositing TiN metal on the upper surface of the high-resistance GaN layer to form a TiN metal layer;

and 4, step 4: forming a gate region on the upper surface of the TiN metal layer, and etching away the TiN metal layer, the high-resistance GaN layer and the P-GaN layer outside the gate region until reaching the upper surface of the barrier layer;

and 5: depositing dielectric materials on the upper surfaces of the TiN metal layer and the barrier layer and on the two sides of the P-GaN layer and the high-resistance GaN layer to form a passivation layer;

step 6: injecting N ions into two ends of the upper surface of the passivation layer respectively to form N ion injection regions; wherein the implantation depth of the N ion implantation region comprises the passivation layer, the barrier layer and the channel layer;

and 7: forming the grid electrode region on the upper surface of the passivation layer on the high-resistance GaN layer, etching the passivation layer of the grid electrode region until reaching the upper surface of the TiN metal layer, and depositing grid metal on the upper surface of the TiN metal layer to form a grid electrode;

and 8: forming a drain region and a source region on the upper surface of the passivation layer adjacent to the N ion implantation region, respectively, etching away the passivation layer, the barrier layer and a portion of the channel layer in the drain region, depositing a drain metal on the channel layer to form a drain electrode, etching away the passivation layer, the barrier layer and a portion of the channel layer in the source region, and depositing a source metal on the channel layer to form a source electrode.

2. The method for manufacturing a P-GaN gate enhanced HEMT device according to claim 1, wherein the step 1 of sequentially growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on a substrate layer comprises:

sequentially growing a high-resistance GaN buffer layer with the thickness of 800 nm-6000 nm, a non-doped GaN channel layer with the thickness of 50 nm-500 nm and Al with the thickness of 10 nm-40 nm on the substrate layer by utilizing the MOCVD technology_xGa_1-xN barrier layer with thickness of 50-500 nm and Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3A P-GaN layer of (1); wherein x is 0.1 to 0.5.

3. The method for manufacturing a P-GaN gate enhanced HEMT device according to claim 1, wherein the step 1 of sequentially growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on a substrate layer comprises:

sequentially growing a high-resistance AlGaN buffer layer with the thickness of 800nm to 6000nm, a non-doped GaN channel layer with the thickness of 50nm to 500nm and Al with the thickness of 10nm to 40nm on the substrate layer by utilizing the MOCVD technology_xGa_1-xN barrier layer with thickness of 50-500 nm and Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3A P-GaN layer of (1); wherein x is 0.1 to 0.5.

4. The method for manufacturing a P-GaN gate enhanced HEMT device according to claim 1, wherein said step 2 of implanting hydrogen atoms into the upper half layer of the P-GaN layer to form a high resistance GaN layer comprises:

implanting hydrogen atoms into the upper half layer of the P-GaN layer by using an ion implantation process or a plasma treatment process, wherein the implantation depth of the hydrogen atoms is 5-100 nm, and the implantation concentration is 10¹⁸cm^-3～10²⁰cm^-3And forming a high-resistance GaN layer with the thickness of 5 nm-100 nm.

5. The method for manufacturing a P-GaN gate enhanced HEMT device according to claim 1, wherein said step 3 of depositing TiN metal on the upper surface of said high resistance GaN layer to form a TiN metal layer comprises:

and sputtering and depositing TiN metal on the upper surface of the high-resistance GaN layer by utilizing a PVD process to form the TiN metal layer with the thickness of 5 nm-300 nm.

6. The method for manufacturing a P-GaN gate enhanced HEMT device according to claim 1, wherein said step 5 of depositing a dielectric material on the upper surfaces of said TiN metal layer and said barrier layer and on both sides of said P-GaN layer and said high resistance GaN layer to form a passivation layer comprises:

and depositing dielectric materials on the upper surfaces of the TiN metal layer and the barrier layer and on the two sides of the P-GaN layer and the high-resistance GaN layer by using a PEALD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition) or ECVD (electron cyclotron resonance deposition) or LPCVD (low pressure chemical vapor deposition) process to form the passivation layer with the thickness of 50 nm-400 nm.

7. The method for manufacturing a P-GaN gate-enhanced HEMT device according to claim 1, wherein said dielectric material comprises SiO₂Or SiN or AlON or Al₂O₃。

8. A P-GaN gate enhanced HEMT device, comprising:

the substrate layer is sequentially arranged on the buffer layer, the channel layer and the barrier layer on the substrate layer;

a Mg-doped P-GaN layer on a portion of the barrier layer;

the high-resistance GaN layer is positioned in the P-GaN layer; the high-resistance GaN layer is formed by injecting hydrogen atoms into the upper half layer of the P-GaN layer, and the thickness of the high-resistance GaN layer is smaller than that of the P-GaN layer;

the TiN metal layer is positioned on the high-resistance GaN layer;

the passivation layer is positioned on the TiN metal layer and the barrier layer and on two sides of the P-GaN layer and the high-resistance GaN layer;

n ion implantation regions located at two ends of the device; wherein the implantation depth of the N ion implantation region comprises the passivation layer, the barrier layer and the channel layer;

the grid electrode penetrates through the passivation layer and is positioned on the TiN metal layer;

the drain electrode and the source electrode respectively penetrate through the passivation layer, the barrier layer and part of the channel layer adjacent to the N ion implantation area and are positioned on the channel layer;

the P-GaN gate enhanced HEMT device is prepared by the preparation method of the P-GaN gate enhanced HEMT device according to any one of claims 1-7.

9. The P-GaN gate-enhanced HEMT device of claim 8,the thickness of the P-GaN layer is 50 nm-500 nm, and the Mg doping concentration is 10¹⁸cm^-3～10²⁰cm^-3。

10. The P-GaN gate-enhanced HEMT device of claim 8, wherein said high-resistance GaN layer formed by hydrogen atom implantation has a thickness of 5 to 100 nm; wherein, the implantation depth of hydrogen atoms is 5nm to 100nm, and the implantation concentration is 10¹⁸cm^-3～10²⁰cm^-3。

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a P-GaN gate enhanced HEMT device and a preparation method thereof.

Background

The GaN High Electron Mobility Transistor (HEMT) has the advantages of wide band gap, High breakdown field strength, High Electron Mobility, High energy conversion efficiency and the like, and has great potential in High-frequency and High-power electronic power application.

The conventional AlGaN/GaN high electron mobility transistor is a normally-on device, however, in practical application scenarios, an enhancement type HEMT device is often required in consideration of practical cost, fault protection and other factors. After decades of development, the current method for manufacturing the enhancement type HEMT device mainly comprises a trench gate, fluorine ion implantation, a P-GaN gate and the like, wherein the P-GaN gate enhancement type HEMT device is commercialized and has a wide development prospect.

However, in the current practical application, the forward breakdown voltage of the gate of the device adopting the P-GaN gate is low, which limits the gate driving voltage swing of the device and directly causes high conduction loss. In addition, higher quality dielectric deposition on GaN is not achieved, and therefore a usable MIS P-GaN gate structure cannot be prepared.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a P-GaN gate enhanced HEMT device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

an embodiment of the invention provides a method for manufacturing a P-GaN gate enhanced HEMT device, comprising the following steps:

step 1: sequentially growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on the substrate layer;

step 2: injecting hydrogen atoms into the upper half layer of the P-GaN layer to form a high-resistance GaN layer; wherein, the implantation depth of the hydrogen atoms is less than the thickness of the P-GaN layer;

and step 3: depositing TiN metal on the upper surface of the high-resistance GaN layer to form a TiN metal layer;

and 4, step 4: forming a gate region on the upper surface of the TiN metal layer, and etching away the TiN metal layer, the high-resistance GaN layer and the P-GaN layer outside the gate region until reaching the upper surface of the barrier layer;

and 5: depositing dielectric materials on the upper surfaces of the TiN metal layer and the barrier layer and on the two sides of the P-GaN layer and the high-resistance GaN layer to form a passivation layer;

step 6: injecting N ions into two ends of the upper surface of the passivation layer respectively to form N ion injection regions; wherein the implantation depth of the N ion implantation region comprises the passivation layer, the barrier layer and the channel layer;

and 7: forming the grid electrode region on the upper surface of the passivation layer on the high-resistance GaN layer, etching the passivation layer of the grid electrode region until reaching the upper surface of the TiN metal layer, and depositing grid metal on the upper surface of the TiN metal layer to form a grid electrode;

and 8: forming a drain region and a source region on the upper surface of the passivation layer adjacent to the N ion implantation region, respectively, etching away the passivation layer, the barrier layer and a portion of the channel layer in the drain region, depositing a drain metal on the channel layer to form a drain electrode, etching away the passivation layer, the barrier layer and a portion of the channel layer in the source region, and depositing a source metal on the channel layer to form a source electrode.

In one embodiment of the present invention, the step 1 of growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on a substrate layer in sequence includes:

sequentially growing a high-resistance GaN buffer layer with the thickness of 800 nm-6000 nm, a non-doped GaN channel layer with the thickness of 50 nm-500 nm and Al with the thickness of 10 nm-40 nm on the substrate layer by utilizing the MOCVD technology_xGa_1-xN barrier layer with thickness of 50-500 nm and Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3A P-GaN layer of (1); wherein x is 0.1 to 0.5.

In one embodiment of the present invention, the step 1 of growing a buffer layer, a channel layer, a barrier layer and a Mg-doped P-GaN layer on a substrate layer in sequence includes:

sequentially growing a high-resistance AlGaN buffer layer with the thickness of 800nm to 6000nm, a non-doped GaN channel layer with the thickness of 50nm to 500nm and Al with the thickness of 10nm to 40nm on the substrate layer by utilizing the MOCVD technology_xGa_1-xN barrier layer with thickness of 50-500 nm and Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3A P-GaN layer of (1); wherein x is 0.1 to 0.5.

In an embodiment of the present invention, the step 2 of implanting hydrogen atoms into the upper half layer of the P-GaN layer to form the high resistance GaN layer includes:

implanting hydrogen atoms into the upper half layer of the P-GaN layer by using an ion implantation process or a plasma treatment process, wherein the implantation depth of the hydrogen atoms is 5-100 nm, and the implantation concentration is 10¹⁸cm^-3～10²⁰cm^-3And forming a high-resistance GaN layer with the thickness of 5 nm-100 nm.

In one embodiment of the present invention, the step 3 of depositing TiN metal on the upper surface of the high resistance GaN layer to form a TiN metal layer includes:

and sputtering and depositing TiN metal on the upper surface of the high-resistance GaN layer by utilizing a PVD process to form the TiN metal layer with the thickness of 5 nm-300 nm.

In an embodiment of the present invention, the step 5 of depositing a dielectric material on the upper surfaces of the TiN metal layer and the barrier layer and on both sides of the P-GaN layer and the high resistance GaN layer to form a passivation layer includes:

and depositing dielectric materials on the upper surfaces of the TiN metal layer and the barrier layer and on the two sides of the P-GaN layer and the high-resistance GaN layer by using a PEALD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition) or ECVD (electron cyclotron resonance deposition) or LPCVD (low pressure chemical vapor deposition) process to form the passivation layer with the thickness of 50 nm-400 nm.

In one embodiment of the invention, the dielectric material comprises SiO₂Or SiN or AlON or Al₂O₃。

Another embodiment of the present invention provides a P-GaN gate enhancement HEMT device, comprising:

the substrate layer is sequentially arranged on the buffer layer, the channel layer and the barrier layer on the substrate layer;

a Mg-doped P-GaN layer on a portion of the barrier layer;

the high-resistance GaN layer is positioned in the P-GaN layer; the high-resistance GaN layer is formed by injecting hydrogen atoms into the upper half layer of the P-GaN layer, and the thickness of the high-resistance GaN layer is smaller than that of the P-GaN layer;

the TiN metal layer is positioned on the high-resistance GaN layer;

the passivation layer is positioned on the TiN metal layer and the barrier layer and on two sides of the P-GaN layer and the high-resistance GaN layer;

n ion implantation regions located at two ends of the device; wherein the implantation depth of the N ion implantation region comprises the passivation layer, the barrier layer and the channel layer;

the grid electrode penetrates through the passivation layer and is positioned on the TiN metal layer;

the drain electrode and the source electrode respectively penetrate through the passivation layer, the barrier layer and part of the channel layer adjacent to the N ion implantation area and are positioned on the channel layer;

the P-GaN gate enhanced HEMT device is prepared by the preparation method of the P-GaN gate enhanced HEMT device according to any one of claims 1-7.

In one embodiment of the invention, the thickness of the P-GaN layer is 50 nm-500 nm, and the Mg doping concentration is 10¹⁸cm^-3～10²⁰cm^-3。

In one embodiment of the present invention, the thickness of the high-resistance GaN layer formed by hydrogen atom implantation is 5nm to 100 nm; wherein, the implantation depth of hydrogen atoms is 5nm to 100nm, and the implantation concentration is 10¹⁸cm^-3～10²⁰cm^-3。

The invention has the beneficial effects that:

according to the preparation method of the P-GaN gate enhanced HEMT device, hydrogen atoms are injected into the upper half layer of the Mg-doped P-GaN layer, the hydrogen atoms and the doping element Mg form Mg-H complex, so that holes are consumed, the high-resistance GaN layer is formed in the upper half layer of the P-GaN layer, and the enhanced HEMT device with small grid leakage current, high breakdown voltage and stable threshold voltage is obtained;

in addition, the invention adopts a hydrogen atom injection mode to prepare an available MIS P-GaN gate structure, the prepared device has small damage, and the energy conversion efficiency and the reliability of the P-GaN gate enhanced HEMT device under the high-frequency and high-power working condition are improved.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a P-GaN gate enhancement type HEMT device according to an embodiment of the present invention;

fig. 2a to fig. 2h are schematic views of a manufacturing structure of a P-GaN gate enhanced HEMT device according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a P-GaN gate enhancement type HEMT device according to an embodiment of the present invention.

Description of reference numerals:

1-a substrate layer; 2-a buffer layer; 3-a channel layer; 4-barrier layer; a 5-P-GaN layer; 6-high resistance GaN layer; a 7-TiN metal layer; 8-a passivation layer; 9-a grid; 10-a source electrode; 11-drain electrode.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

In order to improve the breakdown voltage of the P-GaN gate enhanced HEMT device, an embodiment of the present invention provides a method for manufacturing the P-GaN gate enhanced HEMT device, please refer to fig. 1, where fig. 1 is a schematic flow diagram of a method for manufacturing the P-GaN gate enhanced HEMT device provided in an embodiment of the present invention, and the method includes the following steps:

step 1, growing a buffer layer 2, a channel layer 3, a barrier layer 4 and a Mg-doped P-GaN layer 5 on a substrate layer 1 in sequence.

In particular toIn other words, referring to fig. 2a, in an alternative embodiment of the present invention, a Metal-organic Chemical Vapor Deposition (MOCVD) technique is used to sequentially grow a high-resistance GaN buffer layer 2 with a thickness of 800nm to 6000nm, an undoped GaN channel layer 3 with a thickness of 50nm to 500nm, and an Al layer with a thickness of 10nm to 40nm on a substrate layer 1_xGa_1-xAn N barrier layer 4 having a thickness of 50 to 500nm and a Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3The P-GaN layer 5; wherein x is 0.1 to 0.5.

According to another alternative scheme of the embodiment of the invention, the MOCVD technology is utilized to sequentially grow the high-resistance AlGaN buffer layer 2 with the thickness of 800nm to 6000nm, the non-doped GaN channel layer 3 with the thickness of 50nm to 500nm and the Al with the thickness of 10nm to 40nm on the substrate layer 1_xGa_1-xAn N barrier layer 4 having a thickness of 50 to 500nm and a Mg doping concentration of 10¹⁸cm^-3～10²⁰cm^-3The P-GaN layer 5; wherein x is 0.1 to 0.5.

Step 2, injecting hydrogen atoms into the upper half layer of the P-GaN layer 5 to form a high-resistance GaN layer 6; wherein, the implantation depth of the hydrogen atoms is less than the thickness of the P-GaN layer 5.

Specifically, in order to increase the gate breakdown voltage, it is necessary to interpose a high-resistance insulating layer having a low defect density between the gate metal and the P-GaN layer, and generally to grow a high-resistance insulating layer between the gate metal and the P-GaN layer, such as: if SiO grows on the P-GaN layer₂As a high-resistance insulating layer, grown high-resistance insulating layer SiO₂The quality is low, so that the grid has a serious threshold voltage drift problem; if the high-resistance GaN layer is directly grown on the P-GaN layer to serve as the high-resistance insulating layer, in the process of growing the high-resistance GaN layer, because the Mg source has a memory effect and is easy to diffuse in the material, Mg remained in the furnace can be continuously doped into the high-resistance GaN layer after the Mg source is cut off, and Mg in the P-GaN layer is easy to diffuse into the high-resistance GaN layer, so that the high-quality high-resistance GaN layer cannot be grown. Therefore, this embodiment proposes to prepare the high-resistance GaN layer by implanting hydrogen atoms, which needs to be controlled to be implanted to a depth smaller than that of the P-GaN layer 5 during the implantation of hydrogen atoms, without introducing new materialThickness to obtain a high-quality high-resistance GaN layer, referring to FIG. 2b, in the embodiment of the invention, hydrogen atoms are implanted into the upper half layer of the P-GaN layer 5 by using an ion implantation process or a plasma treatment process, the implantation depth of the hydrogen atoms is 5 nm-100 nm, and the implantation concentration is 0¹⁸cm^-3～10²⁰cm^-3The high-resistance GaN layer 6 with the thickness of 5nm to 100nm is formed, namely, the high-resistance GaN layer 6 is the P-GaN layer 5 implanted with hydrogen atoms, the P-GaN layer not implanted with hydrogen atoms is the P-GaN layer 5 shown in figure 2b, and the total thickness of the P-GaN layer 5 and the high-resistance GaN layer 6 in figure 2b is the thickness of the P-GaN layer 5 not implanted with hydrogen atoms in figure 2 a.

In the embodiment of the invention, after hydrogen atoms are injected, the high-resistance GaN layer 6 is formed, the current leakage path of the grid 9 is blocked, the leakage current of the grid 9 can be greatly reduced, the high-resistance GaN layer 6 can bear a higher electric field, and the breakdown voltage of the grid 9 of the device is effectively improved while the threshold voltage drift is inhibited; in addition, the embodiment of the invention utilizes the same material to prepare the high-resistance layer, thereby reducing the stress problem among different materials and the interface defect of the heterojunction.

And 3, depositing TiN metal on the upper surface of the high-resistance GaN layer 6 to form a TiN metal layer 7.

Specifically, referring to fig. 2c, in the embodiment of the invention, TiN metal is sputter deposited on the upper surface of the high resistance GaN layer 6 by using a Physical Vapor Deposition (PVD) process to form a TiN metal layer 7 with a thickness of 5nm to 300 nm.

And 4, forming a gate 9 region on the upper surface of the TiN metal layer 7, and etching away the TiN metal layer 7, the high-resistance GaN layer 6 and the P-GaN layer 5 outside the gate 9 region until reaching the upper surface of the barrier layer 4.

Specifically, referring to fig. 2d, in the embodiment of the invention, a gate 9 region is formed on the upper surface of the TiN metal layer 7 by using a photoresist as a mask layer by using a photolithography and development technique, and the TiN metal layer 7, the high-resistance GaN layer 6 and the P-GaN layer 5 outside the gate 9 region are etched away to the upper surface of the barrier layer 4.

And 5, depositing dielectric materials on the upper surfaces of the TiN metal layer 7 and the barrier layer 4 and on the two sides of the P-GaN layer 5 and the high-resistance GaN layer 6 to form a passivation layer 8.

Specifically, referring to fig. 2e, in the embodiment of the invention, a passivation Layer 8 with a thickness of 50nm to 400nm is formed by depositing dielectric materials on the upper surfaces of the TiN metal Layer 7 and the barrier Layer 4 and on the two sides of the P-GaN Layer 5 and the high resistance GaN Layer 6 by using a Plasma Enhanced Atomic Layer Deposition (PEALD) or an Atomic Layer Deposition (ALD) or an Enhanced Chemical Vapor Deposition (ECVD) or a Low Pressure Chemical Vapor Deposition (LPCVD) process. Wherein the dielectric material comprises SiO2 or SiN or AlON or Al₂O₃But are not limited to these materials.

Step 6, respectively injecting N ions into two ends of the upper surface of the passivation layer 8 to form N ion injection regions; wherein, the implantation depth of the N ion implantation region comprises a passivation layer 8, a barrier layer 4 and a channel layer 3.

Specifically, referring to fig. 2f, in the embodiment of the present invention, N ions are respectively implanted into two ends of the upper surface of the passivation layer 8 by using a plasma implantation process to form N ion implantation regions, and the implantation depth is controlled to the channel layer 3 to implement planar device isolation.

And 7, forming a grid electrode 9 region on the upper surface of the passivation layer 8 on the high-resistance GaN layer 6, etching away the passivation layer 8 in the grid electrode 9 region until reaching the upper surface of the TiN metal layer 7, and depositing grid metal on the upper surface of the TiN metal layer 7 to form the grid electrode 9.

Specifically, referring to fig. 2g, in the embodiment of the present invention, a gate 9 region is formed on the upper surface of the passivation layer 8 on the high-resistance GaN layer 6 by using a photoresist as a mask layer through a photolithography and development technique, the passivation layer 8 in the gate 9 region is etched to reach the upper surface of the TiN metal layer 7, and a gate metal is deposited on the upper surface of the TiN metal layer 7 to form the gate 9, so as to implement ohmic contact of the gate 9.

And 8, forming a drain electrode 11 region and a source electrode 10 region on the upper surface of the passivation layer 8 adjacent to the N ion injection region respectively, etching away the passivation layer 8, the barrier layer 4 and part of the channel layer 3 in the drain electrode 11 region, depositing drain metal on the channel layer 3 to form a drain electrode 11, etching away the passivation layer 8, the barrier layer 4 and part of the channel layer 3 in the source electrode 10 region, and depositing source metal on the channel layer 3 to form a source electrode 10.

Specifically, referring to fig. 2h, in the embodiment of the present invention, a photolithographic development technique is used, a photoresist is used as a mask layer, a drain 11 region and a source 10 region are respectively formed on the upper surface of the passivation layer 8 adjacent to the N ion implantation region, the passivation layer 8, the barrier layer 4 and a portion of the channel layer 3 in the drain 11 region are etched away, a drain metal is deposited on the channel layer 3 to form the drain 11, so as to implement ohmic contact of the drain 11, and at the same time, the passivation layer 8, the barrier layer 4 and a portion of the channel layer 3 in the source 10 region are etched away, and a source metal is deposited on the channel layer 3 to form the source 10, so as to implement ohmic contact of the source 10. And finally, annealing the whole device.

It should be noted that, in the embodiments of the present invention, specific description of process parameters is not performed, each process adopted in the preparation process is the prior art, and the specific process parameters are designed according to actual situations, and are not limited to be described here.

In summary, in the method for manufacturing the P-GaN gate enhancement type HEMT device provided in the embodiment of the present invention, hydrogen atoms are injected into the upper half layer of the Mg-doped P-GaN layer 5, and the hydrogen atoms and the doping element Mg form a Mg-H complex, so that holes are consumed, and the high resistance GaN layer 6 is formed in the upper half layer of the P-GaN layer 5, so as to obtain the enhancement type HEMT device with a small gate 9 leakage current, a high breakdown voltage, and a stable threshold voltage;

in addition, the embodiment of the invention adopts a hydrogen atom injection mode to prepare an available MIS P-GaN gate structure, the prepared device has small damage, and the energy conversion efficiency and the reliability of the P-GaN gate enhanced HEMT device under the high-frequency and high-power working condition are improved.

Based on the same inventive concept, referring to fig. 3 again, an embodiment of the present invention further provides a P-GaN gate enhanced HEMT device, including:

the device comprises a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4 which are sequentially arranged on the substrate layer 1;

a Mg-doped P-GaN layer 5 on a portion of the barrier layer 4; preferably, the thickness of the P-GaN layer 5 is 50nm to 500nm, and the Mg doping concentration is 10¹⁸cm^-3～10²⁰cm^-3。

The high-resistance GaN layer 6 is positioned in the P-GaN layer 5; the high-resistance GaN layer 6 is formed by injecting hydrogen atoms into the upper half layer of the P-GaN layer 5, and the thickness of the high-resistance GaN layer 6 is smaller than that of the P-GaN layer 5; preferably, the thickness of the high-resistance GaN layer 6 formed by hydrogen atom implantation is 5nm to 100 nm; wherein, the implantation depth of hydrogen atoms is 5nm to 100nm, and the implantation concentration is 10¹⁸cm^-3～10²⁰cm^-3。

A TiN metal layer 7 on the high-resistance GaN layer 6;

the passivation layer 8 is positioned on the TiN metal layer 7 and the barrier layer 4 and on two sides of the P-GaN layer 5 and the high-resistance GaN layer 6;

n ion implantation regions located at two ends of the device; the implantation depth of the N ion implantation region comprises a passivation layer 8, a barrier layer 4 and a channel layer 3;

the grid 9 penetrates through the passivation layer 8 and is positioned on the TiN metal layer 7;

a drain electrode 11 and a source electrode 10 respectively penetrating through the passivation layer 8 adjacent to the N ion implantation region, the barrier layer 4 and a part of the channel layer 3 and located on the channel layer 3;

the P-GaN gate enhanced HEMT device is prepared according to the preparation method of the P-GaN gate enhanced HEMT device.

For the device embodiment, since it is basically similar to the preparation method embodiment, the description is simple, and the relevant points can be referred to the partial description of the preparation method embodiment.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.