阅读说明：本技术 一种电浮硅无畸变异质dehfet器件及其制备方法 (Electro-floating silicon distortionless heterogeneous DEHFET device and preparation method thereof ) 是由 廖晨光 雷晓艺 戴扬 张云尧 张涵 马晓龙 赵武 于 2021-08-11 设计创作，主要内容包括：本发明公开了一种电浮硅无畸变异质DEHFET器件及其制备方法,所述方法包括：制备离子注入后的P型衬底；在离子注入后的P型衬底上形成碳掺杂缓冲区；在碳掺杂缓冲区上形成碳掺杂电浮动区；在碳掺杂电浮动区上形成屏蔽区；在屏蔽区上表面中部形成介电区,使得屏蔽区的两端上表面未被介电区覆盖；在介电区上形成栅电极；通过离子注入在碳掺杂电浮动区和屏蔽区的两端制作源电极和漏电极；在栅电极上表面以及介电区和栅电极的侧面制作氮化硅膜区；在P型衬底底部开设阱槽并在阱槽中制备阱槽石墨烯。利用本发明方法制备的电浮硅无畸变异质DEHFET器件,能够减少漏电极热电荷,有效抑制漏电极暂态电流,从而使得引发器件逻辑错误的几率减小。(The invention discloses an electrically floating silicon distortionless heterogeneous DEHFET device and a preparation method thereof, wherein the method comprises the following steps: preparing a P-type substrate after ion implantation; forming a carbon doped buffer region on the P-type substrate after the ion implantation; forming a carbon-doped electrically floating region on the carbon-doped buffer region; forming a shielding region on the carbon-doped electrically floating region; forming a dielectric region in the middle of the upper surface of the shielding region so that the upper surfaces of both ends of the shielding region are not covered by the dielectric region; forming a gate electrode on the dielectric region; manufacturing a source electrode and a drain electrode at two ends of the carbon-doped electric floating region and the shielding region by ion implantation; manufacturing a silicon nitride film region on the upper surface of the gate electrode and the side surfaces of the dielectric region and the gate electrode; and (3) forming a well groove at the bottom of the P-type substrate and preparing well groove graphene in the well groove. The electric floating silicon distortionless heterogeneous DEHFET device prepared by the method can reduce the electric leakage electrode thermal charge and effectively inhibit the drain electrode transient current, thereby reducing the probability of causing device logic error.)

1. A preparation method of an electrically floating silicon distortionless heterogeneous DEHFET device is characterized by comprising the following steps:

preparing a P-type substrate (1) after ion implantation;

forming a carbon-doped buffer region (2) on the P-type substrate (1) after the ion implantation;

forming a carbon-doped electrically floating region (3) on the carbon-doped buffer region (2);

forming a screening region (4) on the carbon-doped electrically floating region (3);

forming a dielectric region (5) in the middle of the upper surface of the shielding region (4) so that the upper surfaces of both ends of the shielding region (4) are not covered by the dielectric region (5);

-forming a gate electrode (6) on said dielectric region (5);

manufacturing a source electrode (7) and a drain electrode (8) at two ends of the carbon-doped electric floating region (3) and the shielding region (4) through ion implantation;

manufacturing a silicon nitride film region (9) on the upper surface of the gate electrode (6) and the side surfaces of the dielectric region (5) and the gate electrode (6);

and (2) forming a well groove at the bottom of the P-type substrate (1) and preparing well groove graphene (10) in the well groove.

2. The process of the electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein the preparation of the ion implanted P-type substrate (1) comprises:

selecting a P-type doped silicon substrate (1);

injecting boron ions into the P-type doped silicon substrate (1) and annealing to obtain the P-type substrate (1) injected with the boron ions;

and implanting argon ions into the P-type substrate (1) implanted with the boron ions and annealing to obtain the P-type substrate (1) after ion implantation.

3. The process of forming an electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein forming a carbon doped buffer region (2) on the ion implanted P-type substrate (1) comprises:

with SiHCL₂As a gas source of silicon, with CH₄And as a carbon gas source, preparing a carbon doping buffer area (2) on the P-type substrate (1) after ion implantation, wherein the carbon doping concentration in the carbon doping buffer area (2) is gradually increased from bottom to top according to the proportion of 0%, 15%, 25% to 35%.

4. The process for manufacturing an electrically floating silicon distortionless hetero DEHFET device according to claim 3, wherein the material of the carbon doped electrically floating region (3) is SiC with a carbon doping concentration of 35%.

5. The process of forming an electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein forming a dielectric region (5) in a middle portion of an upper surface of the shielding region (4) comprises:

growing a graphite oxide layer on the shielding region (4) by using a chemical vapor deposition method;

growing a layer of HfO2 on the graphite oxide layer using atomic layer deposition to form a dielectric region (5) consisting of the graphite oxide layer and the HfO2 layer.

6. Process for the production of an electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein forming a gate electrode (6) on the dielectric region (5) comprises:

and depositing graphene on the dielectric region (5) at the temperature of 505-705 ℃ to prepare a gate electrode (6).

7. A process of fabricating an electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein fabricating a source electrode (7) and a drain electrode (8) at both ends of the carbon doped electrically floating region (3) and the shielding region (4) by ion implantation comprises:

and coating photoresist on the gate electrode (6), forming a photoresist pattern after exposure and development, and performing ion implantation on the region where the source electrode (7) and the drain electrode (8) are located after mask lithography to manufacture the source electrode (7) and the drain electrode (8) at two ends of the carbon-doped electric floating region (3) and the shielding region (4), wherein part of the source electrode (7) and part of the drain electrode (8) are both positioned below the dielectric region (5).

8. A process for fabricating an electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein forming a silicon nitride film (9) on the upper surface of the gate electrode (6) and on the sides of the dielectric region (5) and the gate electrode (6) comprises:

NH at 705-905 deg.C₃As a nitrogen source, with SiH₄For silicon source, a plasma enhanced chemical vapor process is used to deposit silicon nitride on the upper surface of the gate electrode (6) and on the dielectric region (5) and the side surfaces of the gate electrode (6) to prepare a silicon nitride film region (9) covering the dielectric region (5) and the gate electrode (6).

9. The process method for manufacturing the electrically floating silicon distortionless hetero DEHFET device according to claim 1, wherein the step of forming a well trench in the bottom of the P-type substrate (1) and preparing well trench graphene (10) in the well trench comprises:

coating photoresist on the bottom of the P-type substrate (1), forming a photoresist pattern after exposure and development, and etching the P-type substrate (1) to form a well groove;

and growing graphene in the trap groove at the temperature of 505-705 ℃ to prepare trap groove graphene (10).

10. An electrically floating silicon distortionless hetero DEHFET device prepared by the method of any of claims 1 to 9, comprising a P-type substrate (1), a carbon doped buffer region (2), a carbon doped electrically floating region (3), a shielding region (4), a dielectric region (5), a gate electrode (6), a source electrode (7), a drain electrode (8), a silicon nitride film region (9) and well-trench graphene (10), wherein,

the P-type substrate (1), the carbon-doped buffer region (2), the carbon-doped electric floating region (3), the shielding region (4), the dielectric region (5) and the gate electrode (6) are sequentially arranged from bottom to top, and two sides of the shielding region (4) are not covered by the dielectric region (5);

the source electrode (7) and the drain electrode (8) are respectively positioned at two ends of the shielding region (4), the lower ends of the source electrode and the drain electrode extend into the carbon-doped electric floating region (3), and a part of the upper surface of the source electrode and a part of the lower surface of the drain electrode are both positioned below the dielectric region (5);

the silicon nitride film region (9) covers the upper surface of the gate electrode (6) and the side surfaces of the dielectric region (5) and the gate electrode (6);

the trap groove graphene (10) is arranged in a trap groove formed in the center of the bottom of the P-type substrate (1).

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to an electrically floating silicon distortionless heterogeneous DEHFET device and a preparation method thereof.

Background

Space satellites, spacecraft, and electronic systems operating in an electromagnetically damaged environment are subject to damage from charged particles, cosmic rays, and nuclear electromagnetic damage. As a novel device in an electronic system, DEHFET (defectionless Electric Clamping of Van der Waals Heterojunction Field Effect Transistor) has the advantages of high performance, high reliability, simple process, compatibility with the traditional silicon process and the like, is expected to be applied to a future high-performance three-dimensional integrated system, and opens up a new technical path for further improving the performance of an integrated circuit.

With the rapid development of space technology, the subsequent reliability of electronic systems is particularly important. The space electromagnetic damage and the nuclear electromagnetic damage influence the electromagnetic damage resistance of the nanometer electrically floating silicon distortionless DEHFET device and the integrated circuit thereof. The single-particle electromagnetic damage effect has a different damage mechanism to DEHFET devices than total dose electromagnetic damage. The high-energy single particle bombardment of the DEHFET device generates a large number of electron-hole pairs at the depletion end close to the drain electrode, so that the device is invalid and cannot work normally. Therefore, the technical requirement for strengthening the DEHFET device against the single event transient effect is very urgent.

Therefore, how to solve the problem of DEHFET device failure becomes an urgent problem to be solved.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an electrically floating silicon distortionless heterogeneous DEHFET device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

the invention provides a preparation method of an electrically floating silicon distortionless heterogeneous DEHFET device, which comprises the following steps:

preparing a P-type substrate after ion implantation;

forming a carbon doped buffer region on the P-type substrate after the ion implantation;

forming a carbon-doped electrically floating region on the carbon-doped buffer region;

forming a shielding region on the carbon-doped electrically floating region;

forming a dielectric region in the middle of the upper surface of the shielding region such that the upper surfaces of both ends of the shielding region are not covered by the dielectric region;

forming a gate electrode on the dielectric region;

manufacturing a source electrode and a drain electrode at two ends of the carbon-doped electric floating region and the shielding region by ion implantation;

manufacturing a silicon nitride film region on the upper surface of the gate electrode and the side surfaces of the dielectric region and the gate electrode;

and forming a well groove at the bottom of the P-type substrate and preparing well groove graphene in the well groove.

In one embodiment of the present invention, preparing an ion implanted P-type substrate includes:

selecting a P-type doped silicon substrate;

injecting boron ions into the P-type doped silicon substrate and annealing to obtain the P-type substrate injected with the boron ions;

and injecting argon ions into the P-type substrate injected with the boron ions and annealing to obtain the P-type substrate after ion injection.

In one embodiment of the present invention, forming a carbon doped buffer region on the ion implanted P-type substrate includes:

with SiHCL₂As a gas source of silicon, with CH₄And as a carbon gas source, preparing a carbon doping buffer area on the P-type substrate after ion implantation, wherein the carbon doping concentration in the carbon doping buffer area is gradually increased from bottom to top according to the proportion of 0%, 15%, 25% to 35%.

In one embodiment of the present invention, the material of the carbon-doped electrical floating region is SiC, and the carbon doping concentration is 35%.

In one embodiment of the present invention, forming a dielectric region in a middle portion of an upper surface of the shielding region includes:

growing a graphite oxide layer on the shielding region by using a chemical vapor deposition method;

growing a layer of HfO2 on the graphite oxide layer using atomic layer deposition to form a dielectric region comprised of the graphite oxide layer and the HfO2 layer.

In one embodiment of the present invention, forming a gate electrode on the dielectric region includes:

and depositing graphene on the dielectric region at the temperature of 505-705 ℃ to prepare a gate electrode.

In one embodiment of the present invention, fabricating a source electrode and a drain electrode at both ends of the carbon-doped electrically floating region and the shielding region by ion implantation includes:

and coating photoresist on the gate electrode, forming a photoresist pattern after exposure and development, and performing ion implantation on the region where the source electrode and the drain electrode are located after mask lithography to manufacture the source electrode and the drain electrode at two ends of the carbon-doped electric floating region and the shielding region, wherein part of the source electrode and part of the drain electrode are both positioned below the dielectric region.

In one embodiment of the present invention, forming a silicon nitride film on the upper surface of the gate electrode and the side surfaces of the dielectric region and the gate electrode includes:

NH at 705-905 deg.C₃As a nitrogen source, with SiH₄And depositing silicon nitride on the upper surface of the gate electrode and the side surfaces of the dielectric region and the gate electrode by adopting a plasma enhanced chemical vapor process to prepare a silicon nitride film region covering the dielectric region and the gate electrode.

In an embodiment of the present invention, opening a well trench at the bottom of a P-type substrate and preparing well trench graphene in the well trench includes:

coating photoresist on the bottom of the P-type substrate, forming a photoresist pattern after exposure and development, and etching the P-type substrate to form a well groove;

and growing graphene in the trap tank at the temperature of 505-705 ℃ to prepare the trap tank graphene.

Another aspect of the present invention provides an electrically floating silicon distortionless hetero-DEHFET device fabricated by the method of any of the above embodiments, the electrically floating silicon distortionless hetero-DEHFET device comprising a P-type substrate, a carbon-doped buffer region, a carbon-doped electrically floating region, a shielding region, a dielectric region, a gate electrode, a source electrode, a drain electrode, a silicon nitride film region, and well trench graphene, wherein,

the P-type substrate, the carbon-doped buffer region, the carbon-doped electrically floating region, the shielding region, the dielectric region and the gate electrode are arranged from bottom to top in sequence, and two sides of the shielding region are not covered by the dielectric region;

the source electrode and the drain electrode are respectively positioned at two ends of the shielding region, the lower ends of the source electrode and the drain electrode extend into the carbon-doped electric floating region, and part of the upper surface of the source electrode and part of the lower surface of the drain electrode are both positioned below the dielectric region;

the silicon nitride film region covers the upper surface of the gate electrode and the side surfaces of the dielectric region and the gate electrode;

the trap groove graphene is arranged in a trap groove formed in the center of the bottom of the P-type substrate.

Compared with the prior art, the invention has the beneficial effects that:

1. when a single particle bombards the device, the chemical bond between silicon and nitrogen in the silicon nitride film is relatively stable, and the electrically floating silicon distortionless heterogeneous DEHFET device prepared by the method has certain blocking capability on heavy ions. When the energy of heavy ions enters the drain electrode in the device, the generated electron-hole pairs are reduced, and a small amount of electrons are absorbed by the trap groove graphene in the substrate area, so that the thermal charge of the drain electrode is reduced, the transient current of the drain electrode is reduced, and the probability of logic errors of the device is low.

2. According to the electric floating silicon distortionless heterogeneous DEHFET device prepared by the method, the graphene in the trap groove has conductivity, and generated electrons are collected, so that the electron collection of a drain electrode is reduced, and the transient current of the drain electrode is reduced.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic flow chart of a process method of an electrically floating silicon distortionless hetero-DEHFET device according to an embodiment of the present invention;

fig. 2a to fig. 2j are schematic process diagrams of a process of an electrically floating silicon distortionless hetero-DEHFET device according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an electrically floating silicon distortionless hetero-DEHFET device according to an embodiment of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description is provided with reference to the accompanying drawings and the detailed description of the present invention for an electrically floating silicon distortionless hetero DEHFET device and the manufacturing method thereof.

The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be further and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.

Example one

Referring to fig. 1, please refer to fig. 1 and fig. 2a to fig. 2i, fig. 1 is a flow chart of a method for manufacturing an electrically floating silicon distortionless hetero-DEHFET device according to an embodiment of the present invention; fig. 2a to fig. 2i are schematic views illustrating a process for manufacturing an electrically floating silicon distortionless hetero DEHFET device according to an embodiment of the present invention. The preparation method of the DEHFET device comprises the following steps:

step 1, please refer to fig. 2a, preparing an ion implanted P-type substrate 1.

Step 1.1, selecting a P-type lightly doped silicon substrate 1.

Wherein, the thickness range of the P-type lightly doped silicon substrate 1 is 305-405 um.

And step 1.2, implanting boron ions into the P-type lightly doped silicon substrate 1, and annealing after the implantation of the boron ions is finished to obtain the P-type substrate 1 implanted with the boron ions.

And 1.3, implanting argon ions into the boron ion implanted P-type substrate 1, and annealing after the argon ion implantation is finished to obtain the ion implanted P-type substrate 1.

Specifically, firstly, implanting boron ions into the selected P-type doped silicon substrate, wherein the implantation energy is 905Kev, and the implantation concentration is 6 × 10¹²cm^-3-8×10¹²cm^-3After the injection is finished, annealing for 30 minutes under the conditions of nitrogen environment and 905 ℃ to form light doping; then, the boron ion implanted P-type substrate 1 was subjected to argon ion implantation at an implantation energy of 45Kev and an implantation concentration of 2X 10¹²cm^-3And after the injection is finished, annealing is carried out for 2 hours under the conditions of nitrogen environment and 905 ℃ temperature, so that the defects of the carbon-doped buffer region 2 to be grown later are reduced.

Step 2, referring to fig. 2b, a carbon doped buffer region 2 is formed on the ion implanted P-type substrate 1.

Specifically, a reduced pressure epitaxial growth process is adopted to prepare a carbon-doped buffer region 2 on the P-type substrate 1 after ion implantation, wherein the material of the carbon-doped buffer region 2 is SiC, and the carbon doping concentration is gradually increased from bottom to top according to the proportion of 0%, 15%, 25% to 35%. The reduced pressure epitaxial growth referred to herein means that chemical vapor phase epitaxial growth is performed at a pressure of less than one atmosphere.

In one embodiment, a reduced pressure epitaxial growth process is used with SiHCL₂As a gas source of silicon, with CH₄The carbon-doped buffer region 2 is prepared as a source gas of carbon. In order to reduce dislocation density and surface roughness, the conditions of 605 ℃ in a low-temperature environment, 105 Torr of pressure and 105nm/min of growth rate are adopted, and the carbon doped buffer region 2 with carbon doping sequentially increased from bottom to top is prepared on the P-type substrate 1 after ion implantation, and the growth mode ensures that crystal defects are not easy to diffuse to the surface, and the high-quality carbon doped buffer region 2 can be obtained. In the embodiment, the carbon doping concentration is set to be gradually increased within the ranges of 0%, 15%, 25% and 35%, so that the gradual carbon doping concentration can effectively reduce the crystal misfit dislocation density, and the tensile stress degree generated by the shielding region is better.

Preferably, the thickness of the carbon-doped buffer region 2 is in the range of 2 to 3 μm.

Step 3, please refer to fig. 2c, a carbon-doped floating region 3 is formed on the carbon-doped buffer region 2.

Specifically, a carbon-doped electric floating region 3 with constant carbon doping is grown on the carbon-doped buffer region 2 prepared in the step 2 by using a Low Energy Plasma Enhanced Chemical Vapor Deposition (LEPECVD) and solid-state source molecular beam epitaxy (SSE) technology method, and the material of the carbon-doped electric floating region 3 is SiC. The growth environment of the carbon doped electrically floating region 3 is at a low temperature of 605 degrees celsius and a pressure of 105 torr.

In the present embodiment, the carbon doping concentration of the carbon-doped electrical floating region 3 is 35%. When the C component of the carbon-doped electrically floating region 3 is 35%, the relaxation degree of the carbon-doped buffer region 2 is good and the dislocation density is low.

Preferably, the thickness of the carbon-doped electrical floating region 3 is in the range of 505 to 605 nm.

Step 4, referring to fig. 2d, a shielding region 4 is formed on the carbon-doped electrically floating region 3.

Specifically, the shielding region 4 is epitaxially grown on the carbon-doped electrically floating region 3 prepared in step 3 by an epitaxial deposition method at a temperature and for a time of 605 ℃ for 1 hour. The material of the shielding region 4 in this embodiment is multi-walled carbon nanotubes. Due to the different lattice constants of the carbon doped electrically floating region 3 and the silicon, epitaxially grown multiwall carbon nanotubes will grow along the lattice of the carbon doped electrically floating region 3, and the multiwall carbon nanotube layer spacing and lattice will be stretched, thereby forming a biaxial tensile strain region in the shield region 4. Under the action of tensile stress, the reduction of the effective mass of the electric conduction and the reduction of the inter-valley scattering improve the mobility of electrons, thereby improving the driving capability of the device.

Preferably, the thickness of the shielding region 4 is in the range of 10 to 25 nm.

Step 5, please refer to fig. 2e, forming a dielectric region 5 in the middle of the upper surface of the shielding region 4, so that the upper surfaces of the two ends of the shielding region 4 are not covered by the dielectric region 5, and the dielectric region 5 of this embodiment includes a graphite oxide layer and an HfO2 layer.

Specifically, step 5 comprises:

and 5.1, growing a graphite oxide layer on the shielding region 4 by using a chemical vapor deposition method.

And 5.2, growing an HfO2 layer on the graphite oxide layer by utilizing an atomic layer deposition method to obtain the dielectric region 5 consisting of the graphite oxide layer and the HfO2 layer.

In this embodiment, a graphite oxide layer is first grown on a part of the surface of the shielding region 4 by using a chemical vapor deposition method to expose the upper surface parts of the two ends of the shielding region 4, wherein the growth temperature of the graphite oxide layer is 605-805 ℃, and the thickness of the graphite oxide layer is 6-14 nm. And then, growing an HfO2 layer on the graphite oxide layer by adopting an atomic layer deposition method to prepare a dielectric region 5 consisting of the graphite oxide layer and an HfO2 layer, wherein the growth temperature of the HfO2 layer is 605-805 ℃, and the thickness of the HfO2 layer is 4-6 nm. As the dielectric constant of HfO2 is larger, the thickness of the dielectric region composed of graphite oxide and HfO2 is reduced, and the principle of scaling down of small-size devices can be met.

Preferably, the thickness of the dielectric region 5 is in the range of 10 to 25 nm.

Step 6, referring to fig. 2f, a gate electrode 6 is formed on the dielectric region 5.

Specifically, graphene is grown on the dielectric region 5 prepared in the step 5 by using a traditional deposition process to prepare the gate electrode 6, and the growth temperature of the gate electrode 6 is 505-705 ℃.

Preferably, the thickness of the gate electrode 6 is in the range of 30 to 55 nm.

Step 7, referring to fig. 2g, a source electrode 7 and a drain electrode 8 are formed at both ends of the carbon-doped electrically floating region 3 and the shielding region 4 by ion implantation.

Specifically, photoresist is coated on the gate electrode 6, a photoresist pattern is formed after exposure and development, and ion implantation is performed on the region where the source electrode 7 and the drain electrode 8 are located after mask lithography, so that a source electrode region and a drain electrode region are formed at two ends of the middle region between the carbon-doped electric floating region 3 and the shielding region 4;

then, phosphorus ions are implanted into the source electrode region and the drain electrode region at the same time, and the doping concentration is 5 × 10¹⁹cm^-3～5×10²⁰cm^-3And carrying out N-type heavy doping on the source electrode 7 and the drain electrode 8 with the energy of 150-205 Kev. The source electrode 7 and the drain electrode 8 of the present embodiment are respectively located at both ends of the shielding region 4, and the lower ends thereof extend into the carbon-doped electrically floating region 3, and a portion of each of the source electrode 7 and the drain electrode 8 is located below the dielectric region 5, i.e., each is covered by the dielectric region 5.

Preferably, the thickness of the source electrode 7 and the drain electrode 8 ranges from 50 to 65 nm.

In step 8, referring to fig. 2h, a silicon nitride film region 9 is formed on the upper surface of the gate electrode 6 and the side surfaces of the dielectric region 5 and the gate electrode 6 to cover the dielectric region 5 and the gate electrode 6.

Specifically, under the temperature condition of 705-905 ℃, silicon nitride is deposited on the upper surface of the gate electrode 6 and the side surfaces of the dielectric region 5 and the gate electrode 6 by adopting a plasma enhanced chemical vapor process to prepare a silicon nitride film region 9 covering the dielectric region 5 and the gate electrode 6, wherein the nitrogen source is NH₃Flow rate of 5cm³Min, SiH as silicon source₄Flow rate of 120cm³The growth rate is 105 nm/min. Silicon nitride grown in the ambientThe film has high hardness and the chemical bond between nitrogen and silicon is more stable. When external high-energy single particles bombard the device, the silicon nitride region of the outermost region has a protective effect on the internal structure of the van der waals device, and the radiation resistance of the device is enhanced. With the increase of the thickness of the silicon nitride film area, the ionization energy loss and the incidence depth of heavy ions after the heavy ions are incident to the device are reduced, and the transient current of the drain electrode of the device is reduced.

Preferably, the thickness of the silicon nitride film region 9 is in the range of 105 to 205 nm.

Step 9, please refer to fig. 2i, preparing well trench graphene 10 at the bottom of the P-type substrate 1.

In this embodiment, step 9 specifically includes:

and 9.1, coating photoresist on the bottom of the P-type substrate 1, forming a photoresist pattern after exposure and development, and etching the middle of the bottom of the P-type substrate 1 to form a well groove.

And 9.2, growing graphene in the trap tank at the temperature of 505-705 ℃ to prepare trap tank graphene 10.

In the present embodiment, the reason why the graphene is filled in the well trench is as follows: firstly, graphene has the characteristics of semimetal and semiconductor and can be used as a good conductor; and secondly, the metal work function of the graphene can be changed by modulating the carbon doping concentration in the graphene, and the critical voltage of the interface of the graphene and the P-type substrate is regulated and controlled. Based on the structure, when heavy ions bombard the device, a part of heavy ion energy is lost due to the silicon nitride film area on the surface of the device, the residual energy forms a plasma column with electrons and holes at the sensitive end, namely the drain electrode consumption end, and the electrons and the holes are absorbed by the P-type substrate and collected by the drain electrode. At this time, the graphene in the well groove has conductivity, and generated electrons are collected, so that the collection of the drain electrode is reduced, and the transient current of the drain electrode is reduced.

Preferably, the thickness of the well trench graphene 10 ranges from 120 nm to 185 nm.

In this embodiment, after step 9, the method further includes:

and 10, referring to fig. 2j, etching the source electrode 7, the drain electrode 8, the gate electrode 6 and the P-type substrate 1 to form a hole 11, then depositing metal Ni on the hole 11, then depositing a borophosphosilicate glass passivation region on the surface of the wafer to be fixed of the device, and then etching an interconnection line at the position where the metal Ni is deposited.

When the electrically floating silicon distortionless heterogeneous DEHFET device prepared by the embodiment is used, when a single particle bombards the device, the chemical bond between silicon and nitrogen in the silicon nitride film is relatively stable, and the electrically floating silicon distortionless heterogeneous DEHFET device has certain blocking capability on heavy ions. When the energy of heavy ions enters the sensitive end region of the drain electrode in the device, the generated electron-hole pairs are reduced, and a small amount of electrons are absorbed by the trap groove graphene in the substrate region, so that the thermal charge of the drain electrode is reduced, the transient current of the drain electrode is reduced, and the probability of logic generation of the device is low. In addition, the graphene in the trap groove has conductivity, and generated electrons are collected, so that the electron collection of the drain electrode is reduced, and the transient current of the drain electrode is reduced.

Example two

The present embodiment provides an electrically floating silicon distortionless hetero-DEHFET device on the basis of the above embodiments. Referring to fig. 3, fig. 3 is a schematic structural diagram of an electrically floating silicon distortionless hetero DEHFET device according to an embodiment of the present invention. The electric floating silicon distortionless heterogeneous DEHFET device comprises a P-type substrate 1, a carbon-doped buffer region 2, a carbon-doped electric floating region 3, a shielding region 4, a dielectric region 5, a gate electrode 6, a source electrode 7, a drain electrode 8, a silicon nitride film region 9 and trap groove graphene 10.

The P-type substrate 1, the carbon-doped buffer region 2, the carbon-doped electric floating region 3, the shielding region 4, the dielectric region 5 and the gate electrode 6 are sequentially arranged from bottom to top, and the dielectric region 5 covers the middle part of the shielding region 4, so that part of the surfaces of two ends of the shielding region 4 are not covered. The source electrode 7 and the drain electrode 8 of this embodiment are located at both ends of the shielding region 4, respectively, and the lower ends thereof extend into the carbon-doped electrically floating region 3, and a part of the upper surface thereof is covered with the dielectric region 5. A silicon nitride film region 9 covers the upper surface of the gate electrode 6 and the side surfaces of the dielectric region 5 and the gate electrode 6. The well groove graphene 10 is arranged in a well groove formed in the center of the bottom of the P-type substrate 1.

The material of the carbon-doped buffer region 2 is SiC, wherein the carbon doping concentration is gradually increased from bottom to top according to the proportion of 0%, 15%, 25% to 35%. The carbon-doped electrically floating region 3 has a constant carbon doping concentration of 35%. The dielectric region 5 of the present embodiment comprises a graphite oxide layer and a HfO2 layer.

Preferably, the thickness range of the P-type lightly doped silicon substrate 1 is 305-405 um, the thickness range of the carbon doped buffer region 2 is 2-3 μm, the thickness range of the carbon doped electric floating region 3 is 505-605 nm, the thickness range of the shielding region 4 is 10-25 nm, the thickness range of the dielectric region 5 is 10-25 nm, the thickness range of the gate electrode 6 is 30-55 nm, the thickness ranges of the source electrode 7 and the drain electrode 8 are 50-65 nm, the thickness range of the silicon nitride film region 9 is 105-205 nm, and the thickness range of the well groove graphene 10 is 120-185 nm.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.