Method for manufacturing semiconductor element
阅读说明：本技术 制造半导体元件的方法 (Method for manufacturing semiconductor element ) 是由 林俊亨 金亨俊 金莹俊 朴柱相 禹皇帝 于 2021-04-29 设计创作，主要内容包括：实施例涉及一种制造半导体元件的方法,所述方法包括下述步骤：准备基底；在所述基底上形成半导体层,其中,所述半导体层包括结晶的二维层；在所述半导体层上形成源极电极和漏极电极；通过使用次氯酸钠湿蚀刻所述半导体层,形成半导体构件,其中,所述湿蚀刻导致残留物；以及使用纯净水和惰性气体去除所述残留物。(An embodiment relates to a method of manufacturing a semiconductor component, the method comprising the steps of: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a crystalline two-dimensional layer; forming a source electrode and a drain electrode on the semiconductor layer; forming a semiconductor member by wet etching the semiconductor layer using sodium hypochlorite, wherein the wet etching results in a residue; and removing the residue using purified water and an inert gas.)
1. A method of manufacturing a semiconductor element, wherein the method comprises:
preparing a substrate;
forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a crystalline two-dimensional layer;
forming a source electrode and a drain electrode on the semiconductor layer;
forming a semiconductor member by wet etching the semiconductor layer using sodium hypochlorite, wherein the wet etching results in a residue; and
the residue is removed using purified water and inert gas.
2. The method of claim 1, wherein the semiconductor layer comprises at least one of molybdenum disulfide, molybdenum diselenide, and molybdenum ditelluride.
3. The method of claim 2, wherein the molybdenum disulfide is produced by synthesis from molybdenum chloride and hydrogen sulfide at a temperature in the range of 650 degrees celsius to 750 degrees celsius for a length of time in the range of 13 minutes to 17 minutes.
4. The method of claim 2, wherein the molybdenum disulfide is produced by synthesis from molybdenum chloride and hydrogen sulfide at 700 degrees celsius for 15 minutes.
5. The method of claim 1, wherein the semiconductor layer comprises at least one of tungsten disulfide, tungsten diselenide, and tungsten ditelluride.
6. The method of claim 1, wherein the semiconductor layer comprises at least one of zirconium disulfide and zirconium diselenide.
7. The method of claim 1, wherein the semiconductor layer comprises at least one of hafnium disulfide and hafnium diselenide.
8. The method of claim 1, wherein the semiconductor layer comprises at least one of platinum disulfide and platinum diselenide.
9. The method of claim 1, wherein the semiconductor layer comprises at least one of rhenium disulfide and rhenium diselenide.
10. The method of claim 1, wherein the source electrode and the drain electrode are formed by a lithographic process.
Technical Field
The technical field relates to a method for manufacturing a semiconductor element.
Background
The display device may display an image according to an input signal. Modern display devices include liquid crystal display devices and organic light emitting display devices.
The display device may include a display element and a transistor for controlling the display element. The transistor may include an active component. In order to form the active member, the active layer needs to be etched. If the active layer is etched by a dry etching process, a large set of equipment is generally required. In general, the dry etching process requires a long time.
Disclosure of Invention
Embodiments may relate to a method of manufacturing a display device including a semiconductor element. An object of an embodiment may be to provide an etching process that takes time and does not require a large apparatus used in dry etching.
The method of manufacturing a semiconductor element according to the embodiment may include the steps of: preparing a substrate; forming an active layer on the substrate, the active layer having a crystalline two-dimensional layered structure and including a first region, a second region spaced apart from the first region, and a third region between the first region and the second region; forming a source electrode on the first region and a drain electrode on the second region; wet etching the active layer by applying sodium hypochlorite (NaOCl) to the active layer, forming an active pattern; and removing a residue generated by the wet etching using purified water and an inert gas.
According to an embodiment, the active layer may include at least one of molybdenum compounds including molybdenum disulfide (MoS)2) Molybdenum diselenide (MoSe)2) And molybdenum ditelluride (MoTe)2)。
According to embodiments, the material may be prepared by reacting molybdenum chloride (MoCl)5) And hydrogen sulfide (H)2S) synthetic production of the molybdenum disulfide (MoS)2). The synthesis may be performed at 650 degrees celsius to 750 degrees celsius for 13 minutes to 17 minutes.
According to embodiments, the material may be prepared by reacting molybdenum chloride (MoCl)5) And hydrogen sulfide (H)2S) synthetic production of the molybdenum disulfide (MoS)2). The synthesis may be performed at 700 degrees celsius for 15 minutes.
According to an embodiment, the active layer may include at least one of tungsten compounds including tungsten disulfide (WS)2) Tungsten diselenide (WSe)2) And tungsten ditelluride (WTE)2)。
According to an embodiment, the active layer may comprise at least one of zirconium compounds comprising zirconium disulfide (ZrS)2) And zirconium diselenide (ZrSe)2)。
According to an embodiment, the active layer may include at least one of a hafnium compound including hafnium disulfide (HfS)2) And hafnium diselenide (HfSe)2)。
According to an embodiment, the active layer may include at least one of platinum compounds including platinum disulfide (PtS)2) And platinum diselenide (PtSe)2)。
According to an embodiment, the active layer may comprise at least one of a rhenium compound comprising rhenium disulfide (ReS)2) And rhenium diselenide (ReSe)2)。
According to an embodiment, the source electrode and the drain electrode may be formed by a lithography process.
According to an embodiment, the source electrode and the drain electrode may include one or more of titanium (Ti) and silver (Ag).
According to an embodiment, the method may further comprise: forming a gate insulating layer on the active pattern; forming a gate electrode on the gate insulating layer; and forming an interlayer insulating layer on the gate electrode.
According to an embodiment, the method may further comprise: forming a first contact hole exposing the source electrode in the interlayer insulating layer and the gate insulating layer; and forming a source pattern filling the first contact hole on the interlayer insulating layer.
According to an embodiment, the method may further comprise: forming a second contact hole exposing the drain electrode in the interlayer insulating layer and the gate insulating layer; and forming a drain pattern filling the second contact hole on the interlayer insulating layer.
According to an embodiment, the inert gas may include nitrogen (N)2)。
According to an embodiment, the inert gas may include argon (Ar).
According to an embodiment, the inert gas may include nitrogen (N)2) And argon (Ar).
According to an embodiment, the sodium hypochlorite (NaOCl) may be applied by a dropper.
According to an embodiment, the method may further comprise: forming a buffer layer on the substrate after the step of preparing the substrate and before the step of forming the active layer.
The method of manufacturing a semiconductor element according to an embodiment may include: forming an active layer having a crystalline two-dimensional layered structure on the substrate; wet etching the active layer by applying sodium hypochlorite (NaOCl) to the active layer, forming an active pattern; and removing a residue generated by the wet etching using purified water and an inert gas.
Embodiments may relate to a method of manufacturing a semiconductor element. The method may comprise the steps of: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer may include a crystalline two-dimensional layer; forming a source electrode and a drain electrode on the semiconductor layer; forming a semiconductor member by wet etching the semiconductor layer using sodium hypochlorite, wherein the wet etching may result in a residue; and removing the residue using purified water and an inert gas.
The semiconductor layer may include at least one of molybdenum disulfide, molybdenum diselenide, and molybdenum ditelluride.
The molybdenum disulfide may be produced by synthesis from molybdenum chloride and hydrogen sulfide at a temperature in a range of 650 degrees celsius to 750 degrees celsius for a length of time in a range of 13 minutes to 17 minutes.
The molybdenum disulfide may be produced by synthesis from molybdenum chloride and hydrogen sulfide at 700 degrees celsius for 15 minutes.
The semiconductor layer may include at least one of tungsten disulfide, tungsten diselenide, and tungsten ditelluride.
The semiconductor layer may include at least one of zirconium disulfide and zirconium diselenide.
The semiconductor layer may include at least one of hafnium disulfide and hafnium diselenide.
The semiconductor layer may include at least one of platinum disulfide and platinum diselenide.
The semiconductor layer may include at least one of rhenium disulfide and rhenium diselenide.
The source electrode and the drain electrode may be formed by a lithography process.
The source electrode and the drain electrode may include one or more of titanium and silver.
The method may further comprise the steps of: forming a gate insulating layer on the semiconductor member; forming a gate electrode on the gate insulating layer; and forming an interlayer insulating layer on the gate electrode.
The method may further comprise the steps of: forming a first contact hole in the interlayer insulating layer and the gate insulating layer, the first contact hole exposing the source electrode; and forming a source member on the interlayer insulating layer, the source member filling the first contact hole.
The method may further comprise the steps of: forming a second contact hole in the interlayer insulating layer and the gate insulating layer, the second contact hole exposing the drain electrode; and forming a drain member on the interlayer insulating layer, the drain member filling the second contact hole.
The inert gas may include nitrogen.
The inert gas may include argon.
The inert gas may include a mixed gas of nitrogen and argon.
The sodium hypochlorite can be applied to the semiconductor layer by a dropper.
The method may further comprise: forming a buffer layer on the substrate after the step of preparing the substrate and before the step of forming the semiconductor layer.
According to the embodiment, in the method of manufacturing the semiconductor element, a process of etching the active layer/semiconductor layer may be very simple, a time required for etching the active layer/semiconductor layer may be minimized, and/or a cost of etching the active layer/semiconductor layer may be saved.
Drawings
Fig. 1 is a sectional view illustrating a display device according to an embodiment.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are diagrams illustrating structures formed in a method of manufacturing a semiconductor element according to at least one embodiment.
Detailed Description
Illustrative embodiments are described with reference to the drawings. Although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. A first element could be termed a second element without departing from the teachings of one or more embodiments. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may be used to distinguish different types or sets of elements. For brevity, the terms "first", "second", etc. may represent "a first type (or first set)", "a second type (or second set)", etc., respectively. The term "connected" may mean "electrically connected" or "not electrically connected through intervening elements. The term "insulating" may mean "electrically insulating" or "electrically isolating". The term "conductive" may mean "conductive". The term "semiconductor element" may mean a "switching element" or a "transistor". The term "pattern" may mean "member". The bill of materials may mean at least one of the listed materials. The term "active" may mean "semiconductor". The term "comprising" may mean "formed from … …".
Fig. 1 is a sectional view illustrating a display device according to an embodiment.
Referring to fig. 1, the display apparatus 1000 may include a substrate 110, a buffer layer 120, a gate insulating layer 140, an interlayer insulating layer 150, a via hole insulating layer 160, a semiconductor element 300, a pixel defining layer PDL, and an organic light emitting diode OLED. The semiconductor element 300 may include a source electrode 131, a drain electrode 132, an active pattern (also referred to as a semiconductor member) 133, a gate electrode 135, a source pattern 136, and a drain pattern 137. The organic light emitting diode OLED may include a lower electrode 170, an emission layer 180, and an upper electrode 190.
The substrate 110 may include one or more transparent and/or opaque materials. The substrate 110 may be formed of a flexible transparent resin. The substrate 110 may include a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer, which are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material. The substrate 110 may be/include at least one of a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, and an alkali-free glass substrate.
The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may cover the entire face or surface of the substrate 110. The buffer layer 120 may prevent metal atoms or impurities from diffusing from the substrate 110 to the semiconductor element 300. The buffer layer 120 may improve the flatness of the surface of the substrate 110 if the surface of the substrate 110 is not uniform. Two or more may be provided on the substrate 110A buffer layer. The buffer layer 120 may be optional. The buffer layer 120 may include a silicon compound, a metal oxide, and the like. For example, the buffer layer 120 may include silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) Silicon oxycarbide (SiO)xCy) Silicon carbide nitride (SiC)xNy) Aluminum oxide (AlO)x) Aluminum nitride (AlN)x) Tantalum oxide (TaO)x) Hafnium oxide (HfO)x) Zirconium oxide (ZrO)x) And titanium oxide (TiO)x) And the like.
The active pattern 133 may be disposed on the buffer layer 120. The active pattern 133 may include two-dimensional layers each including a single layer of atoms. The active pattern 133 may determine the performance of the semiconductor device 300.
The active pattern 133 may include Transition Metal Dichalcogenide (TMDC) and graphene. The transition metal dichalcogenide may include molybdenum disulfide (MoS)2) Molybdenum diselenide (MoSe)2) Molybdenum ditelluride (MoTe)2) Tungsten disulfide (WS)2) Tungsten diselenide (WSe)2) Tungsten ditelluride (WTE)2) Zirconium disulfide (ZrS)2) Zirconium diselenide (ZrSe)2) Hafnium disulfide (HfS)2) Hafnium diselenide (HfSe)2) Platinum disulfide (PtS)2) Platinum diselenide (PtSe)2) Rhenium disulfide (ReS)2) And rhenium diselenide (ReSe)2) And the like. The graphene may include at least one of hexagonal boron nitride graphene (hBN graphene: hexagonal boron nitride graphene), boron-nitrogen co-doped graphene (BCN graphene: boron-nitrogenco-doped graphene), and the like. The active pattern 133 may be made of molybdenum disulfide (MoS)2) And (4) forming.
The active pattern 133 may be formed by a wet etching process. The wet etching process may be performed using sodium hypochlorite (NaOCl).
The active pattern 133 may have a thinner thickness, a higher mobility, a higher on/off (on/off) current ratio, and/or a higher stability than a silicon-based active pattern or a metal oxide-based active pattern. The active pattern 133 may have a nano-platelet structure, may have a band gap, and may be suitable for the semiconductor element 300. In addition, since the active pattern 133 has flexibility, the active pattern 133 may be used for the semiconductor element 300 included in the flexible display device. The active pattern 133 may serve as a channel electrically connecting the source electrode 131 and the drain electrode 132.
The active pattern 133 may include a first region 10, a second region 20 spaced apart from the first region 10, and a third region 30 between the first region 10 and the second region 20.
The source electrode 131 may be disposed on the first region 10 of the active pattern 133. The drain electrode 132 may be disposed on the second region 20 of the active pattern 133. The source electrode 131 and the drain electrode 132 may include titanium (Ti) and/or silver (Ag). The source electrode 131 and the drain electrode 132 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. For example, the source electrode 131 and the drain electrode 132 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), aluminum nitride (AlN)x) Silver (Ag) -containing alloy, tungsten (W), and tungsten nitride (WN)x) Copper (Cu) -containing alloy, molybdenum (Mo) -containing alloy, and titanium nitride (TiN)x) Tantalum nitride (TaN)x) Strontium ruthenium oxide (SrRu)xOy) Zinc oxide (ZnO)x) Indium Tin Oxide (ITO) and tin oxide (SnO)x) Indium oxide (InO)x) Gallium oxide (GaO)x) And Indium Zinc Oxide (IZO), and the like.
The source electrode 131 and the drain electrode 132 may be formed by a lithographic (photolithography) process.
The gate insulating layer 140 may be disposed on the buffer layer 120. The gate insulating layer 140 may cover the active pattern 133, the source electrode 131, and the drain electrode 132. The gate insulating layer 140 may have a substantially flat top surface without generating steps around the active pattern 133, the source electrode 131, and the drain electrode 132. Alternatively, the gate insulating layer 140 may cover the active pattern 133, the source electrode 131, and the drain electrode 132 on the buffer layer 120, and may be disposed at a substantially uniform thickness along the outline of the active pattern 133, the source electrode 131, and the drain electrode 132.
The gate insulating layer 140 may include a material having a high dielectric constant. For example, the gate insulating layer 140 may include a transition metal such as hafnium, zirconium, or tantalum.
The gate electrode 135 may be disposed on the gate insulating layer 140 and may overlap the third region 30. The gate electrode 135 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. For example, the gate electrode 135 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), aluminum nitride (AlN)x) Silver (Ag) -containing alloy, tungsten (W), and tungsten nitride (WN)x) Copper (Cu) -containing alloy, molybdenum (Mo) -containing alloy, and titanium nitride (TiN)x) Tantalum nitride (TaN)x) Strontium ruthenium oxide (SrRu)xOy) Zinc oxide (ZnO)x) Indium Tin Oxide (ITO) and tin oxide (SnO)x) Indium oxide (InO)x) Gallium oxide (GaO)x) And Indium Zinc Oxide (IZO), and the like. One or more of the foregoing materials may be used alone or in combination to form the gate electrode 135.
An interlayer insulating layer 150 may be disposed on the gate insulating layer 140. The interlayer insulating layer 150 may cover the gate electrode 135. The interlayer insulating layer 150 may include a silicon compound or a metal oxide, etc. For example, the interlayer insulating layer 150 may include silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) Silicon oxycarbide (SiO)xCy) Silicon carbide nitride (SiC)xNy) Aluminum oxide (AlO)x) Aluminum nitride (AlN)x) Tantalum oxide (TaO)x) Hafnium oxide (HfO)x) Zirconium oxide (ZrO)x) And titanium oxide (TiO)x) And the like. The interlayer insulating layer 150 may be formed using one or more of the foregoing materials alone or in combination.
The source and drain patterns 136 and 137 may be disposed on the interlayer insulating layer 150. The source pattern 136 may be connected to the source electrode 131 through a first contact hole formed in the gate insulating layer 140 and the interlayer insulating layer 150. The drain pattern 137 may be connected to the drain electrode 132 through a second contact hole formed in the gate insulating layer 140 and the interlayer insulating layer 150. The source pattern 136 may fill the first contact hole. The drain pattern 137 may fill the second contact hole. Each of the source and drain patterns 136 and 137 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. One or more of the foregoing materials may be used alone or in combination to form the source and drain patterns 136 and 137.
Referring to fig. 1, a semiconductor device 300 may have an upper gate structure. In another embodiment, the semiconductor device 300 may have a bottom gate structure. In yet another embodiment, the semiconductor element 300 may have a double gate structure. A separate conductive layer and/or a separate insulating layer may be disposed between at least two of the source pattern 136, the drain pattern 137, and the interlayer insulating layer 150.
The via insulating layer 160 may be disposed on the interlayer insulating layer 150. The via insulating layer 160 may cover the source pattern 136 and the drain pattern 137. The via insulating layer 160 may be thicker than the interlayer insulating layer 150. The via insulating layer 160 may have a substantially flat top surface. A planarization process may be applied to the via insulating layer 160 to achieve a flat top surface of the via insulating layer 160. Alternatively, the via insulating layer 160 may have a substantially uniform thickness and may be disposed along the contour of the source and drain patterns 136 and 137. The via insulating layer 160 may be made of an organic material and/or an inorganic material. The via insulating layer 160 may include an organic material such as polyacrylic resin, polyimide resin, polyamide resin, acrylic resin, or epoxy resin.
The lower electrode 170 may be disposed on the via insulating layer 160. The lower electrode 170 may be connected to the drain pattern 137 through a third contact hole formed in the via hole insulating layer 160. The lower electrode 170 may be electrically connected to the semiconductor element 300 through the third contact hole. The lower electrode 170 may include metal, alloy, goldThe metal oxide is nitride, conductive metal oxide, transparent conductive material, and the like. For example, the lower electrode 170 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), aluminum nitride (AlN)x) Silver (Ag) -containing alloy, tungsten (W), and tungsten nitride (WN)x) Copper (Cu) -containing alloy, molybdenum (Mo) -containing alloy, and titanium nitride (TiN)x) Tantalum nitride (TaN)x) Strontium ruthenium oxide (SrRu)xOy) Zinc oxide (ZnO)x) Indium Tin Oxide (ITO) and tin oxide (SnO)x) Indium oxide (InO)x) Gallium oxide (GaO)x) And Indium Zinc Oxide (IZO), and the like. One or more of the foregoing materials may be used alone or in combination to form the lower electrode 170.
The pixel defining layer PDL may be disposed on the via insulating layer 160 and may expose at least a portion of the lower electrode 170. The pixel defining layer PDL may be made of an organic material and/or an inorganic material.
The emission layer 180 may be disposed on a face of the lower electrode 170 exposed by the pixel defining layer PDL. The emission layer 180 may emit red, green, or blue light.
The upper electrode 190 may be disposed on the pixel defining layer PDL and the emission layer 180. The upper electrode 190 may include the same material as the lower electrode 170.
The lower electrode 170 may be an anode electrode, and the upper electrode 190 may be a cathode electrode. In another embodiment, the lower electrode 170 may be a cathode electrode and the upper electrode 190 may be an anode electrode.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are diagrams illustrating structures formed in a method of manufacturing a semiconductor element according to at least one embodiment.
Referring to fig. 1 and 2A, a substrate 110 may be prepared. The substrate 110 may include a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer, which are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material.
The buffer layer 120 may be formed on the substrate 110. The buffer layer 120 may be formed on the entire face (e.g., the entire top surface) of the substrate 110. An active layer (also referred to as a semiconductor layer) 130 may be formed on the buffer layer 120. The active layer 130 may include two-dimensional layers each including a single layer of atoms. At least one of the two-dimensional layers may be a crystalline two-dimensional layer.
The active layer 130 may include a first region 10, a second region 20 spaced apart from the first region 10, and a third region 30 between the first region 10 and the second region 20 (i.e., the first region 10, the second region 20, and the third region 30 of the active pattern 133 shown in fig. 1).
The active layer 130 may include Transition Metal Dichalcogenide (TMDC) and graphene. The active layer 130 may include a molybdenum compound. For example, the active layer 130 may include molybdenum disulfide (MoS)2) Molybdenum diselenide (MoSe)2) And molybdenum ditelluride (MoTe)2) At least one of (1).
The active layer 130 may include a tungsten compound. For example, the active layer 130 may include tungsten disulfide (WS)2) Tungsten diselenide (WSe)2) And tungsten ditelluride (WTE)2) At least one of (1).
The active layer 130 may include a zirconium compound. For example, the active layer 130 may include zirconium disulfide (ZrS)2) And zirconium diselenide (ZrSe)2) At least one of (1).
The active layer 130 may include a hafnium compound. For example, the active layer 130 may include hafnium disulfide (HfS)2) And hafnium diselenide (HfSe)2) At least one of (1).
The active layer 130 may include a platinum compound. For example, the active layer 130 may include platinum disulfide (PtS)2) And platinum diselenide (PtSe)2) At least one of (1).
The active layer 130 may include a rhenium compound. For example, the active layer 130 may include rhenium disulfide (ReS)2) And rhenium diselenide (ReSe)2) At least one of (1).
The graphene may include at least one of hexagonal boron nitride graphene, boron-nitrogen co-doped graphene, and the like.
In an embodiment, the active layer 130 may include molybdenum disulfide (MoS)2). For example, the active layer 130 may include crystalline molybdenum disulfide (MoS)2). Can be prepared by using molybdenum chloride (MoCl)5) And hydrogen sulfide (H)2S) synthetic production of molybdenum disulfide (MoS)2). Molybdenum disulfide (MoS)2) The synthesis of (a) may be performed at one or more temperatures in the range of about 650 degrees celsius to about 750 degrees celsius for a time period in the range of about 13 minutes to about 17 minutes. Molybdenum disulfide (MoS)2) The synthesis of (a) may be performed at about 700 degrees celsius for about 15 minutes.
The active layer 130 may have a thinner thickness, higher mobility, higher on/off current ratio, and/or higher stability than a silicon-based active layer or a metal oxide-based active layer for more desirable performance of the semiconductor element 300.
Referring to fig. 1 and 2B, a source electrode 131 may be disposed on the first region 10 of the active layer 130. The drain electrode 132 may be disposed on the second region 20 of the active layer 130. The source electrode 131 and the drain electrode 132 may include at least one of titanium (Ti) and silver (Ag). The source electrode 131 and the drain electrode 132 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like.
The source electrode 131 and the drain electrode 132 may be formed by a lithography process. For example, the source electrode 131 and the drain electrode 132 may be formed by a photolithography (photolithography) process. In an embodiment, after forming a conductive layer covering the face of the active layer 130, the conductive layer is etched by a photolithography process to form the source electrode 131 and the drain electrode 132.
Referring to fig. 1, 2C and 2D, an etching process may be performed to form the active pattern 133. The etching process may be a wet etching process. When the active layer 130 is etched by the dry etching process, a large-scale apparatus may be required. If the active layer 130 is etched by a dry etching process, the time required for the etching may be undesirably long. Thus, process throughput may be undesirably low.
In an embodiment, the active layer 130 may be etched using a wet etching process. Sodium hypochlorite (NaOCl) may be used in the wet etching process. As shown in FIG. 2C, canTo apply sodium hypochlorite (NaOCl) to the remaining regions 40 and 50 of the active layer 130 except for the first, second and third regions 10, 20 and 30 by a dropping tube 200. Molybdenum disulfide (MoS) of active layer 130 in remaining regions 40 and 50 may be etched by sodium hypochlorite (NaOCl)2). The wet etching process may be performed at room temperature. The wet etching process may be performed for several seconds. The wet etching process can be completed in a short time using equipment smaller than that required for the conventional dry etching method.
Referring to fig. 1 and 2D, after a wet etching process is performed to form the active pattern 133, a residue remaining on the buffer layer 120 may be removed. The removal of the residue can be performed using purified water and inert gas. For example, after spraying purified water, the residue may be removed using an inert gas. The inert gas may include nitrogen (N)2). The inert gas may include argon (Ar). The inert gas may comprise a mixed gas comprising nitrogen (N)2) And argon (Ar).
Referring to fig. 1 and 2E, a gate insulating layer 140 may be formed on the active pattern 133. The gate insulating layer 140 may cover the active pattern 133, the source electrode 131, and the drain electrode 132.
Referring to fig. 1 and 2F, a gate electrode 135 may be formed on the gate insulating layer 140 to overlap the third region 30 of the active pattern 133. The gate electrode 135 may be formed by etching a conductive pattern formed on the gate insulating layer 140. The gate electrode 135 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.
Referring to fig. 1 and 2G, an interlayer insulating layer 150 may be formed on the gate insulating layer 140. The interlayer insulating layer 150 may cover the gate electrode 135. The interlayer insulating layer 150 may completely or substantially cover an exposed portion of a face (e.g., a top face) of the gate insulating layer 140.
A source pattern 136 and a drain pattern 137 may be formed on the interlayer insulating layer 150. A first contact hole for exposing the source electrode 131 may be formed by removing portions of the interlayer insulating layer 150 and the gate insulating layer 140. The source pattern 136 may fill the first contact hole. A second contact hole for exposing the drain electrode 132 may be formed by removing portions of the interlayer insulating layer 150 and the gate insulating layer 140. The drain pattern 137 may fill the second contact hole. The source pattern 136 may be (directly) connected to the source electrode 131 through a first contact hole, and the drain pattern 137 may be (directly) connected to the drain electrode 132 through a second contact hole.
Referring to fig. 1, a via hole insulating layer 160 covering the interlayer insulating layer 150, the source pattern 136, and the drain pattern 137 may be formed on the interlayer insulating layer 150. A pixel defining layer PDL may be formed on the via insulating layer 160. An organic light emitting diode OLED including a lower electrode 170, an emission layer 180, and an upper electrode 190 may be formed on the via insulating layer 160. The organic light emitting diode OLED and the semiconductor element 300 may be electrically connected.
While the illustrative embodiments have been described, various modifications may be applied to the illustrative embodiments and are within the scope of the appended claims.
- 上一篇：一种医用注射器针头装配设备
- 下一篇：一种功率模块的制造方法