Synaptic transistor device based on novel polyimide gate insulating layer and preparation method thereof
阅读说明：本技术 一种基于聚酰亚胺新型栅绝缘层的突触晶体管器件及其制备方法 (Synaptic transistor device based on novel polyimide gate insulating layer and preparation method thereof ) 是由 徐文涛 龚江东 卫欢欢 于 2021-08-17 设计创作，主要内容包括：本发明为一种基于聚酰亚胺新型栅绝缘层的突触晶体管器件及其制备方法。所述的人工突触器件结构包括：衬底上分布部分栅绝缘层,栅绝缘层上依次为半导体层和金属层；所述栅绝缘层为掺杂有离子液体的聚酰亚胺类材料,半导体层为聚3-己基噻吩(P3HT)。本发明的突触晶体管器件具有灵敏度高,功耗低,工作电压范围大等优点。(The invention relates to a synapse transistor device based on a polyimide novel gate insulation layer and a preparation method thereof. The artificial synapse device structure comprises: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer; the gate insulating layer is made of polyimide materials doped with ionic liquid, and the semiconductor layer is poly-3-hexylthiophene (P3 HT). The synapse transistor device has the advantages of high sensitivity, low power consumption, large working voltage range and the like.)
1. A synapse transistor device based on polyimide novel gate insulation layer, characterized in that said artificial synapse device structure comprises: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer;
the gate insulating layer is made of polyimide materials doped with ionic liquid, and the mass of the ionic liquid is 5-20% of that of the gate insulating layer; the semiconductor layer is a thiophene polymer;
the area of the gate insulating layer is 70-90% of the area of the substrate.
2. The polyimide novel gate insulator based synaptic transistor device of claim 1, wherein said gate insulator has a thickness of 2-20 microns;
the thickness of the semiconductor layer is 30-100 nanometers;
the metal layer is a left metal electrode and a right metal electrode on the surface of the semiconductor layer, and the metal layer is made of gold;
the horizontal distance between the left electrode and the right electrode is 100-150 microns, and the thickness is 80-100 nanometers.
3. The polyimide novel gate insulator based synaptic transistor device of claim 1, wherein said polyimide based material comprises but is not limited to one of BPEDA-ODA type polyimide, PMDA-ODA type polyimide, or BPDA-ODA type polyimide;
the ionic liquid comprises but is not limited to one of 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imide ([ EMIM ] [ TFSI ]), 1-ethyl-3-methylimidazoline tetrafluoroborate ([ EMIM ] BF4) and 1-ethyl-3-methylimidazoline hexafluorophosphate ([ EMIM ] PF 6);
the semiconductor layer is polythiophene, poly 3 hexyl thiophene or poly 3 bromohexyl thiophene.
4. The polyimide novel gate insulator based synaptic transistor device of claim 1, wherein said substrate is quartz glass, silicon wafer, or indium tin oxide conducting glass.
5. The method of claim 1, wherein the method comprises the steps of:
(1) the substrate is sequentially subjected to ultrasonic cleaning by deionized water, acetone and isopropanol, then the surface of the substrate is dried by nitrogen, and the substrate is placed in an ultraviolet cleaning machine for treatment for 15-20 minutes;
(2) dripping the polyimide precursor solution on the substrate obtained in the step (1) in a glove box, spin-coating for 20-40 seconds at the speed of 500-2000 rpm by using a spin coater, placing the substrate on a heating plate, and heating at the temperature of 150-250 ℃ for 20-40 minutes to obtain a gate insulating layer;
wherein the polyimide precursor solution is prepared from ionic liquid and 10-20% by mass of a polyamic acid solution; is mixed according to the mass ratio of 1 to 10-20.
(3) Dripping the P3HT precursor solution on the gate insulating layer in the step (2), spin-coating for 20-40 seconds by using a spin coater at the speed of 1000-2000 rpm, then placing the substrate on a heating plate, and heating for 5-20 minutes at 50-100 ℃ to obtain a semiconductor layer;
wherein, the P3HT precursor solution is obtained by adding chlorobenzene solvent into poly-3-hexylthiophene (P3HT) and then stirring, and the concentration is 5-10 mg per ml; dripping 60-100 microliters of P3HT precursor solution into each 2-4 square centimeters of gate insulating layer;
(4) obtaining left and right source-drain electrodes on the surface of a semiconductor by a thermal evaporation technology, then removing a gate insulating layer and a semiconductor layer which cover partial areas on the surface of a substrate, exposing partial substrate to be used as a gate electrode, and finally obtaining a complete synapse transistor device based on the polyimide novel gate insulating layer;
wherein the thermal evaporation parameters are that the temperature is controlled at 40-50 ℃ and the vacuum degree is 10-3-10-4The deposition rate is 0.8-1 angstrom/s, and the evaporation time is 30-40 min.
6. The method of claim 5, wherein the polyamic acid solution is poly (biphenylbisether dianhydride-co-4, 4' -oxydianiline) (BPEDA-ODA) amic acid solution, poly (pyromellitic dianhydride-co-4, 4' -oxydianiline) (PMDA-ODA) amic acid solution or poly (biphenyltetracarboxylic dianhydride-co-4, 4' -oxydianiline) (BPDA-ODA) amic acid solution;
wherein the solvent in the BPEDA-ODA amic acid solution is N, N' -dimethylacetamide (DMAc), the solvent in the PMDA-ODA amic acid solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1, and the solvent in the BPDA-ODA amic acid solution is N-methylpyrrolidone (NMP); every 2-4 square centimeters of substrate is dripped with 200-400 microliter of polyimide precursor solution.
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a synaptic transistor electronic device.
Background
Due to the separation of storage and a computing module, a computing system based on the von Neumann structure cannot realize rapid accuracy and intellectualization when processing massive information, and particularly, a plurality of short boards are exposed in pattern recognition and deep learning. Meanwhile, the high intelligence and the strong computing and processing capability of the human brain make brain-like intelligent computing receive more and more extensive attention.
The human brain is a complex and huge neural network system, and only consumes very low energy while a large amount of nonlinear data can be processed in parallel. The human brain is composed of nearly billions of neurons with thousands of synapses between each neuron. The neural computing system based on the neural network has the most basic information transmission, processing and storage unit, namely synapses, and provides a direct research model and basis for brain-like research. Therefore, in order to realize various complex functions of human brain such as memory, calculation, cognition and the like on the hardware level, the design and manufacture of a novel artificial synapse device with small size, low energy consumption and high sensitivity is the most critical task at present. The novel artificial synapse device is a basic functional unit in a human brain computer, is used in emerging fields of intelligent robots, difficult and complicated disease medical diagnosis and the like, and has important significance for promoting the development of new-generation artificial intelligence.
Disclosure of Invention
The invention aims to solve the problems of larger power consumption, smaller working voltage range and the like of an organic polymer synaptic transistor device, and provides a synaptic transistor device based on a novel polyimide gate insulating layer and a preparation method thereof. The device takes polyimide doped with ionic liquid 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imide ([ EMIM ] [ TFSI ]) as a gate insulating layer, and takes poly 3-hexylthiophene (P3HT) as a semiconductor layer material; in the preparation process, ionic liquid [ EMIM ] [ TFSI ] and PMDA-ODA type polyimide are used as raw materials of an insulating layer, and a substrate/gate insulating layer/semiconductor layer/metal electrode structured three-terminal synaptic transistor device is prepared on an indium tin oxide conductive glass substrate by respectively utilizing spin coating and evaporation processes.
The technical scheme of the invention is as follows:
a synapse transistor device based on polyimide novel gate insulation layer, said artificial synapse device structure comprising: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer;
the substrate is made of glass;
the gate insulating layer is made of polyimide materials doped with ionic liquid, and the mass of the ionic liquid is 5-20% of that of the gate insulating layer; the thickness is 2-20 microns;
the semiconductor layer is a thiophene polymer and has a thickness of 30-100 nanometers;
the metal layer is a left metal electrode and a right metal electrode on the surface of the semiconductor layer, and the metal layer is made of gold;
the area of the gate insulating layer is 70-90% of the area of the substrate.
The horizontal distance between the left electrode and the right electrode is 100-150 microns, and the thickness is 80-100 nanometers.
The substrate is quartz glass, silicon chip or indium tin oxide conductive glass.
The polyimide material comprises but is not limited to one of BPEDA-ODA type polyimide, PMDA-ODA type polyimide or BPDA-ODA type polyimide;
the ionic liquid comprises but is not limited to one of 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imide ([ EMIM ] [ TFSI ]), 1-ethyl-3-methylimidazoline tetrafluoroborate ([ EMIM ] BF4) and 1-ethyl-3-methylimidazoline hexafluorophosphate ([ EMIM ] PF 6).
The semiconductor layer is polythiophene, poly 3 hexyl thiophene or poly 3 bromohexyl thiophene.
The preparation method of the synapse transistor device based on the polyimide novel gate insulation layer comprises the following steps:
(1) the substrate is sequentially subjected to ultrasonic cleaning by deionized water, acetone and isopropanol, then the surface of the substrate is dried by nitrogen, and the substrate is placed in an ultraviolet cleaning machine for treatment for 15-20 minutes;
(2) dripping the polyimide precursor solution on the substrate obtained in the step (1) in a glove box, spin-coating for 20-40 seconds at the speed of 500-2000 rpm by using a spin coater, placing the substrate on a heating plate, and heating at the temperature of 150-250 ℃ for 20-40 minutes to obtain a gate insulating layer;
wherein the polyimide precursor solution is prepared from ionic liquid and 10-20% by mass of a polyamic acid solution; is mixed according to the mass ratio of 1 to 10-20. The polyamic acid solution is specifically one of poly (biphenyl diether dianhydride-co-4, 4' -diaminodiphenyl ether) (BPEDA-ODA) amic acid solution, poly (pyromellitic dianhydride-co-4, 4' -diaminodiphenyl ether) (PMDA-ODA) amic acid solution or poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) (BPDA-ODA) amic acid solution; wherein the solvent in the BPEDA-ODA amic acid solution is N, N' -dimethylacetamide (DMAc), the solvent in the PMDA-ODA amic acid solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1, and the solvent in the BPDA-ODA amic acid solution is N-methylpyrrolidone (NMP); dripping 200-400 microliter of polyimide precursor solution on each 2-4 square centimeters of substrate;
(3) dripping the P3HT precursor solution on the gate insulating layer in the step (2), spin-coating for 20-40 seconds at the speed of 1000-2000 rpm by using a spin coater, then placing the substrate on a heating plate, and heating for 5-20 minutes at 50-100 ℃ to obtain a hole transport layer;
wherein, the P3HT precursor solution is obtained by adding chlorobenzene solvent into poly-3-hexylthiophene (P3HT) and then stirring, and the concentration is 5-10 mg per ml; dripping 60-100 microliters of P3HT precursor solution into each 2-4 square centimeters of gate insulating layer;
(4) obtaining left and right source-drain electrodes on the surface of a semiconductor by a thermal evaporation technology, then removing a gate insulating layer and a semiconductor layer which cover partial areas on the surface of a substrate, exposing partial substrate to be used as a gate electrode, and finally obtaining a complete synapse transistor device based on the polyimide novel gate insulating layer;
wherein the thermal evaporation parameters are that the temperature is controlled at 40-50 ℃ and the vacuum degree is 10-3-10-4The deposition rate is 0.8-1 angstrom/s, and the evaporation time is 30-40 min.
The invention has the substantive characteristics that:
in the prior art, a simple polyimide gate insulating layer only contains a single ion: protons. The gate insulating layer has smaller specific capacitance and is easy to generate electric leakage phenomenon; in the invention, the PMDA-ODA type polyimide doped with the ionic liquid [ EMIM ] [ TFSI ] is used as the gate insulating layer, and a certain amount of the ionic liquid [ EMIM ] [ TFSI ] is doped into the polyimide to form multiple ions in the polyimide, so that the specific capacitance of the gate insulating layer is improved, the range of a working voltage interval is expanded, and the electrical performance of the device is improved. The novel grid dielectric layer with the multiple ion conductor films is prepared, the specific capacitance is large, the leakage current is small, and the grid insulating layer is uniform, compact and uniform in whole. The synapse transistor prepared on the basis of the P3HT three-terminal (namely three ports of a grid electrode, a source electrode and a drain electrode of the thin film transistor) adopts a bottom-grid top contact structure, and a good interface contact can be formed between a grid insulation layer and a P3HT semiconductor.
The invention has the beneficial effects that:
the traditional three-terminal synaptic transistor based on the ionic glue type grid insulating layer mostly adopts a device structure with top grid top contact, the grid insulating layer mostly adopts a laminating mode to contact with a semiconductor layer, the laminating degree is poor, and a gap is easily formed between the grid insulating layer and the semiconductor layer. And the dielectric constant of the ion glue type grid insulating layer is small, and the electric leakage phenomenon is easy to occur under the stimulation of large voltage. The invention mixes the ionic liquid [ EMIM ] [ TFSI ] and the PMDA-ODA amic acid solution, and prepares the novel grid dielectric layer with the multiple ion conductor film by using the spin coating process, and the novel grid dielectric layer has larger specific capacitance and smaller leakage current. The gate insulating layer is integrally even, compact and uniform, and the synaptic transistor device with the bottom gate top contact structure prepared on the basis has the advantages of high sensitivity, low power consumption, large working voltage range and the like.
As shown in fig. 3, the specific capacitance per unit area of the novel gate insulating layer can exceed 7 microfarads per square centimeter at a frequency of 1000 hz; the working voltage can reach-50V (shown in figure 4); the minimum energy consumption is less than 1 flying coke (fig. 5).
Drawings
FIG. 1 is a schematic diagram of a structure of a synapse transistor device based on a polyimide-based novel gate insulator layer;
fig. 2 is a scanning electron microscope photograph of the novel polyimide gate insulating layer obtained in example 1.
Fig. 3 is a voltage-capacitance graph of the novel polyimide gate insulating layer obtained in example 1.
FIG. 4 is a transfer curve for a polyimide based novel gate insulator layer based synaptic transistor device obtained in example 1.
FIG. 5 is the current response at-0.1V to-1V for the polyimide based novel gate insulator based synaptic transistor device obtained in example 1.
The specific implementation mode is as follows:
the present invention will now be described in detail with reference to specific examples, which are provided to assist persons in studying and thinking the invention and are not intended to limit the invention in any way.
The materials of the BPEDA-ODA type polyimide, the PMDA-ODA type polyimide and the BPDA-ODA type polyimide related to the invention are all known materials. Specifically, the polyimide is poly (biphenyl diether dianhydride-co-4, 4' -diaminodiphenyl ether) (BPEDA-ODA) type polyimide, poly (pyromellitic dianhydride-co-4, 4' -diaminodiphenyl ether) (PMDA-ODA) type polyimide and poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) (BPDA-ODA) type polyimide.
The ionic liquid [ EMIM ] [ TFSI ] is specifically 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imide.
Example 1:
a preparation method of a synapse transistor device based on a polyimide novel gate insulation layer comprises the following steps:
(1) ultrasonically cleaning a conductive glass substrate with the size of 2 multiplied by 2 cm and the thickness of 2 mm by deionized water, acetone and isopropanol in sequence, then blowing the surface of the substrate by nitrogen, and placing the substrate into an ultraviolet cleaning machine for treatment for 15 minutes;
(2) mixing and uniformly stirring ionic liquid [ EMIM ] [ TFSI ] and a PMDA-ODA amic acid solution with the mass fraction of 12% (the solvent of the solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1.) according to the mass ratio of 1 to 20 to obtain a mixed solution of faint yellow clear PMDA-ODA type polyimide and the ionic liquid [ EMIM ] [ TFSI ].
(3) In a glove box, 200. mu.l of the mixed solution of PMDA-ODA type polyimide and ionic liquid [ EMIM ] [ TFSI ] in the step (2) was dropped onto a 4-cm square substrate in the step (1), followed by spin-coating for 30 seconds at 1500 rpm using a spin coater, and then the substrate was placed on a hot plate and heated at 150 ℃ for 30 minutes to obtain a gate insulating layer of 5 μm thickness.
(4) Chlorobenzene solvent was added to P3HT and stirred well to give a P3HT precursor solution with a concentration of 5 mg P3HT per ml chlorobenzene.
(5) And (3) dropwise adding 100 microliters of the P3HT precursor solution obtained in the step (4) onto the gate insulating layer obtained in the step (3), spin-coating for 30 seconds at a speed of 1500 rpm by using a spin coater, then placing the substrate on a heating plate, and heating at 60 ℃ for 10 minutes to obtain a high-quality hole transport layer with the thickness of 50 nanometers.
(6) Covering the mask plate (the areas of the left and right grooves of the mask plate are 1.5 mm/1 mm, the total area of the mask plate is 5 mm/5 mm, and the distance between the two grooves is 100 micrometers) on the upper surface of the semiconductor layer obtained in the step (5), and performing thermal evaporation (controlling the temperature of the chamber at 40-50 ℃ and the vacuum degree at 4/10)-4-5*10-4Pa, deposition rate 1 angstrom/second, evaporation time 30 minutes) to deposit gold electrodes with thickness of 100 nanometers and distance of 150 micrometers on the thin film surface of the groove part, and a blade is used to remove the gate insulating layer and the semiconductor layer in partial area of the upper surface of the substrate, the removed area is a rectangle with size of 1 x 1 centimeter, the position is the left lower corner edge of the upper surface of the substrate, and the exposed area is used as a gate electrode, thereby obtaining a complete synapse transistor device based on the polyimide novel gate insulating layer.
Performance testing and experimental result analysis:
electrical performance testing and analysis of the two-terminal artificial synapses in (6) was performed using a semiconductor analyzer Keithley 4200A-SCS with the following important results (test environment in nitrogen-sealed glove box, nitrogen purity greater than 99%, ambient temperature 20-25 degrees celsius):
the synapse transistor device based on the polyimide novel gate insulation layer in example 1 has good electrical performance and ultra-low power consumption. As shown in fig. 2, the novel polyimide gate insulating layer prepared by the spin coating process shows a uniform and flat surface topography in a SEM picture of 30 ten thousand times, and can form a good interface contact with the P3HT semiconductor layer. Specific surface capacitance in units of over 7 microfarads per square centimeter at a frequency of 1000 hertz (shown in figure 3); the working voltage of the three-terminal synaptic transistor with the bottom gate top contact prepared by the novel gate insulating layer can be widened to-50V, which is far more than that of the traditional ionic glue type synaptic transistor (shown in figure 4); the minimum power consumption of the synapse transistor based on the polyimide novel gate insulation layer is only 0.84 flying coke, and reaches the biological level.
Example 2:
a preparation method of a synapse transistor device based on a polyimide novel gate insulation layer comprises the following steps:
(1) ultrasonically cleaning a conductive glass substrate with the size of 2 multiplied by 2 cm and the thickness of 2 mm by deionized water, acetone and isopropanol in sequence, then blowing the surface of the substrate by nitrogen, and placing the substrate into an ultraviolet cleaning machine for treatment for 15 minutes;
(2) mixing and uniformly stirring ionic liquid [ EMIM ] [ TFSI ] and a PMDA-ODA amic acid solution with the mass fraction of 12% (the solvent of the solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1.) according to the mass ratio of 1 to 10 to obtain a mixed solution of faint yellow clear PMDA-ODA type polyimide and the ionic liquid [ EMIM ] [ TFSI ].
(3) In a glove box, 350. mu.l of the mixed solution of PMDA-ODA type polyimide and ionic liquid [ EMIM ] [ TFSI ] in step (2) was dropped onto a 4-cm-square substrate in step (1), followed by spin-coating for 30 seconds at 1000 rpm using a spin coater, and then the substrate was placed on a hot plate and heated at 150 ℃ for 20 minutes to obtain a 10-. mu.m-thick gate insulating layer.
(4) Chlorobenzene solvent was added to P3HT and stirred well to give a P3HT precursor solution with a concentration of 5 mg P3HT per ml chlorobenzene.
(5) And (3) dropwise adding 70 microliter of the P3HT precursor solution obtained in the step (4) onto the gate insulating layer obtained in the step (3), spin-coating for 30 seconds at the speed of 1000 revolutions per minute by using a spin coater, then placing the substrate on a heating plate, and heating at 60 ℃ for 10 minutes to obtain a high-quality hole transport layer with the thickness of 70 nanometers.
(6) Covering the mask plate (the areas of the left and right grooves of the mask plate are 1.5 mm/1 mm, the total area of the mask plate is 5 mm/5 mm, and the distance between the two grooves is 100 micrometers) on the upper surface of the semiconductor layer obtained in the step (5), and performing thermal evaporation (controlling the temperature of the chamber at 40-50 ℃ and the vacuum degree at 4/10)-4-5*10-4Pa, deposition rate 1A/s, evaporation time 30 minutes) in the groove portionAnd gold electrodes with the thickness of 80 nanometers and the left-right spacing of 100 micrometers are deposited on the surface, the gate insulating layer and the semiconductor layer in partial areas on the upper surface of the substrate are removed by a blade, the removed areas are rectangles with the size of 1 multiplied by 1 centimeter and are positioned at the edges of the left lower corner of the upper surface of the substrate, and the exposed areas are used as gate electrodes, so that a complete synapse transistor device based on the novel polyimide gate insulating layer is obtained.
Example 3:
the other steps are the same as example 1 except that the polyamic acid solution in step (2) is replaced with a BPDA-ODA amic acid solution from a PMDA-ODA amic acid solution, wherein the solvent in the BPDA-ODA amic acid solution is N-methylpyrrolidone (NMP).
The above embodiments and test results are intended to provide researchers in the relevant field with a certain research basis. Any other simple experimental changes which are not substantial changes and include modifications, simplifications, substitutions and the like are all within the scope of the invention.
The invention is not the best known technology.