阅读说明：本技术 一种高速接口瞬断快速恢复的方法及系统 (Method and system for rapidly recovering instantaneous interruption of high-speed interface ) 是由 周慧 黄士超 于 2021-08-31 设计创作，主要内容包括：一种高速接口瞬断快速恢复的方法及系统,涉及光通信领域,方法包括：链路出现震荡且恢复稳定后,如果高速接口的lane通道个数大于1且出现通道故障,则强制出现故障的lane组的lane通道初始化,重新定帧并开始计时；如果出现故障的lane组内的lane通道在预设时间内没有全部恢复正常,则对出现故障的lane组的lane通道重新定帧,直至全部lane组无故障。本发明使多位宽的高速接口在链路瞬断情况下能够正常恢复,避免光线路保护倒换超时或者线路中断故障。(A method and a system for quickly recovering a high-speed interface transient interruption relate to the field of optical communication, and the method comprises the following steps: after the link vibrates and recovers to be stable, if the number of lane channels of the high-speed interface is more than 1 and a channel fault occurs, forcibly initializing the lane channels of the failed lane group, re-framing and starting timing; and if the lane channels in the lane group with the fault are not all recovered to be normal within the preset time, re-framing the lane channels of the lane group with the fault until all the lane groups have no fault. The invention enables the high-speed interface with multiple bit widths to be normally recovered under the condition of link instantaneous interruption, and avoids the overtime of optical line protection switching or line interruption faults.)

1. A method for quickly recovering a transient interruption of a high-speed interface is characterized by comprising the following steps:

after the link vibrates and recovers to be stable, if the number of lane channels of the high-speed interface is more than 1 and a channel fault occurs, forcibly initializing the lane channels of the failed lane group, re-framing and starting timing;

and if the lane channels in the lane group with the fault are not all recovered to be normal within the preset time, re-framing the lane channels of the lane group with the fault until all the lane groups have no fault.

2. A method for fast recovery of a high speed interface glitch as defined in claim 1, wherein the triggering condition of said method is: and judging whether the link is interrupted excessively according to a hardware LOS pin of the preceding-stage optical module, and if the link is interrupted excessively, triggering the method.

3. The method as claimed in claim 2, wherein the determining the link has a shock and is stable comprises:

and after the link is interrupted, continuously detecting the state of the link for many times, and if the interruption and recovery of the link occur for many times, after the link is stable and can continuously detect the signal frame head, reading the signal continuously and normally through the LOS pin of the hardware to determine that the link is vibrated and can recover stably.

4. The method for rapidly recovering from instantaneous interruption of a high-speed interface as claimed in claim 1, wherein the lane channel failure of the high-speed interface is judged by reading the land state of the PCS layer, and the number of the lane channels is obtained by inquiring and reading the information of the high-speed interface according to the land state of the PCS layer.

5. The method for rapidly recovering a snap of a high-speed interface as claimed in claim 1, wherein a framing manner corresponding to each lane channel is determined by a chip type; the preset time is less than 20 ms.

6. A system for fast recovery of a high speed interface glitch, comprising:

the detection jitter removal module is used for detecting whether the link generates oscillation or not;

the PCS state query module is used for acquiring the number of lane channels of the high-speed interface after the link is recovered to be stable and judging whether the lane channels are in fault;

the lane framing module is used for forcing the lane channels of the lane group with the fault to be initialized and re-framed when the number of the lane channels of the high-speed interface is more than 1 and the channel fault occurs;

the timer is used for timing the framing resetting of the lane framing module;

the control module is used for judging whether the link is stable or not and informing the PCS state query module through the detection debounce module; the system is also used for controlling the lane framing module to forcibly frame again according to the number of lane channels and the fault message of the PCS state query module; and is also used for controlling the timer to count time when the re-framing is started.

7. The system for rapidly recovering from a snap interruption of a high-speed interface as claimed in claim 6, further comprising a lane status recording and determining module for recording the statuses of the lane group and the lane channel at regular time, analyzing and determining whether the lane channel of the failed lane group completes the framing process within the timing period of the timer, and returning the result to the control module.

8. The system as claimed in claim 6, wherein the control module is further configured to determine whether the link is over-interrupted according to a hardware LOS pin of a preceding optical module, and trigger the de-jitter detection module to detect de-jitter after the link is over-interrupted.

9. The system for rapidly recovering from a transient interruption of a high-speed interface as claimed in claim 8, wherein said detection debounce module is configured to detect the status of the link continuously for a plurality of times after the link is interrupted, and if the link is interrupted and recovered for a plurality of times, after the link is stable and the signal frame header is continuously detected; and then the control module reads the LOS pin signal of the hardware to be continuously normal, and determines that the link has oscillation and is recovered to be stable.

10. The system for fast recovering from transient interruption of a high-speed interface as claimed in claim 6, wherein said PCS state query module is configured to determine whether a lane channel has a fault by reading a PCS layer lane state; and the device is also used for inquiring and reading the high-speed interface information according to the LANE state of the PCS layer and acquiring the number of the LANE channels.

Technical Field

The invention relates to the field of optical communication, in particular to a method and a system for quickly recovering a high-speed interface instantaneous interruption.

Background

The most important development trend of the IP network is ethernet, and the ethernet of data services has become a global leading trend; the accelerated innovation and evolution of the Ethernet technology lays a foundation for the future all-IP network bearing; flexible ethernet is becoming a key direction for future network development. In the first 30 years after ethernet birth, 6 ethernet speeds from 10M to 100GE were generated: 10M, 100M, GE, 10GE, 40GE, 100GE, is essentially a trend of 10-fold increase in rate every 10 years. But in the last 3 to 5 years, the new rate of ethernet began to exhibit a multidimensional evolution, and the industry began to be interested in another new 6-rate ethernet: including 25GE, 50GE, 200GE, 400 GE. There are also 3 ethernet rates (50GE, 200GE, 400GE) for which the current standard is in progress. Starting from 2015, the method is oriented to the requirements of cloud service, network slice, AR (Augmented Reality)/VR (Virtual Reality technology)/ultra-high definition video and other time delay sensitive services in a 5G network; by the innovation of interface technology, the evolution of high-speed large ports 400GE, 1TE and the like and the channelized realization of sub-rate bearing, hard pipeline and isolation and delay sensitive network technology are realized; an intelligent end-to-end link is further constructed, and a data network with guaranteed IP low time delay and high QoS service is realized. The rapid development of the high-speed Ethernet not only brings about the improvement of ten times of speed, but also brings about the further improvement of the comprehensive performance of the Ethernet while improving the speed of a single channel. The innovation of the high-speed Ethernet interface can enable wider application.

In a traditional Network topology, Optical line protection is often used in cooperation with an OTN (Optical Transport Network) device, so that data traffic is often carried by the OTN device and then encapsulated into an OTN signal to cooperate with link snap recovery, and a line side is a color Optical module. When the link is broken momentarily, the framing chip sends out an idle frame, so that the data service of the PTN (Packet Transport Network)/IP ran (IP Radio Access Network) device which is connected with the OTN does not sense the broken momentarily of the link.

With the frequent construction of urban construction roads, the situation that the electric layer is frequently switched due to the damage of the optical cable often occurs, and in order to improve the user experience, the frequent switching of the electric layer needs to be prevented through optical line protection. A scenario arises in which ethernet is used directly with optical line protection. Therefore, the application requirement that the high-speed Ethernet interface needs to be quickly recovered after the transient interruption recovery occurs is brought. And a white light/gray light module is used in a metropolitan area short-distance scene, photoelectric device units in the module can cause difference of skew values, and a packet processing chip cannot actively sense instantaneous disconnection of a link, so that the problem caused by abnormal skew cannot be processed, and therefore the problem that quick recovery is needed after the instantaneous disconnection is introduced is solved.

In the past, when the interface rate is relatively low, a single channel can independently bear corresponding flow, and as the interface rate is higher and higher, a high-rate interface needs a plurality of lanes (channels) to bear the flow. An 40/100G link is implemented by multiplexing multiple lanes, usually divided into 25G lanes or 10G lanes. The transmitting end generally divides 40/100G streams into 4 or 10 parallel channels, and the receiving end recombines the code streams of the parallel channels into 40/100G streams. Provision is made in the ethernet interface protocol for: alignment among a plurality of PCS Lanes is performed by using AM (alignment marker) among PCS (Physical Coding Sublayer) Lanes, and only after the AM of all PCS Lanes is aligned, the PCS can complete the deskew process, and then the process of recovering the Symbol code block into the Ethernet frame is started.

In an interface protocol of multiple serderselanes (for example, 100GE CAUI-4 uses servers at 4 to 25.78125 Gbps), in the process of optical layer protection switching and optical signal recovery, if the time interval of turning on and receiving light by multiple lasers in an optical module is greater than the deskew range tolerable between PCS lanes, AM code blocks between multiple PCS lanes cannot be aligned, and a port cannot be link, so that a data stream cannot be recovered.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for quickly recovering the transient interruption of a high-speed interface, so that the high-speed interface with multiple bit widths can be normally recovered under the condition of transient interruption of a link, and the overtime of optical line protection switching or the line interruption fault is avoided.

In order to achieve the above object, in one aspect, a method for quickly recovering a transient interruption of a high-speed interface is adopted, including:

after the link vibrates and recovers to be stable, if the number of lane channels of the high-speed interface is more than 1 and a channel fault occurs, forcibly initializing the lane channels of the failed lane group, re-framing and starting timing;

and if the lane channels in the lane group with the fault are not all recovered to be normal within the preset time, re-framing the lane channels of the lane group with the fault until all the lane groups have no fault.

Preferably, the triggering conditions of the method are as follows: and judging whether the link is interrupted excessively according to a hardware LOS pin of the preceding-stage optical module, and if the link is interrupted excessively, triggering the method.

Preferably, the determining that the link has oscillation and recovers to be stable includes:

and after the link is interrupted, continuously detecting the state of the link for many times, and if the interruption and recovery of the link occur for many times, after the link is stable and can continuously detect the signal frame head, reading the signal continuously and normally through the LOS pin of the hardware to determine that the link is vibrated and can recover stably.

Preferably, the lane channel fault of the high-speed interface is judged by reading the land state of the PCS layer, and the information of the high-speed interface is inquired and read according to the land state of the PCS layer, so that the number of lane channels is acquired.

Preferably, the framing mode corresponding to each lane channel is determined by the chip type; the preset time is less than 20 ms.

In another aspect, a system for fast recovery of a high-speed interface glitch is provided, including:

the detection jitter removal module is used for detecting whether the link generates oscillation or not;

the PCS state query module is used for acquiring the number of lane channels of the high-speed interface after the link is recovered to be stable and judging whether the lane channels are in fault;

the lane framing module is used for forcing the lane channels of the lane group with the fault to be initialized and re-framed when the number of the lane channels of the high-speed interface is more than 1 and the channel fault occurs;

the timer is used for timing the framing resetting of the lane framing module;

the control module is used for judging whether the link is stable or not and informing the PCS state query module through the detection debounce module; the system is also used for controlling the lane framing module to forcibly frame again according to the number of lane channels and the fault message of the PCS state query module; and is also used for controlling the timer to count time when the re-framing is started.

Preferably, the system also comprises a lane state recording and judging module, which is used for recording the states of the lane group and the lane channel at regular time, analyzing and judging whether the lane channel of the fault lane group completes the framing process within the timing period of the timer, and returning the result to the control module.

Preferably, the control module is further configured to determine whether the link is interrupted according to a hardware LOS pin of the preceding-stage optical module, and trigger the shake removal detection module to detect shake removal after the link is interrupted.

Preferably, the detection debounce module is configured to continuously detect a link state for multiple times after the link is interrupted, and if the link is interrupted and recovered for multiple times, the link is stable and can continuously detect a signal frame header; and then the control module reads the LOS pin signal of the hardware to be continuously normal, and determines that the link has oscillation and is recovered to be stable.

Preferably, the PCS state query module is configured to determine whether the lane channel fails by reading a lane state of the PCS layer; and the device is also used for inquiring and reading the high-speed interface information according to the LANE state of the PCS layer and acquiring the number of the LANE channels.

One of the above technical solutions has the following beneficial effects:

when the link oscillates due to interruption and recovers to be stable, the PCS state exception is used for triggering the whole high-speed interface recovery mechanism to prompt the lane channel to perform framing again and simultaneously, so that the received data can be aligned to recover the data stream. After the framing is finished, the states of all the lane channels are detected and recorded in a timing mode, and finally the normal data receiving and link recovery of the high-speed interface lane channels are achieved; the multi-bit wide high-speed interface can be normally recovered under the condition of link instantaneous interruption, and the optical line protection switching overtime or line interruption fault is avoided.

Drawings

FIG. 1 is a schematic diagram of a system for quickly recovering a transient interruption of a high-speed interface according to an embodiment of the present invention;

fig. 2 is a flowchart of a method for quickly recovering a transient interruption of a high-speed interface according to an embodiment of the present invention.

Description of the drawings:

10. detecting a debounce module; 20. a PCS state query module; 30. a lane framing module; 40. a timer; 50. a lane state recording and judging module; 60. and a control module.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The invention provides a method for quickly recovering a high-speed interface transient interruption, which comprises the following steps:

after the link is vibrated and is recovered to be stable, if the number of lane channels of the high-speed interface is more than 1 and a channel fault occurs, forcibly initializing the lane channels of the failed lane group, resetting frames and starting timing;

and if the lane channels in the lane group with the fault are not all recovered to be normal within the preset time, re-framing the lane channels of the lane group with the fault until all the lane groups have no fault.

The method can realize the normal recovery of the high-speed interface with multiple bit widths under the condition of link instantaneous interruption, and avoid the overtime of optical line protection switching or line interruption faults.

The condition for triggering the quick recovery method of the high-speed interface instantaneous interruption is that whether the link is interrupted excessively is judged according to a hardware LOS pin of the preceding-stage optical module, and if the link is interrupted, the method is triggered.

Further, after the method is triggered, an embodiment for judging whether the link has oscillation and recovers to be stable is provided, that is, whether the link has oscillation is judged according to the state change (link on-off) of the link in a continuous detection period by continuously detecting the state of the link for multiple times, and if the link has interruption and recovery for multiple times, after the link is stable and can continuously detect the signal frame head, the jitter removal effect is achieved, and the influence on the link recovery time caused by multiple times of lane sequencing during misjudgment or link oscillation is prevented. And then, continuously and normally reading a signal through a hardware LOS pin, and determining that the link has oscillation and is recovered to be stable. Specifically, when a hardware LOS pin signal is read, if 0 is read, the link is normal, and if 1 is read, the link is failed. The method for reading the LOS pin signal of the hardware can more directly judge whether the link is recovered stably.

Furthermore, the lane channel fault of the high-speed interface is judged by reading the land state of the PCS layer, when the land state is up, the lane channel is normal, and no processing is performed at this time; when the lane state is down, the lane failure is described, and the lane channel of the lane group with the failure needs to be forced to initialize and re-frame. The number of lane channels is also acquired by inquiring and reading the high-speed interface information according to the PCS layer lane state.

Each lane channel has a corresponding framing mode, and although the interfaces of the chips transmit data by adopting a plurality of lane channels, the framing modes are different due to different framing types of different chips, for example, the packet processing chip adopts an AM frame for framing.

In some embodiments, by setting a timer to time the re-framing of the lane channel, the framing period can be set by itself, and since the whole processing time is required to be within 50ms, if the setting is too large, the processing in one period may be unsuccessful, and the processing in the second period may fail, the framing period is recommended to be less than 20 ms. After the framing period, if the state of the lane channel is still abnormal, the framing is considered to fail again, and the framing needs to be performed again; if the read lane channel state is normal, the framing is successfully reset.

As shown in fig. 1, an embodiment of a system for fast recovery of a high-speed interface glitch is provided. In this embodiment, the system includes a jitter detection module 10, a PCS state query module 20, a lane framing module 30, a timer 40, and a control module 60.

The jitter detection and removal module 10 is configured to detect whether a link is oscillating. Specifically, the detection debounce module 10 may continuously detect the link state for multiple times, and analyze and judge whether the link vibrates according to the state change (link on-off) of the link in a continuous detection period, and if the link is interrupted and recovered for multiple times, perform the next operation after the link is stable and the signal frame header can be continuously detected, so as to achieve the debounce effect, and prevent the link recovery time from being affected by multiple times of lane sequencing during misjudgment or link vibration.

And the PCS state query module 20 is configured to, after the detection and processing performed by the debounce module 10, acquire the number of lane channels of the high-speed interface and determine whether the lane channels have a fault or not under the condition that the link is recovered to be stable. Specifically, the PCS state query module 20 reads the high-speed interface information to obtain the number of lane channels; meanwhile, the judgment is also carried out by reading whether the lane state of the PCS layer is up or down, the read lane state is returned to the control module 60, and if the lane state is up, no processing is carried out; if the lane status is down and the number of lane channels of the high-speed interface is greater than 1, the control module 60 starts the lane framing module 30.

And the lane framing module 30 is used for forcing the lane channels of the lane group with the fault to be initialized and re-framed when the number of the lane channels of the high-speed interface is greater than 1 and the lane channel fault occurs.

And the timer 40 is used for timing the Lane framing module for framing again. Preferably, the framing period is set within 20ms, and if the Lane group reading state is recovered to be normal within 20ms, the framing is considered to be successful again; if the lane reading state is still abnormal in 20ms or more than 20ms, the re-framing is considered to fail, and the re-framing is required.

A control module 60, configured to determine whether the link is stable, and notify the PCS state query module 20 by detecting the debounce module 10; the system is also used for controlling the lane framing module 30 to forcibly frame again according to the number of lane channels and the fault message of the PCS state query module 20; and also for controlling the timer 40 to count at the beginning of the reframing frame. Further, the control module 60 may determine whether the link is over-interrupted according to the hardware LOS pin of the preceding-stage optical module, and if the link is over-interrupted, the control module may trigger the detection debounce module 10 to enter the detection debounce process.

In some embodiments, the system further includes a lane status recording and determining module 50, configured to record the lane group and lane channel statuses at regular time, analyze and determine whether the lane channel of the failed lane group completes the framing process within the timing period of the timer 40, and return the result to the control module 60. Specifically, the lane channel state needs to be determined in the framing period of the timer 40, the lane channel state information may be acquired and recorded by the lane state recording and determining module 50, and in a normal state, it indicates that framing is completed, and the lane state recording and determining module 50 may be set to a 5ms polling mechanism.

As shown in fig. 2, in combination with the above system, a specific embodiment of a method for quickly recovering a transient interruption of a high-speed interface is provided, which includes the following steps:

and S101, the control module 60 judges that an interruption occurs according to a hardware LOS pin of a preceding-stage optical module, and triggers the detection debounce module 10.

S102, the detection jitter removal module 10 judges whether the link has oscillation and recovers stability, if so, the S103 is entered; if not, the detection is continued.

S103, the PCS state query module 20 judges whether the number of lane channels of the high-speed interface is greater than 1 and whether the lane channels have faults, and if so, the operation goes to S104; otherwise, the process proceeds to S102.

And S104, starting a timer 40 for recording the initial framing time of the lane channel and preventing the lane channel from generating the condition of initial framing timeout. And meanwhile, forcing all the lane channels of the lane group with the fault to enter an initialization state and resetting the frame.

S105, the lane state recording and judging module 50 acquires the states of the lane groups, records the states of the lane groups, judges whether the states of the lane groups are normal or not, does not perform any treatment if the states of the lane groups are normal, and ends the process; if not, the process proceeds to S106.

And S106, the lane state recording and judging module 50 judges and records the states of all lane channels in the fault lane group.

S107, judging whether the lane channels in all the lane groups return to normal or not according to the recorded lane channel states, and if so, turning to S102; if not, the process proceeds to S108.

S108, judging whether the Lane channel recovery time exceeds the set time of the timer 40, if so, turning to S104; if not, the process goes to S105, and the lane channel state is continuously recorded and judged.

When the link is interrupted, the processing flow is immediately carried out even if the link is once disconnected and then returns to normal, and finally the normal data receiving of the lane channel of the high-speed interface is realized, so that the high-speed interface with multiple bit widths can be normally recovered under the condition of link instantaneous interruption, and the optical line protection switching overtime or line interruption fault is avoided.

The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention.