阅读说明：本技术 用于电气距离的被动补偿 (Passive compensation for electrical distances ) 是由 J·F·施雷克 H·吉杜图里 于 2021-04-30 设计创作，主要内容包括：本申请案涉及用于电气距离的被动补偿。一种存储器装置的架构可利用针对存储器单元的传输路径电阻补偿方案,以减小存取存储器单元时寄生负载的影响。此存储器装置的存储器单元可经历包含与所述存储器单元的相应存取线相关联的传输路径电阻和附加补偿电阻在内的总电阻。前述存储器装置可利用尖峰缓解方案来缓解电压和/或冲击电流对所述存储器装置的附近存储器单元的有害影响。另外,尖峰缓解电路可包含耦合相应解码器附近的存取线上的电阻器。此外,尖峰缓解电路可包含耦合所述解码器之间的电阻器。(The present application relates to passive compensation for electrical distances. An architecture of a memory device may utilize a transmission path resistance compensation scheme for memory cells to reduce the effects of parasitic loading when accessing the memory cells. The memory cells of such a memory device may experience a total resistance including a transmission path resistance and an additional compensation resistance associated with the respective access line of the memory cells. The aforementioned memory devices may utilize a spike mitigation scheme to mitigate the deleterious effects of voltage and/or rush current on nearby memory cells of the memory device. In addition, the spike mitigation circuitry may include resistors coupled on the access lines near the respective decoders. Further, the spike mitigation circuitry may include a resistor coupled between the decoders.)

1. An apparatus, comprising:

a memory array;

a plurality of memory cells disposed at specified locations in the memory array;

a first plurality of access lines, wherein a first access line of the first plurality of access lines associated with accessing a target memory cell comprises a first current path configured to provide access to the target memory cell on a first side, and wherein the first current path comprises a first parasitic resistance associated with accessing the target memory cell; and

a second plurality of access lines, wherein a second access line of the second plurality of access lines associated with accessing the target memory cell comprises a second current path configured to provide access to the target memory cell on a second side, and wherein the second current path comprises a second parasitic resistance associated with accessing the target memory cell and a first compensation resistance associated with accessing the target memory cell.

2. The apparatus of claim 1, wherein a resistance value of the first compensation resistance is proportional to the first parasitic resistance.

3. The apparatus of claim 1, wherein the first compensation resistance comprises a first plurality of resistors disposed on the second access line of the second plurality of access lines between segments associated with the first access line of the first plurality of access lines.

4. The device of claim 3, wherein each of the fragments associated with the first access line of the first plurality of access lines comprises a portion of the first plurality of access lines.

5. The apparatus of claim 3, wherein the first plurality of resistors are disposed in series.

6. The apparatus of claim 1, wherein a resistance value of the second parasitic resistance associated with accessing the target memory cell and the first compensation resistance associated with accessing the target memory cell are proportional to a resistance value of the first parasitic resistance associated with a full length of the second corresponding access line.

7. The apparatus of claim 1, wherein the first current path comprises a second compensation resistance associated with accessing the target memory cell.

8. The apparatus of claim 7, wherein the second compensation resistance comprises a second plurality of resistors disposed on the first access line of the first plurality of access lines between segments associated with the second access line of the second plurality of access lines.

9. The apparatus of claim 8, wherein a resistance value of the first parasitic resistance associated with accessing the target memory cell and the second compensation resistance associated with accessing the target memory cell are proportional to a resistance value of the second parasitic resistance associated with a full length of the first respective access line.

10. The apparatus of claim 1, wherein the memory array comprises a cross-point memory array comprising a plurality of contiguous memory cells disposed between interleaved levels of the first and second pluralities of access lines.

11. The apparatus of claim 1, wherein a first decoder is coupled to an access line of the first plurality of access lines on a first side.

12. The apparatus of claim 1, wherein the second decoder is coupled to the plurality of first decoders on the second side.

13. A method for applying uniform resistance when accessing memory cells of a memory array, comprising:

compensating a parasitic resistance associated with accessing a memory cell on a first access line associated with accessing the memory cell on a second access line, wherein the compensating on the first access line comprises applying an additional resistance on the first access line; and

compensating for parasitic resistance associated with accessing the memory cell on the first access line on the second access line, wherein the compensating on the second access line comprises applying additional resistance on the second access line.

14. The method of claim 13, wherein the parasitic resistance and the additional resistance of the first access line are equal to a parasitic resistance associated with accessing a farthest memory cell on the second access line.

15. The method of claim 13, wherein the parasitic resistance and the additional resistance of the second access line are equal to a parasitic resistance associated with accessing a farthest memory cell on the first access line.

16. A semiconductor device, comprising:

a memory array comprising a plurality of memory cells, wherein a resistance associated with accessing a first memory cell of the plurality of memory cells is configured to be independent of a location of the first memory cell in the memory array;

a first plurality of access lines, wherein the first plurality of access lines are configured to access a first portion of the plurality of memory cells on a first side of the memory array, wherein a first access line of the first plurality of access lines is configured to provide a first access signal to access a second memory cell of the first portion of the first plurality of memory cells, and wherein a voltage associated with the first access signal is independent of a location of the second memory cell in the memory array.

17. The semiconductor device of claim 16, comprising a second plurality of access lines, wherein the second plurality of access lines are configured to access a second portion of the plurality of memory cells on a second side of the memory array, wherein a second access line of the second plurality of access lines is configured to provide a second access signal to access the second memory cell, and wherein a voltage associated with the second access signal is independent of the location of the second memory cell in the memory array.

18. The semiconductor device of claim 16, wherein the first access line of the first plurality of access lines is coupled to a respective first level decoder via a first resistor.

19. The semiconductor device of claim 18, wherein the first level decoder is coupled to a second level decoder via a second resistor.

20. The semiconductor device of claim 19, wherein the second resistor is programmable.

Technical Field

The present disclosure relates to memory devices, and in particular to passive compensation for electrical distance.

Background

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present technology that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

In general, a computing system includes: processing circuitry, such as one or more processors or other suitable components; and memory devices such as chips or integrated circuits. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible by the processing circuit. For example, based on user input to the computing system, the processing circuit may request the memory module to retrieve data corresponding to the user input from its memory device. In some cases, the retrieved data may include firmware, or instructions executable by the processing circuitry to perform operations, and/or may include data to be used as input for the operations. Additionally, in some cases, data output from the operation may be stored in memory to enable subsequent retrieval of the data from the memory.

Some of the memory devices include memory cells that can be accessed by turning on transistors that couple the memory cells (e.g., capacitors) with word lines or bit lines. In contrast, threshold type memory devices include memory devices that are accessed by providing a voltage across a memory cell, where a data value is stored based on the threshold voltage of the memory cell. For example, the data value may be based on whether a threshold voltage of the memory cell is exceeded, and in response to the voltage provided across the memory cell, the memory cell conducts current. The stored data value can be changed, for example, by applying a voltage sufficient to change the threshold voltage of the memory cell.

For threshold type memories, word lines and bit lines are used to transmit select signals to the respective memory cells. The select signals may include signals characterized by voltage levels used to save data into or retrieve data from the memory cells. The word lines and bit lines may be coupled to a selection signal source through a decoding circuit (e.g., a decoder). In a standard "bedding" architecture, a decoder may be coupled to one side of a word line or one side of a bit line.

The standard architecture of the memory cells in the memory device may cause different memory cells to have different physical distances on the word lines and bit lines from the decoder. The word lines and bit lines may each introduce a parasitic resistance on the memory cells depending on the location of the memory cells on the word line driver or the bit line driver. Memory cells disposed relatively far from decoders on respective word or bit lines may suffer from higher parasitic resistances introduced by the word or bit lines. However, memory cells disposed closer to decoders of respective word or bit lines may experience lower parasitic resistance. Furthermore, the memory cell may experience a net resistance due to parasitic resistances introduced by the word lines and bit lines. That is, different memory cells may experience different net parasitic resistances due to different distances of the memory cells from the decoder on their respective word lines and bit lines. Subsequently, during programming due to the high resistance path to the decoder, memory cells disposed on the word line or bit line relatively far away from the decoder may suffer from a low current delivery amplitude on the word line or bit line. Methods for uniform current delivery from the decoder to the memory cells may be needed.

Disclosure of Invention

An aspect of the present disclosure provides an apparatus, wherein the apparatus comprises: a memory array; a plurality of memory cells disposed at specified locations in the memory array; a first plurality of access lines, wherein a first access line of the first plurality of access lines associated with accessing a target memory cell comprises a first current path configured to provide access to the target memory cell, and wherein the first current path comprises a first parasitic resistance associated with accessing the target memory cell; and a second plurality of access lines, wherein a second access line of the second plurality of access lines associated with accessing the target memory cell comprises a second current path configured to provide access to the target memory cell on a second side, and wherein the second current path comprises a second parasitic resistance associated with accessing the target memory cell and a first compensation resistance associated with accessing the target memory cell.

Another aspect of the invention provides a method for applying uniform resistance when accessing memory cells of a memory array, wherein the method comprises: compensating a parasitic resistance associated with accessing a memory cell on a first access line associated with accessing the memory cell on a second access line, wherein the compensating on the first access line comprises applying an additional resistance on the first access line; and compensating for parasitic resistance on the second access line associated with accessing the memory cell on the first access line, wherein the compensating on the second access line comprises applying additional resistance on the second access line.

Another aspect of the present invention provides a semiconductor device, wherein the semiconductor device includes: a memory array comprising a plurality of memory cells, wherein a resistance associated with accessing a first memory cell of the plurality of memory cells is configured to be independent of a location of the first memory cell in the memory array; a first plurality of access lines, wherein the first plurality of access lines are configured to access a first portion of the plurality of memory cells on a first side of the memory array, wherein a first access line of the first plurality of access lines is configured to provide a first access signal to access a second memory cell of the first portion of the first plurality of memory cells, and wherein a voltage associated with the first access signal is independent of a location of the second memory cell in the memory array.

Drawings

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a block diagram of a portion of a memory according to an embodiment;

FIG. 2 is a diagram of a portion of the memory of FIG. 1, according to an embodiment;

FIG. 3 is a portion of a decoding circuit that may be used for a particular embodiment of the memory of FIG. 1 and the memory array of FIG. 2;

FIG. 4 is a diagram of a portion of the memory of FIG. 1 including a resistance compensation scheme, according to an embodiment;

FIG. 5 is a portion of the memory array of FIG. 2 including an alternative resistance compensation scheme in accordance with an embodiment;

FIG. 6 is a block diagram of a portion of the memory of FIG. 1 including an additional resistance for spike mitigation, according to an embodiment;

FIG. 7 is a schematic diagram depicting a first embodiment associated with the block diagram of FIG. 6; and

fig. 8 is a schematic diagram depicting a second embodiment associated with the block diagram of fig. 6.

Detailed Description

When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. One or more specific embodiments of the present invention described herein are described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

The memory generally includes an array of memory cells, with each memory cell coupled to at least two access lines. For example, a memory cell may be coupled to a bit line and a word line. Thus, each access line may be coupled to a large number of memory cells. To select a memory cell, decoder circuitry associated with a first access line for the memory cell and decoder circuitry associated with a second access line for the memory cell may provide both a voltage and/or current on the respective access lines. By applying voltages and/or currents to the respective access lines, the memory cells can be accessed in order to write data to and/or read data from the memory cells.

Since each access line may be coupled to a large number of memory cells, each memory cell may be at a different physical distance from the respective decoder circuit of the access line. Further, because the distance between the memory cells and the select signal source may be different, the parasitic load associated with each memory cell may vary based on the distance. The parasitic loads may include the resistance of the metal traces used to form the access lines, as well as parasitic capacitances associated with both the metal traces and associated decoder circuitry. Thus, due to the different physical distances from the respective decoder circuits of the access lines, each memory cell may have a different associated transmission path resistance or parasitic resistance, which is not negligible. The transmission path resistance associated with each memory cell may affect the voltage and/or current (e.g., a select signal) received by each memory cell when the respective decoder circuit provides the voltage and/or current to the respective access line of each memory cell. That is, while the voltage provided by the decoder circuit to the access line may be the same for each memory cell associated with the access line, the voltage received by a particular memory cell and the voltage delay associated with the received voltage may be different along the same access line than other memory cells. This is due to the location of the memory cell along the access line relative to the decoder circuit (e.g., the physical distance between the decoder circuit and the memory cell), the received voltage at the memory cell may vary, at least in part.

In view of the foregoing, when a select signal is provided to a memory cell, any transmission path resistance affecting memory cells disposed at the ends of the access lines can be compensated for using larger voltages and/or currents. However, this can result in current spikes and/or voltage spikes (e.g., voltages or currents greater than a threshold amount of voltage or current) being delivered to memory cells disposed closer to the decoder. Accordingly, there may be a need to improve the design of memory cell arrays to improve the delivery of select signals (e.g., reduce the likelihood and/or occurrence of current spikes and/or voltage spikes).

According to embodiments described herein, an architecture of a memory device may utilize a transmission path resistance compensation scheme of memory cells to reduce the impact of parasitic loads in accessing the memory cells. The memory cells of such a memory device may experience a total resistance including a transmission path resistance and an additional compensation resistance associated with the respective access lines of the memory cells. The memory device may compensate for the transmission path resistance of the respective bit line and the respective word line of the memory cell using a transmission path resistance compensation scheme as described in detail below.

In accessing each memory cell, a compensation resistance may be applied to any of the access lines of the memory cell, which may be proportional to the transmission path resistance of the opposite access line of the memory cell. In some embodiments, the memory device can include a predetermined total resistance associated with accessing the memory cell, and can include a transmission path resistance and an applied compensation resistance for a respective access line of the target memory cell. In these embodiments, the compensation resistance applied to the access lines can be inversely proportional to the transmission path resistance relative to the access lines to apply the predetermined total resistance. In view of the foregoing, the compensation resistance may be applied externally and/or passively to the access line.

The compensation resistance value may depend on the physical distance of the memory cell being accessed from the respective decoding circuit. In some examples, the compensation resistance can cause a total resistance of each memory cell of the memory device to be approximately equal to a transmission path resistance of a full length of the bit line and word line of the respective memory device. That is, the compensation resistance may scale up the total resistance of the memory cells such that the total resistance of each memory cell is approximately equal to the transmission path resistance between the decoder and the farthest memory cell of the memory device.

The transmission path resistance compensation scheme may allow a decoder of the memory device to provide the same voltage and/or current to access different memory cells. Furthermore, due to the equal total resistance of each memory cell, each memory cell may receive equal voltage and/or current regardless of its physical distance to the respective decoder. The transmission path resistance compensation scheme may require the decoder to provide a voltage and/or current proportional to the voltage and/or current required to access the farthest memory cell to access the different memory cells of such memory devices.

In some embodiments, the voltages provided by the decoders for accessing memory cells on the respective bit lines and/or word lines may initially include higher voltages and/or currents (e.g., voltage spikes, rush currents, or both). In these embodiments, memory cells near the decoder may experience voltage spikes, current spikes, or both, which may be undesirable or even disadvantageous for near memory cells.

Embodiments of the foregoing memory devices can utilize a spike mitigation scheme to mitigate the deleterious effects of voltage and/or rush current on the near memory cells of the memory device. In one embodiment, the spike mitigation circuitry may include resistors coupled on the access lines near the respective decoders. In other embodiments, the spike mitigation circuitry may include a resistor coupled between the decoders. Moreover, different embodiments may include selective coupling of one or more resistors on access lines near and/or between decoders. Specific embodiments of this architecture are described below.

In view of the foregoing, FIG. 1 is a block diagram of a portion of a memory 100. Memory 100 may be any suitable form of memory such as non-volatile memory (e.g., cross-point memory) and/or volatile memory. The memory 100 may include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decoding circuitry), and one or more bit line decoders 110 (e.g., bit line decoding circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may form a memory array 112.

Each of the memory cells 102 may include a selector and/or a storage element. When the voltage across the selector of the respective memory cell reaches a threshold value, the storage element can be accessed to read and/or write a data value from/to the storage element. In some embodiments, each of the memory cells 102 may not include a separate selector and storage element, and have a configuration such that the memory cells still function as having a selector and a storage element (e.g., may include using materials that behave similarly to both the selector material and the storage element material). When the memory cells 102 have a single material that acts as a selector and storage element, these architectures can utilize a single material (e.g., chalcogenide) process architecture and can have a respective value set within each memory cell by setting a logic high value in the memory cell with a positive signal (e.g., positive voltage, positive current) and by clearing the logic high value or setting a logic low value in the memory cell with a negative signal or lower voltage signal (e.g., negative voltage, negative current). During operation of memory 100, a single material process architecture may use a bipolar decoder (e.g., drive circuitry) to access the memory cells. In some cases, a unipolar decoder may be used, such as when the neutral midpoint between the positive and negative signal levels is shifted to equal half the voltage difference between the bit line 104 and the word line 106.

For ease of discussion, FIG. 1 may be discussed with respect to bit line 104, word line 106, word line decoder 108, and bit line decoder 110, but these designations are non-limiting. The scope of the present disclosure should be understood to cover memory cells 102 coupled to multiple access lines and accessed by respective decoders, where the access lines may be used to store data into and read data from the memory cells.

The bit line decoders 110 may be organized into groups of decoders. For example, the memory 100 may include a first set of bit line decoders 114 (e.g., a plurality of bit line decoders 110) and/or a second set of bit line decoders 116 (e.g., a different set of a plurality of bit line decoders 110). Similarly, the word line decoders 108 may also be arranged into multiple groups of word line decoders 108, such as a first group of word line decoders 118 and/or a second group of word line decoders 120. In various embodiments, a set of bit line decoders 114 and 116 and/or a set of word line decoders 118 and 120 may be referred to as decoder segments. Decoders may be used in combination with one another to drive memory cells 102 (e.g., paired and/or paired on either side of word lines 106 and/or bit lines 104). For example, bit line decoder 110-3 may operate in conjunction with bit line decoder 110'-3 and/or in conjunction with word line decoders 108-0, 108' -0 to select target memory cell 102-A. As can be appreciated herein, the decoder circuitry on either end of the word line 106 and/or bit line 104 may be different.

In some embodiments, to reduce or eliminate the occurrence of voltage spikes and/or current surges when selecting and/or accessing a target memory cell, thereby improving the operation of the memory 100, a spike mitigation scheme may be used between the bit lines 104, the word lines 106, and the respective word line decoders 108 and bit line decoders 110 when operating the memory 100. For example, when targeting memory cell 102-A, memory 100 may activate one or more resistors located near word line decoders 108-0 and 108'-0 and bit line decoders 110-3 and 110' -3 to mitigate the effects of possible voltage spikes of the respective decoders. The selection and location of the resistors may be discussed in further detail with reference to fig. 6-8. This may allow the desired voltage or current to be delivered to the memory cell while mitigating the deleterious effects of possible voltage/current spikes on the memory cell in the vicinity of the decoder.

Each of the bit lines 104 and/or word lines 106 may be metal traces disposed in the memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, and the like. Accordingly, the bit lines 104 and word lines 106 may have a uniform resistance per length and a uniform parasitic capacitance per length, such that the resulting parasitic load may increase uniformly per length. As such, the transmission path resistance of each of the memory cells 102 may be different relative to each of the word line decoder 108 and/or the bit line decoder 110 due, at least in part, to the difference in physical distance between the memory cells 102 and each of the associated decoding circuits. It should be noted that the depicted components of memory 100 may include additional circuitry not specifically depicted and/or may be disposed in any suitable arrangement. For example, subsets of the word line decoders 108 and/or the bit line decoders 110 may be disposed in the middle or at both ends of the bit lines 104 and/or the word lines 106 of the memory array 112, and/or on different physical sides of any plane that includes circuitry.

These parasitic effects may affect the driving of the decoding circuit when accessing the memory cell 102, as accessing (e.g., thresholding) a target memory cell of the memory cell 102 may include supplying a voltage and/or current to the target memory cell, such as the target memory cell 102-a. The non-uniform parasitic resistance between memory cells 102 may make driving selection of memory cells 102 difficult because signals received by relatively close memory cells may be larger than signals received by relatively far memory cells. Thus, conventional approaches may use relatively large signals when accessing far memory cells relative to the decoder. As such, the word line decoder 108 and/or the bit line decoder 110 may access the far memory cell by providing a higher voltage and/or current to adjust the voltage across the target memory cell (e.g., the target memory cell 102-A) to achieve the threshold voltage.

For example, a ground reference voltage may be provided on bit line 104-3, while a positive voltage is provided on word line 106-0, such that the voltage difference between the ground voltage and the positive voltage is greater than the threshold voltage. However, when the distance between the memory cells 102 causes the resistance of the transmission path taken by the signal (e.g., a particular length of the bit line and/or word line) to be inconsistent among the memory cells 102, some of the resulting transmission voltage and/or current provided to each of the memory cells 102 may vary based on the resistance of the transmission path used to transmit the signal. Accordingly, the memory 100 may include a transmission path resistance compensation scheme to allow for uniform provision and receipt of voltages between decoding circuitry (e.g., a subset of the word line decoders 108 and/or the bit line decoders 110) and different memory cells 102 of the memory 100, as described below with reference to fig. 3 and 4.

The memory 100 may also include control circuitry 122. The control circuitry 122 may be communicatively coupled to the respective word line decoder 108 and/or bit line decoder 110 to perform memory operations, such as by causing the decoding circuitry to generate or provide selection signals (e.g., selection voltages and/or selection currents) for selecting a target of a memory cell. In some embodiments, positive and negative voltages may be provided on one or more of bit lines 104 and/or word lines 106 to a target memory cell of memory cells 102. In some embodiments, the decoder circuit can provide electrical pulses (e.g., voltages and/or currents) to an access line that accesses a target memory cell. The electrical pulse may be a rectangular pulse, or in other embodiments, other shaped pulses may be used. In some embodiments, the voltage provided to the access lines may be a constant voltage.

Activating the decoder circuit may enable delivery of the electrical pulse to the target memory cell 102-a such that the control circuit 122 can access the data storage area of the target memory cell in order to read from or write to the data storage area. The control circuit 122 receives a control signal (e.g., a select input) that may determine which of the corresponding pair of bit line decoders 110 and/or word line decoders 108 is first activated. The control signal may be based on which of the bit line decoder 110 and the word line decoder 108 is physically farther and/or closer to the target memory cell 102-A. The relative physical distance from the decoder circuit to the target memory cell may be based on the memory address of the target memory cell. The order in which the decoder circuits are activated may be determined by various other logic (not shown) of the memory 100, such as control logic that receives address information.

After accessing the target memory cell 102-A, the data stored in the storage medium of the target memory cell may be read or written. Writing to the target memory cell may include changing a data value stored by the target memory cell. As previously discussed, the data value stored by a memory cell may be based on the threshold voltage of the memory cell. In some embodiments, a memory cell may be "set" to have a first threshold voltage, or may be "reset" to have a second threshold voltage. The set memory cell may have a lower threshold voltage than the reset memory cell. By setting or resetting the memory cells, different data values may be stored by the memory cells. Reading the target memory cell 102-A may include determining whether the target memory cell is characterized by a first threshold voltage and/or by a second threshold voltage. In this manner, the threshold voltage window may be analyzed to determine the value stored by the target memory cell 102-A. The threshold voltage window may be generated by applying programming pulses of opposite polarity to the memory cells 102 (e.g., specifically writing to the select/storage material (SD) of the memory cells) and reading the memory cells 102 (e.g., specifically reading the threshold voltages of the memory cells) using signals of a given (e.g., known) fixed polarity.

In some cases, to access the target memory cell 102-A, respective ones of the bit line decoder 110 and the word line decoder 108 that are farther from the target memory cell 102-A may be activated by the control circuit 122. For example, the bit line decoder and word line decoder furthest from the target memory cell 102-A (e.g., bit line decoder 110'-0 and word line decoder 108-3) may provide voltages via transmission paths characterized as large parasitic loads (e.g., having high resistance) due to the large physical distance between the target memory cell 102-A and the bit line decoder 110' -3 or word line decoder 108-3. A transmission path characterized by a larger parasitic load and/or resistance may reduce the effect of current spikes generated when accessing the target memory cell 102-a. Additionally or alternatively, after selecting the target memory cell 102-A, the control circuitry 122 may be operable to activate the bit line decoder and word line decoder closest to the target memory cell 102-A to cause current to be delivered to the target memory cell 102-A. The current may be the maximum current that can be provided by the decoder and/or associated with a given (e.g., known) fixed polarity for reading or writing to the SD material of the target memory cell 102-a. The delivery of current from the second decoder may occur after the snap back of memory cell 102-a.

FIG. 2 is a diagram illustrating a portion of a memory array 200 according to an embodiment of the present disclosure. The memory array 200 may be a cross-point array including word lines 106 (e.g., 106-0, 106-1, … …, 106-N) and bit lines 104 (e.g., 104-0, 104-1, … …, 104-M). A memory cell 102 may be located at each of the intersections of a word line 106 and a bit line 104. The memory cells 102 may function in a two-terminal architecture (e.g., where particular ones of the word lines 106 and bit lines 104 serve as electrodes for particular ones of the memory cells 102). It should be noted that the memory array 200 of figure 2 is by way of example and relates to a particular embodiment of the memory 100. Different memory array arrangements may be used in different embodiments of the present disclosure.

Each of the memory cells 102 may be a resistance variable memory cell, such as a Resistive Random Access Memory (RRAM) cell, a Conductive Bridging Random Access Memory (CBRAM) cell, a Phase Change Memory (PCM) cell, and/or a spin transfer torque magnetic random access memory (STT-RAM) cell, among other types of memory cells. Each of the memory cells 102 may include memory elements (e.g., memory material) and selector elements (e.g., select/memory material (SD)) and/or material layers that functionally replace the separate memory element layers and selector element layers. A selector element (e.g., SD material) may be disposed between a word line contact and a bit line contact associated with a word line or a bit line forming the memory cell 102. When a read or write operation is performed on the memory cell 102, an electrical signal may be transmitted between the word line contact and the bit line contact.

The selector element may be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, etc., or formed similarly to the underlying cell structure. In some examples, the selector element may include a selector material, a first electrode material, and a second electrode material. The memory elements of memory cell 102 may include memory portions (e.g., portions that are programmable to different states). For example, in a resistance variable memory cell, the memory element may include a portion of the memory cell having a resistance that is programmable to a particular level corresponding to a particular state in response to an applied programming voltage and/or current pulse. In some embodiments, memory cells 102 can be characterized as threshold type memory cells that are selected (e.g., activated) based on a voltage and/or current that crosses a threshold associated with a selector element and/or a memory element. Embodiments are not limited to the particular resistance variable material or materials associated with the storage elements of memory cell 102. For example, the resistance variable material may be a chalcogenide formed from various doped or undoped chalcogenide-based materials. Other examples of resistance variable materials that can be used to form the memory element include bimodal metal oxide materials, giant magnetoresistive materials, and/or various polymer-based resistance variable materials, among others.

In operation, the memory cell 102 may be programmed by applying a voltage (e.g., a write voltage) across the memory cell 102 via the selected word line 106 and bit line 104. A sensing (e.g., read) operation may be performed to determine the state of one or more memory cells 102 by sensing a current. For example, in response to a particular voltage applied to a selected one of the word lines 106 forming a respective memory cell 102, a current may be sensed on one or more bit lines 104 corresponding to the respective memory cell 102.

As illustrated, the memory array 200 may be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends in any direction (e.g., x-axis, y-axis, z-axis). The multi-level cross-point memory array 200 may include a plurality of consecutive memory cells (e.g., 102B, 102C) disposed between alternating (e.g., staggered) levels of bit lines 104 and word lines 106. The number of levels may increase or may decrease in number and should not be limited to the depicted volume or arrangement. Each of the memory cells 102 may be formed between a word line 106 and a bit line 104 (e.g., between two access lines) such that a respective one of the memory cells 102 may be directly electrically coupled (e.g., electrically coupled in series) with its respective pair of bit line 104 and word line 106, and/or formed from electrodes (e.g., contacts) made of respective portions of metal in the respective pair of bit line 104 and word line 106. For example, the memory array 200 may include a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 that may be accessed at a granularity as small as a single storage element and/or multiple storage elements for data operations (e.g., sensing and writing). In some cases, the memory array 200 may include more or fewer bit lines 104, word lines 106, and/or memory cells 102 than shown in the example of fig. 2.

It should be noted that the memory array 200 refers to certain embodiments of the present disclosure. The embodiments described below may be incorporated into the memory 100 using the memory array 200 or any other feasible memory array.

FIG. 3 depicts a portion of a decode circuit 300 that may be used in a particular embodiment of the memory 100 of FIG. 1, including the memory array 112 of FIG. 2. The decoding circuit 300 may be referred to as a bipolar decoder. The decoding circuit 300 may include a bit line decoder circuit 302 and a word line decoder circuit 304. The bit line decoder circuit 302 may be an embodiment of the bit line decoder 110 of FIG. 1, and the word line decoder circuit 304 may be an embodiment of the word line decoder 108 of FIG. 1. The bit line decoder circuit 302 and the word line decoder circuit 304 of the decoding circuit 300 may drive the bit lines 104-0 and 104-1, the word lines 106-0 and 106-1, and the memory cells 102-B, 102-C, 102-D, and 102-E of the memory array 200, as described in detail below.

The decoding circuit 300 may include a positive global bit line 306-A and a negative global bit line 306-B, which may drive a first local bit line 308 and a second local bit line 310. The decoding circuit 300 may also include a positive global word line 312-A and a negative global word line 312-B, which may drive a first local word line 314 and a second local word line 316 in the illustrated portion of the memory array 200. The secondary decoder circuit 318 or an external decoder may control global bit lines, such as global bit lines 306-A and 306-B or global word lines 312-A and 312-B. In addition, the level one decoder circuit 320 or the internal decoder may control a local bit line (e.g., the first local bit line 308 or the second local bit line 310) or a local word line (e.g., the first local word line 314 or the second local word line 316). In different embodiments, the secondary decoder circuit 318 and the primary decoder circuit 320 may be implemented using switching circuits (e.g., transistors).

In some embodiments, the global bit lines 306-A and 306-B may drive the first local bit line 308 and the second local bit line 310 differently, while in other embodiments other voltage configuration arrangements may be provided to the respective local bit lines. Moreover, other embodiments may use different circuit arrangements to drive respective memory cells 102 of memory 100.

In the illustrated embodiment of FIG. 3, the first local bit line 308 may drive the bit line 104-0 and the second local bit line 310 may drive the bit line 104-1 of FIG. 2. In addition, the first local word line 314 may drive the word line 106-0, and the second local word line 316 may drive the word line 106-1 of FIG. 2. That is, the first local bit line 308 and the first local word line 314 may enable access to the memory cell 102-B, the first local bit line 308 and the second local word line 316 may enable access to the memory cell 102-C, the second local bit line 310 and the first local word line 314 may enable access to the memory cell 102-D, and the second local bit line 310 and the second local word line 316 may enable access to the memory cell 102-E when directed by the control circuit 122.

It should be noted that the global bit line 306 and a portion of the global word line 312 are shown in the depicted portion of the decode circuit 300. For example, in some embodiments, each of the global bit lines 306 may drive 32 local bit lines, including a first local bit line 308 and a second local bit line 310. The global word line 312 may drive 32 local word lines, including a first local word line 314 and a second local word line 316. It should also be noted that the depicted portion of the decoding circuit 300 is one embodiment of the word line decoder 108 and/or the bit line decoder 110, and that other embodiments may be used in different embodiments of the described memory 100.

Fig. 4 is a side view illustrating a diagram of a portion of memory 100 of fig. 1, including memory array 200 and resistance compensation scheme 400 of fig. 2 in accordance with some embodiments of the present disclosure. When accessing a memory cell of the memory cells 102, the resistance compensation scheme 400 may include additional circuitry to add resistance and compensate for the transmission path resistance of the respective bit line and/or word line of the target memory cell 102-a. The resistance compensation scheme 400 can result in the same total resistance associated with accessing the target memory cell 102-a.

When accessing a target memory cell 102-A (not shown in FIG. 4), the resistance compensation scheme 400 may facilitate compensating the transmission path resistance of the bit line 104-3 by a compensation resistance on the respective word line 106-1. At the same time, the resistance compensation scheme 400 may facilitate compensating the transmission path resistance of the word line 106-1 by a compensation resistance on the bit line 104-3 associated with the target memory cell 102-A. In this manner, the resistance compensation scheme 400 may cause the total resistance across the memory cells 102 of the memory device 100 to be equal to the transmission path resistance associated with the full length of the bit line (e.g., bit line 104-3) in the bit line 104 and equal to the transmission path resistance of the full length of the word line (e.g., word line 106-1 of the memory device 100) in the word line 106. As such, the total resistance associated with the memory cell 102 of the resistance compensation scheme 400 may be predetermined and may be independent of the location of the memory cell in the memory 100.

The depicted portion of memory 100 in FIG. 4 may include word line sockets. Each word line socket may include/be coupled to a decoder coupled to a word line to access the memory cells. For example, a word line socket 402 may be coupled to the word line 106-1. The memory 100 may include additional sockets coupled to other word lines 106 and/or bit lines 104 not shown in fig. 4. Further, the sockets associated with the bit lines 104 may be positioned perpendicular to the word line sockets. Other circuitry of the socket 402 may be used when transmitting signals to access the memory cell 102.

The illustrated portion of the resistance compensation scheme 400 in FIG. 4 may include compensation resistors 404 disposed onto bit lines 104-3 between different decoder segments 406. In different embodiments, decoder segment 406 may include one or more decoding circuits, such as decoding circuit 300 of fig. 3. In other embodiments, different arrangements or architectures of decoding circuits and/or word lines may be used to drive the memory cells 102. Furthermore, the compensation resistor 404 may be implemented in any feasible form, such as a polymer-based resistive material or any resistive metal layer. Furthermore, the resistance compensation scheme 400 may be implemented passively. This may prevent undesirable parasitic loads from being placed on the memory 100.

In the depicted embodiment, each of the decoder segments 406 of FIG. 4 may include 4 secondary decoder circuits 318 to drive 4 global word lines. Further, each global word line may drive 32 primary decoder circuits 320, each coupled to a local word line. That is, each of the decoder segments 406 may include 128 local word lines to access memory cells 102 positioned on the respective 128 local word lines. In some embodiments, differential secondary decoder circuits and differential global word lines may be used to drive the primary decoder circuits and local word lines.

In some embodiments, when accessing a target memory cell, the compensation resistors 404 on respective ones of the bit lines 104 associated with the target memory cell may compensate for the transmission path resistance associated with respective ones of the word lines 106 associated with the target memory cell. Thus, the compensation resistor 404 on a word line may compensate for the transmission path resistance of the corresponding bit line.

In view of the foregoing, the resistance compensation scheme 400 may include a compensation resistor 404 coupled to the bit line 104 and the word line 106 of the memory 100. For example, in FIG. 4, the resistance compensation scheme 400 may include a compensation resistor 404 coupled to the bit line 104-3 to compensate for the transmission path resistance of the word line 106-1 when the target memory cell is accessed using the bit line 104-3 and the word line 106-1. In this embodiment, when accessing a memory cell, the resistance of bit line 104-3 can be calculated using the following equation. Rbl may be the transmission path resistance of the bit line segment between the bit line decoder and the memory cell. Rext may be the resistance added by compensation resistor 404 on bit line 104-3 to compensate for the transmission path resistance of word line 106-1. Rblmax may be equal to the resistance of the full length bit line.

Rext+Rbl＝Rblmax

The Rext resistance value may depend on the arrangement of the decoder segments 406 and the location of the word lines 106 in the memory array in different embodiments. Rext may be equal to the compensation resistor 404 of the corresponding bit line 104 or word line 106 connected in series to word line 106/bit line 104. For example, the word line 106-1 may be coupled to the socket 402 of the decoder segment 406-1, which may be coupled to the BL NEAR node of the bit line 104-3. In one example, word line 106-1 and bit line 104-3 may be used to access respective memory cells. In this example, Rext on bit line 104-3 may be equal to the series equivalent of compensation resistor 404-1 and compensation resistors 404-2, 404-3, 404-4, 404-5, and 404-6.

In another example, Rext on bit line 104-3 may be determined from the BL FAR node if word line 106 is coupled to the word line socket of decoder segment 406-2. That is, Rext may be equal to the series of compensation resistors 404-5 and 404-6. It should be noted that the compensation resistors shown on fig. 4 are with reference to a particular embodiment of the present disclosure, and that any suitable arrangement of compensation resistors 404 may be used on the bit lines and word lines of memory 100 in different embodiments.

The compensation scheme 400 may also include a compensation resistor 404 coupled to the bit line 104-3 to compensate for the transmission path resistance of the word line 106-1 that is not shown in the illustrated portion of FIG. 4. Again, Rext on word line 106-1 may be determined in the same manner.

The resistance compensation scheme 400 may apply a compensation resistance to the word line 106 and the bit line 104 using a compensation resistor 404. In some embodiments, the bit line transmission path resistance value may be inversely proportional to a respective compensation resistance value applied on a respective word line of the memory cell. Further, when accessing the memory cell, the word line transmission path resistance value may be inversely proportional to the respective compensation resistance value applied to the respective bit line. That is, the total resistance of each memory cell may include the transmission path resistance of the corresponding bit line, the corresponding word line compensation resistance applied by the compensation resistor 404, the transmission path resistance of the corresponding word line, and the bit line compensation resistance applied by the compensation resistor 404.

In a particular embodiment, the resistance compensation scheme 400 may cause each of the memory cells 102 to include the same total resistance value. Thus, due to the equal total resistance value of memory cells 102, memory 100 may use the same voltage and/or current to access different memory cells 102. Thus, each of the memory cells 102 may receive an equal voltage and/or current regardless of its physical distance to the respective decoder. In such embodiments, the decode circuitry may provide a voltage and/or current proportional to the voltage and/or current required to access the farthest of the memory cells 102 from the decode circuitry to access the rest of the memory cells 102.

FIG. 5 is a side view of an alternative embodiment 500 of the compensation resistor 404 on the bit line 104-3 of FIG. 4. The embodiment of fig. 5 may use a transistor 502 in place of the compensation resistor 404. The transistor 502 may be positioned on a bit line compensation bias line 504. The bit line compensation bias line 504 may provide a gate bias voltage to each of the transistors 502. Transistor 502 may impose a DC resistance on bit line 104-3 based at least in part on the provided gate bias voltage.

The transistors 502 may be positioned in series in the memory 100 along the remainder of the bit line 104 and on their respective bit line compensation bias lines (e.g., compensation bit line 504). This may allow the transmission path resistance of the word line 106 on the corresponding bit line 104 to be compensated using the transistor 502 when accessing the memory cell. Additionally, transistors 502 may be positioned in series in the memory 100 along the word lines 106 and on respective word line compensation bias lines (not shown in fig. 5). Thus, an alternative embodiment 500 of the resistance compensation scheme 400 may use transistors 502 disposed on compensation bias lines to compensate for the transmission path resistance of the respective bit lines 104 and the respective word lines 106 in the same manner as the resistance compensation scheme 400 of FIG. 4.

Fig. 6 depicts a portion of the memory 100 of fig. 1 including a portion of the spike mitigation circuit 600 and the decoding circuit 300. The illustrated portion of memory 100 includes a level one decoder circuit 320, a hooking metal 602, and a via 604. The hooking metal 602 may hook from the primary decoder circuit 320 to the via 604 to provide access to the memory cell 102 positioned on an opposite access line of the primary decoder circuit 320. The vias 604 may be coupled to different bit lines 104 or word lines 106 to facilitate accessing memory cells 102 having different electrical distances from the decoder circuit.

The spike mitigation circuit 600 may reduce the impact of rush currents and/or voltage spikes on the memory cells of the memory 100. The hooking metal 602 may include a higher resistance of the primary decoder circuit 320 near the decoding circuit 300. In different embodiments, the hooking metal 602 may comprise a high resistance material, a coupled external resistor, or both. In certain embodiments, the external resistor may be programmable to allow for resistance adjustment for different electrical distances. Additional resistance may be passively applied to the hooking metal 602. Specific embodiments relating to the resistance of the hooking metal 602 may be described below with respect to fig. 7 and 8.

The vias 604 may also include a high resistance material. Thus, the via 604 may reduce the effect of spike voltages of decoder circuits that are close to the near memory cell. Thus, the vias 604 may reduce the damaging effects (not shown in FIG. 6) of possible voltage spikes near the memory cells 102. Additional resistance may be passively applied to the vias 604.

In a particular embodiment, the spike mitigation circuit 600 and the resistance compensation scheme 400 may be incorporated onto the memory 100. As described above, the resistance compensation scheme 400 can cause a voltage and/or current to be provided that is proportional to the voltage and/or current required to access the farthest memory cell 102. In these embodiments, voltage spikes are more likely to occur. The spike mitigation circuit 600 can mitigate the damaging effects of voltages above the threshold on the near memory cell 102 through the resistance compensation scheme 400. It should be noted that the particular values of the hooking metal 602 and the via 604 may be adjusted according to different factors (e.g., the size of the memory 100) in different embodiments.

Furthermore, the illustrated primary decoder circuit 320, hooking metal 602, and vias 604 may be uniformly replicated across the other primary decoder circuits 320 of the memory 100. This may allow uniform spike mitigation across all decoders of decoder circuit 300 and/or memory 100.

Fig. 7 depicts a schematic diagram 700 that may be used in a first embodiment in connection with the spike mitigation circuit 600 of fig. 6. The schematic diagram 700 may include bit lines 104, word lines 106, and a decoding circuit 300 that includes a secondary decoder circuit 318 and a primary decoder circuit 320 coupled to word line 106-1. It should be noted that the schematic diagram 700 shows a single decode circuit 300 connected to the wordline 106-1, however, the schematic diagram may be used to drive the wordline 106 of the memory 100 by means of one or more decode circuits 300.

In a first embodiment of the spike mitigation circuit 600, a resistor 702 may be disposed between the word line 106-1 and the primary decoder circuit 320. When accessing a memory cell via the word line 106-1 and the bit line 104-1, the resistor 702 may apply resistance to the voltage spike to mitigate the damaging effects of the voltage spike on the near memory cell. In different embodiments, the hooking metal 602 or the via 604 may include a resistor 702 between the word line 106-1 and the primary decoder circuit 320.

Fig. 8 depicts a schematic diagram 800 that may be used in some embodiments related to the spike mitigation circuit 600 of fig. 6. The schematic diagram 800 may include bit lines 104, word lines 106, and a decoding circuit 300 that includes a secondary decoder circuit 318 and a primary decoder circuit 320 coupled to the word lines 106. The decoding circuit 300 may include a resistor 802 disposed between the primary decoder circuit 320 and the secondary decoder circuit 318. Further, the decoding circuit 300 may include a switch 804 that may enable or disable the effect of the resistor 802. The switch 804 may be programmable to bypass the resistor 802 or include the resistor 802 in the decoding circuit 300 when accessing memory cells on the word line 106-1.

For example, the switch 804 may be shorted to bypass the resistor 802 when a voltage associated with the decoding circuit 300 is below a threshold. Alternatively, the switch 804 may be opened to effectively dispose the resistor 802 in the decoding circuit 300 between the secondary decoder circuit 318 and the primary decoder circuit 320 when the voltage associated with the decoding circuit 300 is above a threshold. It should be noted that the use of one resistor 802 in the depicted embodiment of fig. 8 is by way of example, and that different numbers of resistors and switches may be used in different embodiments to effectively reduce the effects of spike voltages. It should be noted that the schematic diagram 800 shows a single decode circuit 300 connected to the wordline 106-1, however, the schematic diagram may be used to drive the wordline 104 of the memory 100 by means of one or more decode circuits 300.

In view of these technical effects, a plurality of memory devices may be included on a memory module, thereby enabling the memory devices to be communicatively coupled to the processing circuit as a unit. For example, a dual in-line memory module (DIMM) may include a Printed Circuit Board (PCB) and a plurality of memory devices. The memory module is communicatively coupled to a client device or a host device via a communication network in response to commands from the memory controller. Or in some cases, the memory controller may be used on the host side of the memory host interface; for example, a processor, microcontroller, Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or the like may each include a memory controller. Such a communication network may enable data communication therebetween, and thus, client devices utilize hardware resources that may be accessed by a memory controller. Based at least in part on user input to the client device, the processing circuitry of the memory controller may perform one or more operations to facilitate retrieval or transmission of data between the client device and the memory device. Data transferred between the client device and the memory device may be used for a variety of purposes, including, but not limited to, presenting visualizations, processing operations, calculations, or the like to a user through a Graphical User Interface (GUI) at the client device. Thus, in this regard, the above-described improvements to memory controller operations and memory write operations may manifest themselves as improvements in visualization quality (e.g., rendering speed, rendering quality), improvements in processing operations, improvements in computations, or the like.

The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

The techniques proposed and claimed herein refer to and apply to physical objects and concrete examples of a practical nature which arguably improve the technical field of the invention and which are therefore not abstract, intangible or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [ perform ] [ function ] … …" or "step for [ perform ] [ function ] … …", it is contemplated that such elements should be read in light of 35u.s.c.112 (f). However, for any claim containing elements specified in any other way, it is not intended that such elements be read in accordance with 35u.s.c.112 (f).