阅读说明：本技术 混合PiN结肖特基二极管及其P型欧姆接触的制备方法 (Hybrid PiN junction Schottky diode and preparation method of P-type ohmic contact of hybrid PiN junction Schottky diode ) 是由 季益静 吴贤勇 刘峰松 于 2021-08-24 设计创作，主要内容包括：本发明提供一种混合PiN结肖特基二极管及其P型欧姆接触的制备方法,该制备方法包括：提供叠层结构,由下向上依次包括N+衬底层及N-外延层,N-外延层包括有源区,有源区形成有至少一个P+离子注入区；于叠层结构表面沉积防护掩膜层；采用光刻刻蚀工艺刻蚀防护掩膜层,形成至少一个刻蚀窗口,刻蚀窗口仅显露与其对应的P+离子注入区；于上述结构的表面沉积金属层并对该金属层进行欧姆接触退火；去除防护掩膜层及防护掩膜层上的金属层。通过形成图形化防护掩膜层,在欧姆接触退火过程中,其可有效防止金属层熔融侧向流动至P+离子注入区之外的区域,所以不需要额外制备大面积的P+离子注入区,从而不需要牺牲正向导通面积；且工艺简单便于控制。(The invention provides a mixed Pin junction Schottky diode and a preparation method of a P-type ohmic contact thereof, wherein the preparation method comprises the following steps: providing a laminated structure which sequentially comprises an N + substrate layer and an N-epitaxial layer from bottom to top, wherein the N-epitaxial layer comprises an active region, and at least one P + ion implantation region is formed in the active region; depositing a protective mask layer on the surface of the laminated structure; etching the protective mask layer by adopting a photoetching process to form at least one etching window, wherein the etching window only exposes the P + ion implantation area corresponding to the etching window; depositing a metal layer on the surface of the structure and carrying out ohmic contact annealing on the metal layer; and removing the protective mask layer and the metal layer on the protective mask layer. By forming the graphical protection mask layer, the metal layer can be effectively prevented from being melted and flowing laterally to the region outside the P + ion injection region in the ohmic contact annealing process, so that the large-area P + ion injection region does not need to be prepared additionally, and the positive conduction area does not need to be sacrificed; and the process is simple and convenient to control.)

1. A preparation method of P-type ohmic contact of a hybrid PiN junction Schottky diode is characterized by comprising the following steps:

providing a laminated structure, wherein the laminated structure sequentially comprises an N + substrate layer and an N-epitaxial layer from bottom to top, the N-epitaxial layer comprises an active region, at least one P + ion implantation region is formed in the active region, and the P + ion implantation region is formed by implanting P-type doped ions into the N-epitaxial layer;

depositing a protective mask layer on the surface of the laminated structure;

etching the protective mask layer by adopting a photoetching process to form at least one etching window, wherein the etching window only exposes the P + ion injection region corresponding to the etching window;

depositing a metal layer on the surface of the structure and carrying out ohmic contact annealing on the metal layer;

and removing the protective mask layer and the metal layer on the protective mask layer to form an ohmic contact layer on the P + ion implantation area.

2. The method of claim 1, wherein the step of forming the etching window comprises:

forming a photoresist layer on the surface of the protective mask layer;

patterning the photoresist layer by adopting a photoetching process to form a photoetching window in the photoresist layer;

taking the photoresist layer as a mask, and etching the protective mask layer based on the photoetching window to form the etching window;

and removing the photoresist layer.

3. The method for preparing a P-type ohmic contact of a hybrid PiN-junction schottky diode according to claim 1, wherein: the N + substrate layer is made of 4H-SiC.

4. The method for preparing a P-type ohmic contact of a hybrid PiN-junction schottky diode according to claim 3, wherein: the metal layer is a single-layer structure of a nickel layer, a titanium layer or an aluminum layer, or the metal layer is a lamination of at least two layers of the nickel layer, the titanium layer and the aluminum layer; the annealing temperature for carrying out ohmic contact annealing on the metal layer is between 700 and 1000 ℃, and the annealing time is between 0.5 and 10 min.

5. The method for preparing a P-type ohmic contact of a hybrid PiN-junction schottky diode according to claim 1, wherein: the protective mask layer is a silicon dioxide layer.

6. The method for preparing a P-type ohmic contact of a hybrid PiN-junction schottky diode according to claim 1, wherein: the P + ion implantation regions are arranged in the N-epitaxial layer at intervals, and the number of the etching windows is equal to that of the P + ion implantation regions.

7. The method for preparing a P-type ohmic contact of a hybrid PiN-junction schottky diode according to claim 1, wherein: the N-epitaxial layer further comprises a terminal area surrounding the periphery of the active area, and a terminal protection structure is formed in the terminal area.

8. A method for preparing a mixed PiN junction Schottky diode, which is characterized by comprising the method for preparing the P-type ohmic contact of the mixed PiN junction Schottky diode according to any one of claims 1 to 7.

9. The method of claim 8, wherein the step of forming an ohmic contact layer on the P + ion implantation region further comprises:

depositing a passivation layer on the surface of the obtained structure, and carrying out photoetching on the passivation layer to expose the active region;

and depositing a Schottky metal on the surface of the active region and forming a Schottky contact with the N-epitaxial layer.

10. The method of making a hybrid PiN junction schottky diode of claim 9, wherein: the material of the schottky metal includes nickel, titanium or molybdenum.

Technical Field

The invention relates to the technical field of semiconductor chip manufacturing processes, in particular to a hybrid Pin junction Schottky diode and a preparation method of a P-type ohmic contact of the hybrid Pin junction Schottky diode.

Background

The power diode is a key component of a circuit system, and is widely applied to civil products such as high-frequency inverters, digital products, generators, televisions and the like and military occasions of various advanced weapon control systems and instrument and meter equipment such as satellites, receiving devices, missiles, airplanes and the like. Power diodes are expanding in two important directions: (1) the method develops to thousands of amperes or even tens of thousands of amperes, and can be applied to occasions such as high-temperature arc wind tunnels, resistance welding machines and the like; (2) the reverse recovery time is shorter and shorter, and the development is towards the ultra-fast, ultra-soft and ultra-durable direction, so that the reverse recovery circuit not only can be used in rectification occasions, but also has different functions in various switch circuits. In order to meet the application requirements of low power consumption, high frequency, high temperature, miniaturization and the like, the voltage resistance, the on-resistance, the turn-on voltage drop, the reverse recovery characteristic, the high-temperature characteristic and the like of the high-voltage power source are higher and higher.

Commonly used are conventional rectifier diodes, schottky diodes, PIN diodes (a P-I-N structure diode is a PIN diode formed by adding a thin layer of lightly doped Intrinsic (Intrinsic) semiconductor between P-type and N-type semiconductor materials). They are compared with each other and have the characteristics that: the schottky rectifier has a high speed switching characteristic suitable for applications with high operating frequencies, while the PIN fast recovery rectifier has a high voltage resistance with a small leakage current at high reverse voltages. In order to meet the application matching requirements of the fast switching device, the Schottky rectifier tube and the PIN rectifier tube are integrated, and the mixed Pin junction Schottky diode (namely the MPS diode) is developed, which not only has higher reverse blocking voltage, but also has very low on-state voltage drop, very short reverse recovery time, very small reverse recovery peak current and soft reverse recovery characteristic.

At present, in the process of manufacturing a front P-type ohmic contact metal of an MPS diode, the contact metal is melted and flows to a non-P ion implantation region due to an annealing process, and covers an N-type region, so that the reverse leakage of a device is increased, and even the reverse blocking voltage is reduced. Therefore, the conventional MPS manufacturing process needs to additionally manufacture a large area of P + ion implantation region, sacrifices the area of forward conduction, and has a small process window and is difficult to control.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a hybrid PiN junction schottky diode and a method for manufacturing a P-type ohmic contact thereof, which are used to solve the problems in the prior art that a P + region with a large area needs to be additionally manufactured to cover an N-type region and sacrifice a forward conduction area, and a process window becomes small and is difficult to control, in order to avoid the melting and flowing of a contact metal to a non-P ion implantation region due to an annealing process during the manufacturing process of a front P-type ohmic contact metal of an MPS diode.

In order to achieve the above objects and other related objects, the present invention provides a method for preparing a P-type ohmic contact of a hybrid PiN junction schottky diode, the method comprising:

providing a laminated structure, wherein the laminated structure sequentially comprises an N + substrate layer and an N-epitaxial layer from bottom to top, the N-epitaxial layer comprises an active region, at least one P + ion implantation region is formed in the active region, and the P + ion implantation region is formed by implanting P-type doped ions into the N-epitaxial layer;

depositing a protective mask layer on the surface of the laminated structure;

etching the protective mask layer by adopting a photoetching process to form at least one etching window, wherein the etching window only exposes the P + ion injection region corresponding to the etching window;

depositing a metal layer on the surface of the structure and carrying out ohmic contact annealing on the metal layer;

and removing the protective mask layer and the metal layer on the protective mask layer to form an ohmic contact layer on the P + ion implantation area.

Optionally, the specific step of forming the etching window includes:

forming a photoresist layer on the surface of the protective mask layer;

patterning the photoresist layer by adopting a photoetching process to form a photoetching window in the photoresist layer;

taking the photoresist layer as a mask, and etching the protective mask layer based on the photoetching window to form the etching window;

and removing the photoresist layer.

Optionally, the material of the N + substrate layer is 4H-SiC.

Further, the metal layer is a single-layer structure of a nickel layer, a titanium layer or an aluminum layer, or the metal layer is a lamination of at least two layers of the nickel layer, the titanium layer and the aluminum layer; the annealing temperature for carrying out ohmic contact annealing on the metal layer is between 700 and 1000 ℃, and the annealing time is between 0.5 and 10 min.

Optionally, the protective mask layer is a silicon dioxide layer.

Optionally, the P + ion implantation regions are spaced inside the N-epitaxial layer, and the number of the etching windows is equal to the number of the P + ion implantation regions.

Optionally, the N-epitaxial layer further includes a termination region surrounding the periphery of the active region, and a termination protection structure is formed in the termination region.

The invention also provides a preparation method of the mixed Pin junction Schottky diode, and the preparation method comprises any one of the preparation methods of the P-type ohmic contact of the mixed Pin junction Schottky diode.

Optionally, after forming the ohmic contact layer on the P + ion implantation region, the method further includes:

depositing a passivation layer on the surface of the obtained structure, and carrying out photoetching on the passivation layer to expose the active region;

and depositing a Schottky metal on the surface of the active region and forming a Schottky contact with the N-epitaxial layer.

Further, the material of the schottky metal includes nickel, titanium, or molybdenum.

As described above, according to the hybrid PiN junction schottky diode and the method for manufacturing the P-type ohmic contact thereof, the protective mask layer is formed and patterned, so that only the P + ion implantation region where the ohmic contact needs to be formed is exposed, and in the ohmic contact annealing process, the metal layer can be effectively prevented from being melted and flowing laterally to the region outside the P + ion implantation region, so that the large-area P + ion implantation region does not need to be additionally manufactured, and the forward conduction area does not need to be sacrificed; and the process is simple and convenient to control.

Drawings

Fig. 1 to 4 are schematic structural diagrams of steps in a process for manufacturing a hybrid PiN junction schottky diode in the prior art.

Fig. 5 is a schematic flow chart of a method for manufacturing a P-type ohmic contact of a hybrid PiN junction schottky diode according to the present invention.

Fig. 6 to 14 are schematic structural views showing steps in the process of manufacturing the P-type ohmic contact of the hybrid PiN junction schottky diode according to the present invention.

Fig. 15 and 16 are schematic structural diagrams showing steps in the process of manufacturing the hybrid PiN junction schottky diode according to the present invention.

Description of the element reference numerals

10. 20N + substrate layer

11. 21N-epitaxial layer

12. 24P + ion implantation region

120 large P + ion implantation area

13. 32 passivation layer

14 ohm metal

15. 26 Photoresist layer

16. 27 photo-etching plate

17. 22 active region

23 terminal area

25 protective mask layer

28 lithography window

29 etch window

30 metal layer

31 ohmic contact layer

18. 33 Schottky Metal

S1-S5

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation can be changed according to the actual requirement, and the layout of the components may be more complicated.

Example one

As shown in fig. 1 to 4, a process for manufacturing a hybrid PiN junction schottky diode in the prior art includes the following steps:

as shown in fig. 1, firstly, a stacked structure is provided, the stacked structure sequentially includes an N + substrate layer 10 and an N-epitaxial layer 11 from bottom to top, the N-epitaxial layer 11 includes an active region 17, at least one P + ion implantation region 12 is formed in the active region 17, the P + ion implantation region 12 includes at least one large P + ion implantation region 120, and the P + ion implantation region 12 is formed by implanting P-type doped ions into the N-epitaxial layer 11.

As shown in fig. 1, a passivation layer material is then deposited on the surface of the stacked structure, and the passivation layer material on the surface of the active region 17 is removed by a photolithography etching process, so as to form a passivation layer 13 on the surface of the termination region at the periphery of the active region 17.

As shown in fig. 1, an ohmic metal 14 is deposited on the surface of the stacked structure, and a photoresist layer 15 is lithographically deposited on the surface of the ohmic metal 14 based on a reticle 16; as shown in fig. 2, the ohmic metal 14 is then etched based on the patterned photoresist layer 15, the etching leaving only the ohmic metal 14 over the P + ion implantation region 12, e.g., leaving only the ohmic metal 14 over the large P + ion implantation region 120.

As shown in fig. 3, the patterned photoresist layer 15 is removed, and ohmic contact annealing is performed on the ohmic metal 14, so as to achieve ohmic contact between the ohmic metal 14 and the large P + ion implantation region 120.

Finally, as shown in fig. 4, a schottky metal 18 is deposited on the surface of the active region and schottky annealing is performed at a lower temperature to form a schottky contact between the schottky metal 18 and the N-epitaxial layer 11.

Because the ohmic contact annealing temperature is very high, sometimes thousands of degrees, the ohmic metal is easy to melt during the annealing process, and the flowing ohmic metal flows to a region outside the P + ion implantation region, for example, the surface of the N-epitaxial layer, so that the ohmic metal is in contact with the non-P + ion implantation region, which leads to increase of the reverse leakage of the device and even reduction of the reverse blocking voltage. To avoid this problem, as shown in fig. 1 and fig. 2, in the conventional MPS manufacturing process, in the process of forming the ohmic contact, a P + ion implantation region to be used for manufacturing the ohmic contact is usually made to be a large P + ion implantation region 120, so as to prevent the ohmic metal from melting and flowing out of the P + ion implantation region in the annealing process, but the method sacrifices a forward conduction area, so that the process window becomes smaller and the process is difficult to control, and simultaneously, the contact resistance of the device is also improved.

Based on research and analysis on the preparation process of the conventional mixed Pin junction Schottky diode, the inventor provides a preparation method of the P-type ohmic contact of the mixed Pin junction Schottky diode from the viewpoint of avoiding the molten flow of contact metal to a non-P + ion injection region in the ohmic contact annealing process, and the preparation method comprises the following steps:

as shown in fig. 5 and 6, step S1 is first performed to provide a stacked structure, where the stacked structure includes, in order from bottom to top, an N + substrate layer 20 and an N-epitaxial layer 21, the N-epitaxial layer 21 includes an active region 22, the active region 22 is formed with at least one P + ion implantation region 24, and the P + ion implantation region 24 is formed by implanting P-type dopant ions into the N-epitaxial layer 21.

As an example, the material of the N + substrate layer 20 may be selected from existing wafer materials suitable for manufacturing MPS devices, such as a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, and the like, and in this embodiment, the material of the N + substrate layer 20 is preferably 4H — SiC.

As an example, the material of the N-epitaxial layer 21 may be selected from existing epitaxial materials suitable for fabricating MPS devices. Based on the lattice matching and thermal matching between the N + substrate layer 20 and the N-epitaxial layer 21, the material of the N-epitaxial layer 21 is preferably the same as the material of the N + substrate layer 20, i.e. when the material of the N + substrate layer 20 is 4H-SiC, the material of the N-epitaxial layer 21 is preferably also 4H-SiC.

It should be noted that the characteristics of the schottky contact region and the ohmic contact region may vary depending on the specific application of the device. For example, some embodiments may include a single schottky contact region and one or more ohmic contact regions. While in other embodiments may include multiple schottky contact regions and multiple ohmic contact regions. In addition, the width of the schottky contact region and the width of the ohmic contact region may vary according to a desired function for the MPS diode and physical characteristics of material components of the MPS diode. These widths can also vary within a single MPS diode. In addition, when the MPS diode has a plurality of schottky contact regions and a plurality of ohmic contact regions, the P + ion implantation regions 24 are spaced apart inside the N-epitaxial layer 21, thereby subsequently forming a plurality of schottky contact regions and a plurality of ohmic contact regions.

As an example, the P + ion implantation region 24 may be formed by P-type doping ions to the N-epitaxial layer 21, and the P-type doping ions may be selected from conventional P-type doping ions, such as aluminum ions, boron ions, and the like.

As an example, the doping concentration values between the N + substrate layer 20 and the N-epitaxial layer 21 are relative, as long as the doping concentration of the N + substrate layer 20 is greater than the doping concentration of the N-epitaxial layer 21.

By way of example, the thickness of the N + substrate layer 20 is between 10 and 400 μm, and the doping concentration is 1E17/cm³～1E19/cm³To (c) to (d); the thickness of the N-epitaxial layer 21 is between 1 and 100 mu m, and the doping concentration is 1E14/cm³～1E17/cm³To (c) to (d); the implantation depth of the P + ion implantation region 24 is between 0.3 and 3 mu m, and the doping concentration is 1E16/cm³～1E22/cm³In the meantime.

As an example, the N-epitaxial layer 21 further includes a termination region 23 surrounding the periphery of the active region 22, and a termination protection structure is formed in the termination region 23. The terminal protection structure is an existing conventional terminal structure, and is not described herein in detail.

As shown in fig. 5 and 7, step S2 is performed to deposit a protective mask layer 25 on the surface of the stacked structure. The protective mask layer 25 is used to protect the non-P + ion implantation region during the subsequent ohmic contact annealing process, and prevent the ohmic metal from melting and flowing to the non-P + ion implantation region, for example, to the N-epitaxial layer 21.

As an example, the protective mask layer 25 may be formed by a CVD process, such as PECVD or LPCVD. The material of the protective mask layer 25 is selected to be suitable for a material that is not easily reacted with the ohmic metal during the ohmic contact annealing process, such as silicon dioxide or silicon nitride, and in this embodiment, silicon dioxide is preferred, and the thickness is between 0.5 μm and 2 μm.

As shown in fig. 5 and 12, step S3 is performed to etch the protection mask layer 25 by using a photolithography etching process to form at least one etching window 29, where the etching window 29 only exposes the corresponding P + ion implantation region 24, and the number of the etching windows 29 is not greater than the number of the P + ion implantation regions 24.

As an example, the number of the etching windows 29 is equal to the number of the P + ion implantation regions 24, but is not limited thereto, as shown in fig. 11 and 12, the number of the etching windows 29 may also be smaller than the number of the P + ion implantation regions 24, as shown in fig. 11, the number of the etching windows formed by subsequently etching the protection mask layer 25 is one, that is, smaller than the number of the P + ion implantation regions 24.

The protective mask layer 25 is patterned in the step, so that only a P + ion injection region needing to form ohmic contact is exposed, ohmic metal is protected in the subsequent ohmic contact annealing process, and due to the blocking effect of the protective mask layer, the ohmic metal can be prevented from being melted and flowing laterally to a region outside the P + ion injection region during annealing; and the process is simple and convenient to control.

As shown in fig. 8 to 12, as an example, the specific steps of forming the etching window include:

as shown in fig. 8, a photoresist layer 26 is first formed on the surface of the protective mask layer 25;

as shown in fig. 8-11, the photoresist layer 26 is then patterned using a photolithography process based on a reticle 27 to form a photolithography window 28 in the photoresist layer. It should be noted that the number of the lithography windows 28 corresponds to the number of the etching windows 29 to be formed subsequently, the number of the lithography windows 28 is selected according to the number of the ohmic contacts to be formed subsequently, the number of the lithography windows 28 is the same as the number of the P + ion implantation regions 24, but is not limited thereto, for example, the number (5) of the lithography windows 28 formed by the above-mentioned lithography process adopted in fig. 8 and 9 and the number (1) of the lithography windows 28 formed by the above-mentioned lithography process adopted in fig. 10 and 11 are smaller than the number (7) of the P + ion implantation regions 24;

as shown in fig. 9, 11 and 12, the photoresist layer 26 is used as a mask, and the protection mask layer 25 is etched based on the photoresist window 28 to form the etching window 29;

the photoresist layer 26 is finally removed as shown in fig. 12.

As shown in fig. 5 and 13, step S4 is performed to deposit a metal layer 30 on the surface of the structure and perform ohmic contact annealing on the metal layer 30.

Due to the existence of the patterned protective mask layer 25, in the ohmic contact annealing process, the metal layer 30 can be effectively prevented from laterally flowing to the region outside the P + ion implantation region in a melting manner, so that the large-area P + ion implantation region does not need to be additionally prepared, and the positive conduction area does not need to be sacrificed.

As an example, since a large area of P + ion implantation region does not need to be additionally prepared, all the P + ion implantation regions can be formed into ohmic contacts, so that the contact resistance of the device can be effectively reduced, and the anti-surge capability can be improved.

By way of example, when the N + substrate layer 20 is selected to be a 4H-SiC substrate, the metal layer 30 is generally selected to be a single-layer structure of a nickel layer, a titanium layer or an aluminum layer, or a stack of at least two layers of the nickel layer, the titanium layer and the aluminum layer, the annealing temperature of the ohmic contact annealing is between 700 ℃ and 1000 ℃, and the annealing time is between 0.5min and 10 min. In this embodiment, the metal layer 30 is preferably a three-layer stacked structure from bottom to top, in which the thickness of the nickel layer is between 0nm and 200nm, the thickness of the titanium layer is between 20nm and 200nm, and the thickness of the aluminum layer is between 0.2 μm and 1 μm, the annealing temperature of the ohmic contact annealing is 880 ℃, and the annealing time is 5 min.

As shown in fig. 5 and 14, step S5 is finally performed to remove the protection mask layer 25 and the metal layer 30 on the protection mask layer 25, so as to form an ohmic contact layer 31 on the P + ion implantation region 24.

As an example, when the material of the protective mask layer 25 is silicon dioxide, the protective mask layer 25 may be removed by using a silicon dioxide cleaning solution, and the metal layer 30 formed on the protective mask layer 25 is removed at the same time as the protective mask layer 25 is removed.

Example two

The embodiment provides a method for manufacturing a hybrid PiN junction schottky diode, which includes the method for manufacturing the P-type ohmic contact of the hybrid PiN junction schottky diode described in the first embodiment. The first embodiment is referred to for the achievement of the beneficial effects, and the detailed description is omitted.

As shown in fig. 15 and 16, for example, after forming the ohmic contact layer 31 on the P + ion implantation region 24, the method further includes:

as shown in fig. 15, depositing a passivation layer 32 on the surface of the resulting structure, and performing photolithography etching on the passivation layer 32 to expose the active region;

as shown in fig. 16, a schottky metal 33 is deposited on the surface of the active region and forms a schottky contact with the N-epitaxial layer 21.

As an example, the material of the schottky metal 33 may be selected to be nickel, titanium, or molybdenum.

In summary, the invention provides a hybrid PiN junction schottky diode and a method for manufacturing a P-type ohmic contact thereof, by forming a protective mask layer and patterning the protective mask layer, only a P + ion implantation region where ohmic contact needs to be formed is exposed, and in an ohmic contact annealing process, the protective mask layer can effectively prevent a metal layer from melting and laterally flowing to a region outside the P + ion implantation region, so that a large-area P + ion implantation region does not need to be additionally manufactured, and a forward conduction area does not need to be sacrificed; and the process is simple and convenient to control. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.