阅读说明：本技术 一种级联式高压变频器并联环流抑制方法 (Parallel circulating current restraining method for cascaded high-voltage frequency converter ) 是由 方汉学 刘兴状 朱海梅 荣凯 阮敬稳 郭延双 王玉娇 于 2021-09-08 设计创作，主要内容包括：本发明的级联式高压变频器并联环流抑制方法,主变频器将调制波发送给从变频器,定期同步主变频器与从变频器的载波,并通过相同的载波移相方式,使主变频器和从变频器中逆变单元的载波完全同步；主变频器、从变频器利用调制波与载波比较生成PWM信号,逆变单元利用PWM信号驱动逆变模块工作,使主变频器、从变频器输出的电压完全一致。本发明的级联式高压变频器并联环流抑制方法,主变频器周期性地下发调制波,并定期同步载波,保证了主变频器、从变频器输出的电压完全一致。通过在两变频器输出端连接三个均流电抗器上,起到了环流的进一步抑制作用,还解决了现有利用电抗器时所形成的电压损失。(According to the parallel circulating current restraining method of the cascaded high-voltage frequency converter, a main frequency converter sends a modulation wave to a slave frequency converter, carriers of the main frequency converter and the slave frequency converter are synchronized periodically, and the carriers of inversion units in the main frequency converter and the slave frequency converter are completely synchronized through the same carrier phase shifting mode; the main frequency converter and the slave frequency converter generate PWM signals by comparing the modulation waves with the carrier waves, and the inversion unit drives the inversion module to work by using the PWM signals, so that the voltages output by the main frequency converter and the slave frequency converter are completely consistent. According to the method for restraining the parallel ring current of the cascaded high-voltage frequency converter, the main frequency converter periodically sends down the modulation wave and periodically synchronizes the carrier wave, so that the voltages output by the main frequency converter and the secondary frequency converter are completely consistent. The output ends of the two frequency converters are connected with the three current sharing reactors, so that the further restraining effect of circulation is achieved, and the voltage loss formed when the reactors are utilized in the prior art is also solved.)

1. A cascade connection type high-voltage frequency converter parallel connection circumfluence restraining method comprises two high-voltage frequency converters, wherein an inversion unit for inverting direct current into alternating current signals is arranged in each high-voltage frequency converter, and an inversion module is arranged in each inversion unit; the two high-voltage frequency converters are respectively defined as a main frequency converter (1) and a slave frequency converter (2), and the main frequency converter and the slave frequency converter are connected through a communication line; the method is characterized in that the method for restraining the parallel circulation of the cascade high-voltage frequency converter comprises the following steps: the main frequency converter sends the modulated wave to the slave frequency converter, periodically synchronizes the carrier waves of the main frequency converter and the slave frequency converter, and completely synchronizes the carrier waves of the inversion units in the main frequency converter and the slave frequency converter through the same carrier phase shifting mode; the main frequency converter and the slave frequency converter generate PWM signals by comparing modulation waves with carrier waves, the PWM signals are sent to respective inversion units through timing communication, the inversion units drive the inversion modules to work by the PWM signals, PWM waveforms output by the inversion units at the same positions of the main frequency converter and the slave frequency converter are completely consistent, and therefore the PWM waveforms output by the main frequency converter and the slave frequency converter are completely consistent, namely the voltages output by the main frequency converter and the slave frequency converter are completely consistent.

2. The method for restraining the parallel ring current of the cascaded high-voltage frequency converter according to claim 1, wherein a period of transmitting PWM signals to an inverter unit from a master frequency converter and a slave frequency converter is T, and the period is called a unit communication period; the cascade high-voltage frequency converter parallel loop current suppression method is specifically realized by the following steps:

a) issuing a carrier wave, issuing the calculated modulation wave to a slave frequency converter by a master frequency converter by taking an integral multiple n T of a unit communication period as a period, and simultaneously loading the modulation wave, wherein n T is the communication period of the master frequency converter and the frequency converter, and n is a positive integer more than or equal to 2;

b) generating PWM signals, comparing the modulated waves with carriers by the main frequency converter and the auxiliary frequency converter to generate the PWM signals, sending the PWM signals to respective inversion units according to a period T, and controlling the output of each inversion unit;

c) issuing a synchronous signal, issuing a carrier phase synchronous signal by the main frequency converter by taking an integral multiple m × n × T of a communication period of the main frequency converter and the slave frequency converter as a period, and calculating communication delay, wherein m is a positive integer more than or equal to 2;

d) synchronizing carrier, the slave frequency converter receives the carrier phase synchronizing signal and then carries out carrier synchronization, and the master frequency converter ensures that the master frequency converter and the slave frequency converter carry out carrier synchronization at the same time by calculating communication delay;

the carrier synchronization method comprises the following steps: firstly, calculating a phase shift angle value of a first inversion unit, and calculating phase shift angles of the rest inversion units relative to the first inversion module according to the carrier frequency and the number of the inversion modules; when the carrier of the first inversion module crosses zero, the carrier of each inversion unit is forced to be assigned to the calculated phase shift angle value, so that the phase synchronization of the carriers of the inversion units at the same position of the main frequency converter and the slave frequency converter is achieved, and the consistency of PWM signals output after the modulated waves are compared with the carriers is ensured.

3. The method for restraining parallel loop current of the cascaded high-voltage frequency converter according to claim 1 or 2, is characterized in that: the main frequency converter and the slave frequency converter are connected with three current sharing reactors (3), the three-phase output of the main frequency converter is U1, V1 and W1, the three-phase output of the slave frequency converter is U2, V2 and W2, U1, U2, V1, V2, W1 and W2 are respectively connected to two ends of the input side of the same current sharing reactor, and the output sides of the three current sharing reactors form a three-phase output signal U, V, W.

4. The method for restraining parallel loop current of the cascaded high-voltage frequency converter according to claim 2, is characterized in that: in order to prevent the carrier phase deviation caused by the clock difference of the master frequency converter and the slave frequency converter, the carrier synchronization is synchronized once in each carrier period; the carrier wave period is integral multiple of the communication period of the main frequency converter and the slave frequency converter.

5. The method for restraining parallel loop current of the cascaded high-voltage frequency converter according to claim 1 or 2, is characterized in that: the control system of the main frequency converter directly collects voltage and current data during self operation, obtains the voltage and current data of the slave frequency converter in a communication mode, and calculates the required modulation wave according to the obtained voltage and current data.

Technical Field

The invention relates to a method for restraining parallel circulation of a cascaded high-voltage frequency converter, in particular to a method for restraining parallel circulation of a cascaded high-voltage frequency converter.

Background

The application of the frequency converter to the speed regulation of the motor is more and more extensive; the power of the motor is very high in some occasions, and the frequency converter is difficult to realize high power due to factors such as power devices, manufacturing process, production cost and the like; therefore, the output power is increased by connecting the frequency converters in parallel.

At present, most of the domestic high-voltage frequency converter topology adopts multi-unit cascade connection, direct current buses cannot be directly connected in parallel, and therefore, a mode of connecting the whole frequency converter in parallel is adopted; the frequency converters are used as voltage source outputs and are directly connected in parallel to generate larger circulation, so that part of the frequency converters are designed to increase reactors at the output of the whole machine to inhibit the circulation between the two frequency converters; the voltage output by the frequency converter is PWM waveform, the circulation current is restrained by simply adding the reactor, the circulation current is difficult to be eliminated fundamentally, and in addition, the reactor generates certain voltage drop during working, so the loss of the output voltage of the frequency converter is caused.

Disclosure of Invention

In order to overcome the defects of the technical problems, the invention provides a method for restraining parallel ring current of a cascaded high-voltage frequency converter.

The invention relates to a method for restraining parallel circulation of cascaded high-voltage frequency converters, which comprises two high-voltage frequency converters, wherein an inversion unit for inverting direct current into alternating current signals is arranged in each high-voltage frequency converter, and an inversion module is arranged in each inversion unit; the two high-voltage frequency converters are respectively defined as a main frequency converter and a slave frequency converter, and the main frequency converter and the slave frequency converter are connected through a communication line; the method is characterized in that the method for restraining the parallel circulation of the cascade high-voltage frequency converter comprises the following steps: the main frequency converter sends the modulated wave to the slave frequency converter, periodically synchronizes the carrier waves of the main frequency converter and the slave frequency converter, and completely synchronizes the carrier waves of the inversion units in the main frequency converter and the slave frequency converter through the same carrier phase shifting mode; the main frequency converter and the slave frequency converter generate PWM signals by comparing modulation waves with carrier waves, the PWM signals are sent to respective inversion units through timing communication, the inversion units drive the inversion modules to work by the PWM signals, PWM waveforms output by the inversion units at the same positions of the main frequency converter and the slave frequency converter are completely consistent, and therefore the PWM waveforms output by the main frequency converter and the slave frequency converter are completely consistent, namely the voltages output by the main frequency converter and the slave frequency converter are completely consistent.

The invention relates to a parallel circulating current suppression method of a cascaded high-voltage frequency converter, which is characterized in that the period of issuing PWM (pulse width modulation) signals to an inversion unit from a main frequency converter and a slave frequency converter is set as T and is called as a unit communication period; the cascade high-voltage frequency converter parallel loop current suppression method is specifically realized by the following steps:

a) issuing a carrier wave, issuing the calculated modulation wave to a slave frequency converter by a master frequency converter by taking an integral multiple n T of a unit communication period as a period, and simultaneously loading the modulation wave, wherein n T is the communication period of the master frequency converter and the frequency converter, and n is a positive integer more than or equal to 2;

b) generating PWM signals, comparing the modulated waves with carriers by the main frequency converter and the auxiliary frequency converter to generate the PWM signals, sending the PWM signals to respective inversion units according to a period T, and controlling the output of each inversion unit;

c) issuing a synchronous signal, issuing a carrier phase synchronous signal by the main frequency converter by taking an integral multiple m × n × T of a communication period of the main frequency converter and the slave frequency converter as a period, and calculating communication delay, wherein m is a positive integer more than or equal to 2;

d) synchronizing carrier, the slave frequency converter receives the carrier phase synchronizing signal and then carries out carrier synchronization, and the master frequency converter ensures that the master frequency converter and the slave frequency converter carry out carrier synchronization at the same time by calculating communication delay;

the carrier synchronization method comprises the following steps: firstly, calculating a phase shift angle value of a first inversion unit, and calculating phase shift angles of the rest inversion units relative to the first inversion module according to the carrier frequency and the number of the inversion modules; when the carrier of the first inversion module crosses zero, the carrier of each inversion unit is forced to be assigned to the calculated phase shift angle value, so that the phase synchronization of the carriers of the inversion units at the same position of the main frequency converter and the slave frequency converter is achieved, and the consistency of PWM signals output after the modulated waves are compared with the carriers is ensured.

The invention relates to a method for restraining parallel loop current of a cascaded high-voltage frequency converter, wherein a main frequency converter and a slave frequency converter are connected with three current sharing reactors, the three-phase output of the main frequency converter is U1, V1 and W1, the three-phase output of the slave frequency converter is U2, V2 and W2, U1, U2, V1, V2, W1 and W2 are respectively connected to two ends of the input side of the same current sharing reactor, and the output sides of the three current sharing reactors form a three-phase output signal U, V, W.

The invention relates to a parallel circulating current restraining method of a cascaded high-voltage frequency converter, which aims to prevent carrier phase deviation caused by clock difference of a main frequency converter and a slave frequency converter, wherein carrier synchronization is synchronized once in each carrier period; the carrier wave period is integral multiple of the communication period of the main frequency converter and the slave frequency converter.

According to the parallel circulating current restraining method of the cascaded high-voltage frequency converter, the control system of the main frequency converter directly collects voltage and current data during self operation, obtains the voltage and current data of the slave frequency converter in a communication mode, and calculates the required modulation wave according to the obtained voltage and current data.

The invention has the beneficial effects that: the main frequency converter and the slave frequency converter are connected through a communication line, the main frequency converter periodically issues a modulation wave to the slave frequency converter and periodically issues a carrier synchronization signal to realize carrier synchronization of the main frequency converter and the slave frequency converter, so that PWM waveforms output by inversion units at the same position of the main frequency converter and the slave frequency converter are completely consistent, and the voltages output by the main frequency converter and the slave frequency converter are also completely consistent.

Furthermore, the output ends of the main frequency converter and the slave frequency converter are connected to the three current sharing reactors, so that the effect of restraining the circulation current when the main frequency converter and the slave frequency converter output voltage differences is achieved, and the voltage loss formed by using the reactors in the prior art is solved.

Drawings

Fig. 1 is a schematic diagram of a cascaded high-voltage inverter according to the present invention;

FIG. 2 is a waveform diagram of carrier waves of each inversion unit in the present invention;

FIG. 3 is a waveform diagram of the output of the cascaded high voltage inverter of the present invention;

FIG. 4 is a current waveform diagram of two frequency converters and system output when the prior art has no circulating current suppression;

fig. 5 is a waveform diagram of two frequency conversions and the current output by the system when the method of the present invention is used for circulating current suppression.

In the figure: 1 main frequency converter, 2 slave frequency converters and 3 current sharing reactors.

Detailed Description

The invention is further described with reference to the following figures and examples.

As shown in fig. 1, a schematic diagram of a cascaded high-voltage frequency converter of the present invention is provided, which includes two high-voltage frequency converters, respectively including a main frequency converter 1 and a slave frequency converter 2, where the main frequency converter 1 and the slave frequency converter 2 are connected by communication; the control system of the main frequency converter 1 collects the running current and voltage data of the self frequency converter, collects the current and voltage data of the slave frequency converter 2 through communication and other modes, and calculates the modulation wave to be output, wherein the modulation wave is used for generating the PWM signal of the power unit of the self frequency converter and the PWM signal of the power unit of the other frequency converter.

The main frequency converter 1 sends the calculated modulated wave to the slave frequency converter 2, loads the modulated wave at the same time, periodically synchronizes the carriers of the two frequency converters, and completely synchronizes the carriers of each unit in the same carrier phase shifting mode; the modulation wave is compared with the carrier wave to generate a PWM signal, the control system sends the PWM signal to the inversion unit through timing communication, and the inversion unit drives the inversion module according to the PWM signal; the inversion units at the same positions of the two frequency converters output PWM waveforms completely consistent, so that the PWM waveforms output by the two complete machines are ensured to be completely consistent, and the output voltages are consistent. As shown in fig. 3, a waveform diagram of the output of the cascaded high-voltage frequency converter of the present invention is shown.

The master frequency converter 1 sends data to the slave frequency converter 2 in a timing mode, wherein the data comprise modulation waves and carrier synchronization signals; the main frequency converter 1 calculates the transmission time of communication data, and updates the modulation wave and the synchronous signal simultaneously with the slave frequency converter 2; the modulated wave is updated every communication cycle, and the carrier synchronization signal is transmitted once in a plurality of cycles.

The period of sending PWM signals to the inversion unit from the main frequency converter and the slave frequency converter is set as T, and the period is called a unit communication period. And the main frequency converter issues the calculated modulation wave to the slave frequency converter by taking integer multiple n × T of the unit communication period as the period, and loads the modulation wave at the same time, wherein n × T is the communication period of the main frequency converter and the frequency converter, and n is a positive integer more than or equal to 2. The main frequency converter issues carrier phase synchronous signals by taking integral multiple m x n x T of the communication period of the main frequency converter and the slave frequency converter as a period, and calculates communication delay, wherein m is a positive integer larger than or equal to 2.

After receiving the synchronous signal from the frequency converter 2, forcibly assigning the carrier to a fixed value, simultaneously calculating the communication data receiving delay of the frequency converter 2 by the main frequency converter 1, and forcibly assigning the carrier to the same fixed value at the same time; then, the carrier synchronization between the main frequency converter 1 and the slave frequency converter 2 can be ensured; in order to prevent carrier phase offset caused by clock difference of a control system of the master frequency converter and the slave frequency converter 2, the synchronization mode is synchronized once in each carrier period; the carrier wave period must therefore be an integer multiple of the communication period.

The synchronization between the master frequency converter 1 and the slave frequency converter 2 is only the carrier of the first synchronous inversion unit, the carriers of other inversion units can calculate the phase shift relative to the first inversion unit according to the carrier frequency and the number of the inversion units, and the zero crossing point of the carrier of the first inversion unit is assigned to the phase shift angle value in a forced mode, so that the carrier synchronization of all the inversion units of the master frequency converter 1 and the slave frequency converter 2 can be achieved. As shown in fig. 2, a carrier waveform diagram of each inversion unit in the present invention is shown.

The modulation wave is compared with the carrier wave to generate a PWM signal, the PWM signal is sent to a power inversion unit at regular time, and the inversion unit drives an inversion module according to the PWM signal to output a corresponding PWM waveform; in order to ensure that the phases of the output waveforms of the main frequency converter 1 and the slave frequency converter 2 are consistent, the PWM signals are set to be sent to the inversion unit at the zero crossing point of the carrier wave at fixed time, so that the delay time of the PWM signals received by the inversion unit is ensured to be consistent; therefore, the communication frequency from the main control system to the inverter unit is required to be integral multiple of the carrier frequency.

Due to differences of devices, the output waveforms of the master frequency converter 1 and the slave frequency converter 2 cannot be completely consistent; therefore, a flow restriction means must be added to prevent the generation of the circulating current; the three-phase output of the main frequency converter 1 and the three-phase output of the slave frequency converter 2 are respectively connected in parallel through a current sharing reactor, the current sharing reactor comprises an iron core and two coils which have the same number of turns and are opposite in winding direction, and magnetic fields generated by the two coils are mutually offset when two branch currents output by the frequency converters are consistent through magnetic coupling of the iron core; when the currents of the two branches output by the frequency converter are inconsistent, the two coils respectively generate a counter electromotive force on the coil of the opposite side, and the counter electromotive force enables the potential difference between the two branches to be almost zero, so that the effect of restraining the circulating current is achieved. Therefore, the current sharing reactor solves the problem of circulation, and the loss of the output voltage of the frequency converter can not be caused under the normal condition;

as shown in fig. 4, a current waveform diagram output by two frequency converters and a system when the existing loop current is not restrained is given, fig. 5 is a current waveform diagram output by two frequency converters and a system when the loop current restraining method of the invention is adopted, the upper two waveform diagrams are a current waveform diagram output by a main frequency converter 1 and a secondary frequency converter 2, and the lower one is a voltage waveform diagram output by a secondary side of a current sharing reactor 3.